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Each memory cell can hold one bit of information. Memory cells are organized in the form of an array. One row is one memory word.

All cells of a row are connected to a common line, known as the “wordline”.

Word line is connected to the address decoder. Sensewrite circ!its are connected to the data in"!to!t"!t lines of the

memory chi".

#ead o"eration $ Address gi%en to AoA&A'A(, #W) *&, sense circ!it Write o"eration $ Address gi%en to AoA&A'A(, data in write circ!it,

#W) *+

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FF

circuitSense / Write

Address

decoder

FF

CS

cellsMemory

circuitSense / Write Sense / Write

circuit

Data input /output lines:

A0

A1

A2

A3

W0

W1

W15

7 1   0

WR / 

7   1 0

b7   b1   b0

•••

•••

•••

•••

•••

•••

•        •        •        

•        •        •        

•        •        •        

16 x 8 organization

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•  &'- organization re!ires &/ e-ternal connection

• &0 - & organization re!ires &1 e-ternal connection

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 Two types

Static RAM (SRAM)

Dynamic RAM (DRAM)

Asynchronous DRAM (ADRAM)

Synchronous DRAM(SDRAM)

▪ Double Data Rate SDRAM

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Static #AMs 2S#AMs3$ 4onsist of circ!its that are ca"able of retaining their state as

long as the "ower is a""lied.

5olatile memories, beca!se their contents are lost when "ower is interr!"ted.

Access times of static #AMs are in the range of fewnanoseconds.

6owe%er, the cost is !s!ally high.

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7wo transistor in%erters are cross connected to im"lement a basic fli"8flo".

7he cell is connected to one word line and two bits lines bytransistors 7& and 7'

When word line is at gro!nd le%el, the transistors are t!rned offand the latch retains its state

Y  X 

Word line

Bit lines

b

T  2T 1

b ′

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#ead o"eration$

word line is acti%ated to close switches 7& and 7'.

SenseWrite circ!its at the bottom monitor the state

of b and b9Write o"eration $

7he state of the cell is "lacing on bit line b and itscom"lement on b9,

acti%ating the wordline.

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7ransistor 27(,71 : 7;,7 is maintained high

 by ha%ing transistors 7( and 7< on.

?ower s!""ly, s!""ly is 15(.(5.

=f "ower is interr!"ted, the cell9s contents will be

lost.

6ence S#AMs are %olatile.

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 AdvantageLow power consumption.

ery less access time in terms o!nanoseconds.

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@o not retain their state indefinitely #easonable cost when com"ared to S#AMs. =nformation is stored in the form of a charge on a

ca"acitor. 7his charge can be maintained for onlytens of milliseconds.

6ence the contents are to be "eriodically refreshed2i.e. restoring the ca"acitor to its f!ll %al!e3 to store

the %al!e for a longer time. 4ontents may be refreshed while accessing them for

reading.

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 Two types o! DRAMs

Asynchronous DRAM

Synchronous DRAM

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Write Operation

7 is t!rned on, and an a""ro"riate %oltage is a""lied to the bit line. 7his ca!ses the ca"acitor to "osses some charge.

After the transistor is t!rned off, the ca"acitor begins todischarge 2d!e to ca"acitor9s leakage resistance3

6ence the information stored in the cell can be retrie%edcorrectly, only if it is read before the ca"acitor9s chargedro"s below some threshold %al!e.

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Read Operation

7he transistor is t!rned on.

A Sense Am"lifier connected to the bit line detects whether

the charge on the ca"acitor is abo%e threshold %al!e.  =f so, the bit line is dri%en to f!ll %oltage to re"resents the

logic %al!e &.

=f the charge detected by sense Am"lifier is below

threshold, the bit line is "!lled to gro!nd le%el re"resentingno charge.

#eading a!tomatically refreshes the cell.

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Each row can store 1&' bytes.&' bits to select a row, and / bits to select a gro!" in a row.7otal of '& bits.

Birst a""ly the row address,#AS signal latches the rowaddress. 7hen a""ly the col!mnaddress, 4AS signal latches theaddress.

7iming of the memory !nit iscontrolled by a s"ecialized !nitwhich generates #AS and

4AS. 7his is asynchrono!s @#AM

Column

CSSense /

Writecircuits

cell arraylatchaddressRow

Column

latch

decoderRow

decoderaddress

4096 512 8×( )×

R/W

A20 9-   A8 0- ⁄ 

D0D7

RAS

CAS

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Suppose i! we want to access the consecutivebytes in the selected row.

 This can be done without having to reselectthe row. Add a latch at the output o! the sense circuits in each row. All the latches are loaded when the row is selected. Di"erent column addresses can be applied to select and place

di"erent bytes on the data lines. #onsecutive se$uence o! column addresses

can be applied under the control signal #AS%

without reselecting the row. Allows a bloc& o! data to be trans!erred at a much !aster rate than

random accesses. A small collection'group o! bytes is usually re!erred to as a bloc&.

 This trans!er capability is re!erred to as the!ast page mode !eature.

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R/ W

RAS

CAS

CS

Clock 

Cell arraylatch

addressRow

decoderRow

decoder

Column   Read/Writecircuits & latches

counteraddressColumn

Row/Column

address

Data inputregister

Data outputregister

Data

Refreshcounter

Mode register

andtiming control

•Operation is directly synchronizedwith processor clock signal.•The outputs of the sense circuitsconnected to a latch.•During a Read operation, thecontents of the cells in a row are

loaded onto the latches.•During a refresh operation, thecontents of the cells are refreshedwithout changing the contents of  the latches.•Data held in the latches correspoto the selected columns are transf 

to the output.•For a burst mode of operation,successive columns are selected ucolumn address counter and clock.!" signal need not be generatede#ternally. ! new data is placed d

raising edge of the clock 

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Memory latency is the time it ta&es totrans!er a word o! data to or !rommemory

Memory bandwidth is the number o!bits or bytes that can be trans!erred inone second.

DDRSDRAMs #ell array is organied in two ban&s

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19-bit internal chip address

decoder2-bit

addresses21-bit

A0

A1

A19

 memory chip

A20

D31-24

  D7-0

D23-16

  D15-8

512K 8×

Chip select

 memory chip

19-bitaddress

512K 8×

8-bit datainput/output

$mplement a memory unit of %&words of '% bits each.(se )*%#+ static memory chips.ach column consists of - chips.ach chip implements one byte

 position.

 ! chip is selected by setting itschip select control line to *."elected chip places its data on thdata output line, outputs of otherchips are in high impedance state.%* bits to address a '%bit word./igh order % bits are needed toselect the row, by activating thefour hip "elect signals.*0 bits are used to access speci1cbyte locations inside the selectedchip.

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Large dynamic memory systems can beimplemented using DRAM chips in a similar wayto static memory systems.

lacing large memory systems directly on themotherboard will occupy a large amount o!space. Also% this arrangement is in*e+ible since the memory system cannot be e+panded

easily.  ac&aging considerations have led to the

development o! larger memory units &nown as

S,MMs (Single ,n-line Memory Modules) andD,MMs (Dual ,n-line Memory Modules).  Memory modules are an assembly o! memory

chips on a small board that plugs vertically ontoa single soc&et on the motherboard. ccupy less space on the motherboard.

Allows !or easy e+pansion by replacement.

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Recall that in a dynamic memory chip% to reducethe number o! pins% multiple+ed addresses areused.

Address is divided into two parts/ 0igh-order address bits select a row in the array.

 They are provided 1rst% and latched using RAS signal.

Low-order address bits select a column in the row.

 They are provided later% and latched using #AS signal. 0owever% a processor issues all address bits at

the same time. ,n order to achieve the multiple+ing% memory

controller circuit is inserted between theprocessorand memory. 

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23

Processor

RAS

CAS

R/ W

Clock 

Address

Row/Columnaddress

Memorycontroller

R/ W

Clock 

Request

CS

Data

Memory