UNIT 3 - chettinadtech.ac.inchettinadtech.ac.in/storage/12-06-28/12-06-28-11-58-42-1553... · Some...
Transcript of UNIT 3 - chettinadtech.ac.inchettinadtech.ac.in/storage/12-06-28/12-06-28-11-58-42-1553... · Some...
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UNIT 3 THE PENTIUM MICROPROCESSOR
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THE PENTIUM MICROPROCESSOR
Contents Introduction
The software model of the Pentium
Pentium processor registers
Data organization
Instruction types
Addressing modes
Pentium instructions
Interrupt processing
Programming the Pentium
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OBJECTIVES
In this unit will be learn about:
Introduction to Pentium microprocessor
Real mode and protected mode operation
The register set of the Pentium
The addressing capabilities and data types that may be used
The different addressing modes and instruction types available
The usefulness of interrupts
Some of differences between the 8086 and the 80286,80386,80486,and
Pentium microprocessors
Introduction to Pentium
Pentium is a registered trademark that is included in the brand names of
many of Intel's x86-compatible microprocessors, both single- and multi-core. The
name Pentium was derived from the Greek pente, meaning 'five', and the Latin
ending -ium, a name selected after courts had disallowed trade marking of number
based names like "i586" or "80586" (model numbers cannot always be
trademarked).
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Intel filed a U.S. trademark for the name 'Pentium' on July 2, 1992, more than 8
months before the public release of the first Pentium microprocessor, with the
description 'computer hardware; namely, microprocessors'. Following Intel's
previous series of 8086, 80186, 80286, 80386, and 80486 microprocessors, Intel's
fifth-generation micro architecture, the P5, was first released under the Pentium
brand on March 22, 1993
A Brief History of the Pentium Processor Family
The Pentium family of processors, which has its roots in the Intel486(TM)
processor, uses the Intel486 instruction set (with a few additional instructions). The
term ''Pentium processor'' refers to a family of microprocessors that share a
common architecture and instruction set. The first Pentium processors (the P5
variety) were introduced in 1993. This 5.0-V processor was fabricated in 0.8-
micron bipolar complementary metal oxide semiconductor (BiCMOS) technology.
The P5 processor runs at a clock frequency of either 60 or 66 MHz and has 3.1
million transistors. The next version of the Pentium processor family, the P54C
processor, was introduced in 1994. The P54C processors are fabricated in 3.3-V,
0.6-micron BiCMOS technology. The P54C processor also has System
Management Mode (SMM) for advanced power management The Pentium
processor has two primary operating modes and a "system management mode."
The operating mode determines which instructions and architectural features are
accessible. These modes are:
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Protected Mode
This is the native state of the microprocessor. In this mode all instructions and
architectural features are available, providing the highest performance and
capability.
Among the capabilities of protected mode is the ability to directly execute
"real-address mode" 8086 software in a protected, multi-tasking
environment. This feature is known as Virtual-8086 "mode" (or "V86
mode").
Virtual-8086 "mode" however, is not actually a processor "mode," it is in
fact an attribute which can be enabled for any task (with appropriate
software) while in protected mode.
Real-Address Mode (also called "real mode")
This mode provides the programming environment of the Intel 8086 processor,
with a few extensions (such as the ability to break out of this mode). Reset
initialization places the processor in real mode where, with a single instruction, it
can switch to protected mode.
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System Management Mode
The Pentium microprocessor also provides support for System Management
Mode(SMM). SMM is a standard architectural feature unique to all new Intel
microprocessors, beginning with the Intel386 SL processor, which provides an
operating-system and application independent and transparent mechanism to
implement system power management and OEM differentiation features. SMM is
entered through activation of an external interrupt pin (SMI#), which switches the
CPU to a separate address space while saving the entire context of the CPU. SMM-
specific code may then be executed transparently. The operation is reversed upon
returning.
Advanced Features
The Pentium P54C processor is the product of a marriage between the
Pentium processor's architecture and Intel's 0.6-micron, 3.3-V BiCMOS
process The Pentium processor achieves higher performance than the fastest
Intel486 processor by making use of the following advanced technologies.
Superscalar Execution
The Intel486 processor can execute only one instruction at a time. With superscalar
execution, the Pentium processor can sometimes execute two instructions
simultaneously.
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Pipeline Architecture
Like the Intel486 processor, the Pentium processor executes instructions in five
stages. This staging, or pipelining, allows the processor to overlap multiple
instructions so that it takes less time to execute two instructions in a row. Because
of its superscalar architecture, the Pentium processor.
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The Architecture of Pentium Microprocessor
The Pentium microprocessor contains four data registers referred as EAX, EBX,
ECX, and EDX .All are 32 bit wide. The lower 16 bits of each register are called
AX,BX,CX, and DX, and may be split up into halves of 8 bits each. Figure shows
how each lower 16 bit half is referred to by the programmer.
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Figure 1 shows a block diagram of the Pentium design.
The most important enhancements over the 486 are the separate instruction
and data caches, the dual integer pipelines (the U-pipeline and the V-
pipeline, as Intel calls them), branch prediction using the branch target
buffer (BTB), the pipelined floating-point unit, and the 64-bit external data
bus. Even-parity checking is implemented for the data bus and the internal
RAM arrays (caches and TLBs).
As for new functions, there are only a few; nearly all the enhancements in
Pentium are included to improve performance, and there are only a handful
of new instructions. Pentium is the first high-performance micro-processor
to include a system management mode like those found on power-miserly
processors for notebooks and other battery-based applications; Intel is
holding to its promise to include SMM on all new CPUs. Pentium uses about
3 million transistors on a huge 294 mm 2 (456k mils 2 ).
The caches plus TLBs use only about 30% of the die. At about 17 mm on a
side, Pentium is one of the largest microprocessors ever fabricated and
probably pushes Intel’s production equipment to its limits. The integer data
path is in the middle, while the floating-point data path is on the side
opposite the data cache. In contrast to other super scalar designs, such as
Super SPARC, Pentium’s integer data path is actually bigger than its FP data
path. This is an indication of the extra logic associated with complex
instruction support.
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Intel estimates about 30% of the transistors were devoted to compatibility
with the x86 architecture. Much of this overhead is probably in the micro
code ROM, instruction decode and control unit, and the adders in the two
address generators, but there are other effects of the complex instruction set.
For example, the higher frequency of memory references in x86 programs
compared to RISC code led to the implementation of the dual-ac.
Register set
The purpose of the Register is to hold temporary results, and control the
execution of the program. General-purpose registers in Pentium are EAX,
ECX, EDX, EBX, ESP, EBP,ESI, or EDI.
The 32-bit registers are named with prefix E, EAX, etc, and the least 16 bits
0-15 of these registers can be accessed with names such as AX, SI Similarly
the lower eight bits (0-7) can be accessed with names such as AL & BL. The
higher eight bits (8-15) with names such as AH & BH.
The instruction pointer EAP known as program counter(PC) in 8-bit
microprocessor, is a 32-bit register to handle 32-bit memory addresses, and
the lower 16 bit segment IP is used for 16-bi memory address.
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The flag register is a 32-bit register , however 14-bits are being used at
present for 13 different tasks; these flags are upward compatible with those
of the 8086 and 80286.
The comparison of the available flags in 16-bit and 32-bit microprocessor is
may provide some clues related to capabilities of these processors.
The 8086 has 9 flags, the 80286 has 11 flags, and the 80286 has 13 flags. All
of these flag registers include 6 flags related to data conditions (sign, zero,
carry, auxiliary, carry , overflow, and parity) and three flags related to
machine operations.(interrupts, Single-step and Strings).
The 80286 has two additional : I/O Privilege and Nested Task. The I/O
Privilege uses two bits in protected mode to determine which I/O
instructions can be used, and the nested task is used to show a link between
two tasks. The processor also includes control registers and system address
registers , debug and test registers for system and debugging operations.
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Addressing mode & Types of instructions
Instruction set is divided into 9 categories of operations and has 11
addressing modes. In addition to commonly available instructions in a 8 bit
microprocessor and this set includes operations such as bit manipulation and
string operations, high level language support and operating system support.
An instruction may have 0-3 operands and the operand can be 8, 16, or 32-
bits long. The 80386 handles various types of data such as Single bit , string
of bits , signed and unsigned 8-, 16-, 32- and 64- bit data, ASCII character
and BCD numbers.
High level language support group includes instructions such as ENTER and
LEAVE. The ENTER instruction is used to ENTER from a high level
language and it assigns memory location on the stack for the routine being
entered and manages the stack.
On the other hand the LEAVE generates a return procedure for a high level
language. The operating system support group includes several instructions ,
such as APRL.( Adjust Requested Privilege Level) and the VERR/W (Verify
Segment for Reading or Writing).
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The APRL is designed to prevent the operating system from gaining access
to routines with a higher priority level and the instructions VERR/W verify
whether the specified memory address can be reached from the current
privilege level.
PENTIUM PROCESSOR REGISTERS
Figures 2(a) and2l(b) show the Pentium registers. The Pentium contains 8-, 16-,
and 32-bit registers classified into four groups: general-purpose registers, stack
pointers and index registers, extended instruction pointer and flag register, and
Segment registers. These are described next.
General-Purpose Registers
As shown in Figure 2(a), the Pentium has four 32-bit general-purpose registers:
EAX, EBX, ECX, and EDX. These registers can be used for arithmetic, logic, and
other operations as follows:
EAX, EBX, ECX, and EDX as four 32-bit registers AX (low 16 bits of
EAX), BX (low 16 bits of EBX), CX (low 16 bits of ECX), and DX (low 16
bits of EDX) as four 16-bit registers AH, AL, BH, BL, CH, CL, DH, and DL
as eight 8-bit registers as follows:
Some general-purpose registers perform specific functions for certain
instructions The uses of EAX, AX, and AL registers are assumed by some
instructions. The I/O (IN or OUT) instructions always use the EAX, AX, or
AL for inputting or outputting 32-, 16- or 8-bit data from or to an VO port.
Multiplication and division instructions also use the EAX, AX, or AL.
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The ECX or CX register is known as the counter register respectively in
protected mode and real mode because some instructions use these registers
for a loop count for iterative instructions.
The EDX or DX register is used during multiplication and division
instructions. EDX is used by 32 X 32 multiplication and 64 + 32
instructions. DX, on the other hand, is used by 16 x 16 multiplication and 32
+ 16 division instructions.
Note that BX can be used as a 16-bit pointer to memory while EAX, EBX,
ECX, and EDX can be used as 32-bit pointers to memory.
Stack Pointers and Index Registers
The Pentium stack pointer registers can be used as 32-bit or 16-bit registers as
follows
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DATA ORGANIZATION
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INSTRUCTION TYPES
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EXAMPLE 1:
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EXAMPLE 2:
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ADDRESSING MODES
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INTERRUPT PROCESSING
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SUMMARY
This unit has to take an introductory look at the Pentium microprocessor and the
8086 family of upward- compatible microprocessor. The software model of the
Pentium was examined first, showing all the 32 bit registers. The Intel Pentium is a
32-bit microprocessor based on their 80486. The 80486, on the other hand, is an
enhanced 80386. Hence, before proceeding further, an overview of the basic
features of the 80386 and 80486 will be helpful. The Intel 80386 was Intel’s first
32-bit micro programmed microprocessor. Its introduction in 1985 facilitated the
introduction of Microsoft’s Windows operating systems. The high-speed computer
requirement of the graphical interface of Windows operating systems was supplied
by the 80386. Also, the on-chip memory management of the 80386 allowed
memory to be allocated and managed by the operating system. In the past, memory
management was performed by software.
The 80386 is based on Intel’s 16-bit microprocessor, the 8086. The 80386 is
software compatible with the 8086 at the object code level. The 80386 includes
eight 32-bit general-purpose registers. The processor can handle 8-, 16-, and 32-bit
data types. It has separate 32-bit data and 32-bit address pins, and generates a 32-
bit physical address. The 80386 can address directly up to 4 GB (232) of physical
memory. The 80386 can be interfaced to external cache memory. The chip has 132
pins and is typically housed in a pin grid array (PGA) package. The 80386 is
designed using high-speed HCMOS I11 technology. The 80386 is pipelined and
can perform instruction fetching, decoding, execution, and memory management
functions in parallel. The on-chip memory management and protection hardware
translates logical addresses to physical addresses and provides the protection rules
required in a multitasking environment.
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The 80386 contains a total of 129 instructions. The 80386 protection mechanism,
paging, and instructions to support them are not present in the 8086. The main
differences between the 8086 and the 80386 are that the 80386 contains 32-bit
addresses and data types and paging and memory management. To provide these
features and other applications, several new instructions are added in the 80386
instruction
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1. How many stages are available in pipelining of Pentium?
2. The clock frequency of Pentium is_________.
3. The flags used to select between virtual and protected mode is_________
4. What is the size of memory the Pentium can access.
5. Pentium has a internal ROM of 4K .Say Yes/No
6.The physical address is ________ bits.
7. The addressing mode of MOV EAX,[EBX+12345689] is__________
8. The address and data bus of Pentium are same. say true or false
9. Which processor has the cache organization
a) Pentium b)80286 c)80386 d)80486
10. The real mode in Pentium will work in the memory address range of ____M
bytes only.
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