8/4/2019 unit-2(comp)

1/17

U nit -2: Da ta F low an d St ruc tu r a l Modeling

Dataflow Modeling with examples: Concurrent Signal Assignment Statement,

Concurrent versus sequential signal assignment statement, Delta Delay, Multiple Drivers,

Conditional signal assignment statement, selected signal assignment statement,

concurrent assertion statement.

Structural Modeling with example: Component declaration, component instantiation

and examples, Direct instantiation of component.

2.1 Dataflow Modeling with examples:

2.1.1 Concurrent Signal Assignment Statement:

A signal assignment statement represents a process that assigns values to signals. These

statements are used in dataflow style of modeling. An example of concurrent signal

assignment statement is:

C

8/4/2019 unit-2(comp)

2/17

2. With expression select A

8/4/2019 unit-2(comp)

3/17

2.1.3 Delta Delay: In addition to real time delay, VHDL language also defines a

simulation delay known as delta delay. This delay is used to model hardware

concurrency. This concept can be better understood with the help of following example:In Unit-1, we dealt with the concept of inertial and transport delay. The examples of these

delays are shown along with waveform.

Examples

B

8/4/2019 unit-2(comp)

4/17

NOTE: If no delay is specified, the signal event is scheduled for one infinitessimally-

small "delta" delay from the current time. The signal change will occur in the next

simulation cycle.

Example:

(Assume current time is T)

clock

8/4/2019 unit-2(comp)

5/17

Y: out bit);

End Mux;

Architecture Mux_Beh of Mux is

begin

P1: process (A, B, C, D, S)

beginif S = 00 then

Y Y Y Y

8/4/2019 unit-2(comp)

6/17

When 11 => Y null;

End case;

End process P1;

End Mux_Beh;

More than one values may be specified by separating by a symbol | e.g. 00| 01.

2.1.5.3 Loop Statements: The versatility of a programming language lies in its ability toperform a set of instructions repeatedly. This repetitive operation is done through a

control loop structure. A loop statement is used to iterate through a set of sequential

statements. There are three kinds of iteration statements.

1) The first form of the iteration scheme is for the scheme.

Syntax:

[ label: ] for variable in range loop

sequence-of-statementsend loop [ label ] ;

Example:

A := 1;

for I in 1 to 10 loop

A := A +I;

end loop;

In this example, loop executes for 10 times & each time the value of I is incremented by 1.

2) The second form of the iteration scheme is the while scheme.

Syntax:

[ label: ] while condition loop

sequence-of-statements

end loop [ label ] ;

Example: A := 1,B:=1;

while A

8/4/2019 unit-2(comp)

7/17

Syntax:

[ label: ] loop

sequence-of-statements

end loop [ label ] ;

Example:

A := 1,B:=1;

Loop

B := B +1;

A := A +1;

exit when A > 10;

end loop;

All kinds of the loops may contain the 'next' and 'exit' statements.

2.1.5.4 Null Statements: These statements are used when nothing is required to be done.Execution continues with the statement which is appearing next to the null statement.

Wherever in the program, we need to use this statement, we simply write null

The example for null statement is the same as used for case statement. This statement

can be used in if statement or in case statement where certain condition is to be satisfied.Null statement can be used to indicate that when some conditions are met, no action is

to performed.

Example:

Case ABC is

When 001 => Y1 := A and B;

When 010 => Y2:= A or B;

When 100 => Y3:= Not A;

When others => null;

2.1.5.5 Exit statements: A statement that may be used in a loop to immediately exit the

loop.

Syntax:

[ label: ] exit [ label2 ] [ when condition ] ;

Label2 identifies the loop from which the execution jumps out. If no label is defined, the

execution jumps out of the innermost loop.

Example:

exit;

exit outer_loop;

8/4/2019 unit-2(comp)

8/17

exit when A>B;

exit this_loop when C=D or done; -- done is a Boolean variable

The exit statement terminates entirely the execution of the loop in which it is located. The

execution of the exit statement depends on a condition placed at the end of statement

right after the WHEN reserved word. When the condition is TRUE (or if there is nocondition at all), the exit statement is executed and the control is passed to the first

statement after the end loop.

2.1.5.6 Next statements: A statement that may be used in a loop to cause the next

iteration. This statement can only be used inside a loop & it replaces the keyword exit.

Next statement skips the remaining statements and execution goes to next iteration of the

loop.

Syntax :

[ label: ] next [ label2 ] [ when condition ] ;

Example:

next;

nextouter_loop;nextwhenA>B;

nextthis_loopwhenC=Dordone; -- done is a Boolean variable

The NEXT statement allows to skip a part of an iteration loop. If the condition specified

after the WHEN reserved word is TRUE, or if there is no condition at all, then thestatement is executed. This results in skipping all the statements below it until the end of

the loop & passing the control to the first statement in the next iteration.

A NEXT statement may specify the name of the loop it is expected to influence. If nolabel is supported, then the statement applies to the innermost enclosing loop.

The NEXT statement is often confused with the EXIT statement. The difference between

the two is that the EXIT statement exits the loop entirely, while the NEXT statementskips to the next loop iteration (in other words, it exits the current iteration of the

loop.

2.1.5.7Assertion statement: Assertion statement is used for internal consistency checkor error message generation.

Syntax :

[ label: ]assertboolean_condition[ reportstring ][ severityname ] ;

Example:

assert a=(b or c);

http://www.csee.umbc.edu/help/VHDL/sequential.html#asse%23assehttp://www.csee.umbc.edu/help/VHDL/sequential.html#asse%23asse

8/4/2019 unit-2(comp)

9/17

assert j

8/4/2019 unit-2(comp)

10/17

type STRING, and it is a message that will be reported when the assertion violation

occurred.

The report statement was introduced as late as in VHDL93 and is equivalent to the assertfalse statement. The latter form was the only acceptable form in VHDL83.

2.1.5.9Procedure call statement:Procedure call statement invoke an externally-defined subprogram in the same manner as

a concurrent procedure call. A procedure call statement can either be a sequential

statement or concurrent statement. If the statement is inside a process statement oranother subprogram, it is sequential procedure call statement otherwise concurrent

procedure call statement

Syntax :

[ label: ] procedure-name [ ( actual parameters ) ] ;

Actual parameters specifies the list of formal parameters for the procedure. Actuals may

be specified using positional association or named association.

Example:

do_it; -- no actual parameters

compute(stuff, A=>a, B=>c+d); -- positional association first,

-- then named association of

-- formal parameters to actual parameters

2.1.5.10 Return Statement:

Return statement is a special STATEMENT allowed only within subprograms. It is arequired statement in a function, optional in a procedure.

Syntax :

[ label: ] return [ expression ] ;

Return statement causes the subprogram to terminate & control to be returned to thecalling program.

return; -- from somewhere in a procedure

returna+b; -- returned value in a function

The return statement ends the execution of a subprogram (Procedure or function) in

which it appears. It causes an unconditional jump to the end of the subprogram.

If a return statement appears inside nested subprogram it applies to the innermostsubprogram (i.e. the jump is performed to the next end procedure or end function clause).

This statement can only be used in a procedure or function body. The return statement in

a procedure may not return any value, while a return in a function must return a value (an

http://www.csee.umbc.edu/help/VHDL/sequential.html#proc%23prochttp://www.csee.umbc.edu/help/VHDL/sequential.html#retu%23retuhttp://www.csee.umbc.edu/help/VHDL/sequential.html#proc%23prochttp://www.csee.umbc.edu/help/VHDL/sequential.html#retu%23retu

8/4/2019 unit-2(comp)

11/17

expression) which is of the same type as specified in the function after the return

keyword.

2.1.6 Selected Signal Assignment Statement: Selected Signal Assignment Statementis

another form of concurrent signal assignment statement. In this statement, selection is

based on the value of an included expression. The syntax for this statement is:with select

target signal

8/4/2019 unit-2(comp)

12/17

assert a=(b or c);

assert j

8/4/2019 unit-2(comp)

13/17

generic (data_bits, addr_bits : positive);

port (en : in bit;

addr : in bit_vector(depth1 downto 0);

data :out bit_vector(width1 downto 0) );

end component;

3. component adder

port(a,b: in bit_vector(7 downto 0);

s : out bit_vector(7 downto 0);

cin: in bit;

cout: out bit);

end component;The first example declares a three-input gate with a generic parameter specifying its

propagation delay. Different instances can later be used with possibly different

propagation delays. The second example declares a read only memory component withaddress depth and data width dependent on generic constants. This component could act

as a template for the ROM entity.

A component represents an entity/ architecture pair. It specifies a subsystem, which canbe instantiated in another architecture leading to a hierarchical specification. Component

instantiation is like plugging a hard component into a socket in a board as shown in fig

2.2.

A component must be declared before it is instantiated. The component declarationdefines the virtual interface of the instantiated design entity (the socket) but it does not

directly indicates the design entity. The binding of a design entity to a given component

may be delayed and may be placed either in the configuration specification orconfiguration declaration. The component can be defined in package, design entity,

architecture or block declarations. If the component is declared in an architecture, it must

be declared before the begin statement of the architecture. In such a case, the componentcan be used (instantiated) in the architecture only.

A more universal approach is to declare a component in the package. Such a component

is visible in any architecture, which uses this package. Generic and ports of a component

are copies of generics and ports of the entity the component represents.

Example:

Architecture stru_x of ABC is

Component Xor1 is

Port (A,B : in bit_vector (0 to 3);

C : out bit_vector (0 to 3);

End component Xor1;

Signal S1, S2 : bit_vector (0 to 3);

Signal S3 : bit_vector (0 to 3);

Begin

X1 : Xor1 portmap (S1, S2, S3);

End architecture stru_x;

8/4/2019 unit-2(comp)

14/17

2.2.2 Component Instantiation: A component represents an entity/ architecture pair. Itspecifies a subsystem, which can be instantiated in another architecture leading to a

hierarchical specification. Component instantiation is like plugging a hard component

into a socket in a board. The component instantiation statement introduce a subsystemdeclared elsewhere, either as a component or as an entity/architecture pair (without

declaring it as a component).

Instantiates (i.e. create instances of) predefined components within a design architecture.Each such component is first declared in the declaration section of that architecture, and

then "instantiated" one or more times in the body of the architecture. A component

defined in an architecture may be instantiated using the syntax:

8/4/2019 unit-2(comp)

15/17

Syntax:

component_instantiation_statement ::= instantiation_label : component_name

[ generic_map_aspect ] [ port_map_aspect ] ;

This indicates that the architecture contains an instance of the named component, with

actual values specified for generic constants, and with the component ports connected toactual signals or entity ports. The example components declared in the previous section

might be instantiated as:

Example:

enable_gate: nand3 port map (a => en1, b => en2, c => int_req, y => interrupt);

parameter_rom: read_only_memory

generic map (data_bits => 16, addr_bits => 8);

port map (en => rom_sel, data => param, addr => a (7 downto 0);

In the first instance, no generic map specification is given, so the default value for thegeneric constant Tpd is used. In the second instance, values are specified for the address

and data port sizes. Note that the actual signal associated with the port addr is a slice ofan array signal. This illustrates that a port which is an array can be connected to part of a

signal which is a larger array, a very common practice with bus signals.

The component instantiation contains a reference to the instantiated unit and actual values

for generics and ports. There are three forms of component instantiation:

Instantiation of a component.

Instantiation of a design entity.

Instantiation of a configuration.

The actual values of generic map aspect and portmap aspect connections allow assigningthe components of the actual values to generic parameters and ports.

Instantiation of a component:

Instantiation of a component introduces a relationship to a unit defined earlier as acomponent. The name of the instantiated component must match the name of the declared

component. The instantiated component is called with the actual parameters for generics

and ports. The association list can be either positional or named.In the positional list, the actual parameters (generics and ports) are connected in the same

order in which ports were declared in the component.

Named association allows to list the generics and ports in an order that is different from

the one declared for the component. In such a case, the ports have to be explicitlyreferenced.

Instantiation of a Design Entity

It is not necessary to define a component to instantiate it. The entity/ architecture pair can be instantiated directly. In such a direct instantiation, the component instantiation

statement contains the design entity name and optionally the name of the architecture to

be used for this design entity. The reserved word entity follows the declaration of thistype of the component instantiation statements.

8/4/2019 unit-2(comp)

16/17

If architecture name is not specified in an instantiation of a design entity, the last

compiled architecture associated with the entity will be taken.

Example: Positional Association

architecture ABC_1 of ABC is

signal X, Y, S, C: bit;component H_A is

port (I1, I2 : in bit;

S0, C0 : out bit);End component H_A;

Begin

HA : H_A portmap (X, Y, S, C);

End architecture ABC_1;

Named Association (Direct Instantiation)architecture ABC_1 of ABC is

signal X, Y, S, C: bit;component H_A is

port (I1, I2 : in bit;

S0, C0 : out bit);

End component H_A;Begin

HA : H_A portmap (S0 => S, C0 => C, I1 => X, I2 => Y);

End architecture ABC_1;

Instantiation

Entity XOR_ G is

Port (I1, I2: in bit_vector (0 to 3);Out1 : out bit_vector (0 to 3));

end entity XOR_G;

architecture XOR_G1 of XOR_G is

beginOut1

8/4/2019 unit-2(comp)

17/17