APPLICATION SPECIFIC INTEGRATED CIRCUITS DESIGN

-Ankita Tijare

WHAT IS THIS COURSE ALL ABOUT?

The course is about Higher Methodology for ASIC design and includes various testing techniques, fault models, algorithms.

An ASIC is application-specific integrated circuit.

History of integration: small-scale integration (SSI, ~10 gates per chip, 60’s), medium scale integration (MSI, ~100–1000 gates per chip, 70’s), large-scale integration (LSI,~1000–10,000 gates per chip, 80’s), very large-scale integration (VLSI, ~10,000–100,000 gates per chip, 90’s), ultra large scale integration (ULSI, ~1M–10M gates per chip)

History of technology: bipolar technology and transistor–transistor logic (TTL) preceded metal-oxide-silicon (MOS) technology because it was difficult to make metal-gate n-channel MOS; the introduction of complementary MOS greatly reduced power.

The feature size is the smallest shape you can make on a chip and is measured in l or lambda

Origin of ASICs: the standard parts, initially used to design microelectronic systems, were gradually replaced with a combination of glue logic, custom ICs, dynamic random access memory (DRAM) and static RAM (SRAM)

ASIC

An application-specific integrated circuit, ASIC pronounced “a-sick”, is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use.

ASICS VS. WHAT?

Application Specific Integrated Circuit• A chip designed to perform a particular

operation as opposed to General Purpose integrated circuits

• An ASIC is generally NOT software programmable to perform a wide variety of different tasks

An ASIC will often have an embedded CPU to manage suitable tasks

An ASIC may be implemented as an FPGA Sometimes considered a separate category

ASICS VS. WHAT? (CONTD.)

General Purpose Integrated Circuits: Examples:• Programmable microprocessors (e.g. Intel

Pentium Series, Motorola HC-11) Used in PCs to washing machines Programmable Digital Signal Processors (e.g.

TI TMS 320 Series)• Used in many multimedia, sensor processing

and communications applications Memory (dRAM, SRAM, etc.)

ASICS VS. STANDARD IC

Standard ICs – ICs sold as Standard Parts SSI/LSI/ MSI IC such as MUX, Encoder, Memory

Chips, or Microprocessor IC Application Specific Integrated Circuits (ASIC) –

A Chip for Toy Bear, Auto-Mobile Control Chip, Different Communication Chips [ GRoT: ICs not Found in Data Book] Concept Started in 1980s. An IC Customized to a Particular System or

Application –Custom ICs. Digital Designs Became a Matter of Placing

of Fewer CICs or ASICs plus Some Glue Logic.

Reduced Cost and Improved Reliability.

TYPES OF ASIC:- Full-Custom ICs/Fixed ASICs and Programmable

ASICs Wafer : A circular piece of pure silicon (10-15 cm in dia, but

wafers of 30 cm dia)

Wafer Lot: 5 ~ 30 wafers, each containing hundreds of chips(dies) depending upon size of the die

Die: A rectangular piece of silicon that contains one IC design

Mask Layers: Each IC is manufactured with successive mask layers(10 – 15 layers)

First half-dozen or so layers define transistors Other half-dozen or so define Interconnect

FULL CUSTOM ASICS

Full Custom ASICs• Every transistor is designed and drawn by

Hand• Typically only way to design analog portions

of ASICs• Gives the highest performance but the

longest design time• Full set of masks required for fabrication

Full-Custom ASICs Include some customized logic cells Have all their mask layers customized Full-custom ASIC design makes sense only

When no suitable existing libraries exist or Existing library cells are not fast enough or The available pre-designed/pre-tested cells

consume too much power that design can allow or The available logic cells are not compact enough to

fit or ASIC technology is new or/and so special that no

cell library exits. Offer highest performance and lowest cost (smallest

die size) but at the expense of increased design time, complexity, higher design cost and higher risk.

Some Examples: High-Voltage Automobile Control Chips, Ana-Digi Communication Chips, Sensors and Actuators

SEMI-CUSTOM ASICS: STANDARD-CELL BASED ASICS (CBIC- “SEA-BICK”)

Use logic blocks from std. cell libraries, other mega-cells, full-custom blocks, system- level macros(SLMs), functional standard blocks (FSBs), cores etc. Get all mask layers customized - transistors and interconnect Manufacturing lead time is around 8 weeks Less efficient in size and performance but lower in design cost

SEMI-CUSTOM ASICS – CONT’D

STANDARD-CELL BASED ASICS (CBIC- “SEA-BICK”) – CONT’D

GATE-ARRAY-BASED ASIC’S:

In a gate-array-based ASIC, the transistors are predefined on the silicon wafer.

The predefined pattern of transistors is called the base array.

The smallest element that is replicate to make the base array is called the base or primitive cell.

The top level interconnect between the transistors is defined by the designer in custom masks-Masked Gate Array(MGA).

Design is performed by connecting predesigned and characterized logic cells from a library.

Gate Array based ASICs

GATE ARRAY BASED ASICS(CONT…)

Semi-Custom ASICs – Cont’d Programmable ASICs - Cont’d

Structure of a CPLD / FPGA

FPGA

CPLD

DESIGN FLOW:

DESIGN FLOW: Design Entry- Using a hardware description

language(HDL) or schematic entry. Logic synthesis- Produces a netlist-logic cells and their

connections. System partitioning- divide a large system into ASIC-sized

pieces. Prelayout simulation- Check to see if the design functions

correctly. Floorplanning- Arrange the blocks of the netlist on the

chip. Placement- Decide the locations of the cells in a block. Routing- make the connections between cells in a block. Extraction- Determine the resistance and capacitance of

the interconnect. Postlayout simulation- Check to see the design still works

with the added loads of the interconnect.

ASIC CELL LIBRARIES

A library of cell is used by the designer to design the logic function for an ASIC.

Option for cell library: 1. Use a design kit from the ASIC vendor Usually requires the use of ASIC vendor

approved tools. Cells are “phantoms”- empty boxes that get

filled in by the vendor when you deliver, or “hand off” the netlist.

Vendor may provide more of a “guarantee” that design will work

ASIC CELL LIBRARIES:

2. Buy an ASIC-vendor library from library vendor

Library vendor is different from fabricator. Library may be approved by the foundry Allows the designer to own the masks for the

part when finished. 3. You can build your own cell library Difficult and costly.

ASIC CELL DEVELOPMENT:

A complete ASIC library must include the following for each cell and macro:

A physical layout A behavioral model A VHDL or verilog model A detailed timing model A test strategy A circuit schematic A cell icon (symbol) A wire- load model A routing model.

ECONOMICS OF ASIC’S:

On a parts only basis,an FPGA is more expensive per-gate than MGA,which is in turn more expensive than a CBIC.

The key is that the fixed cost of the CBIC is higher than the MGA which is higher than the FPGA

-design Cost -fabrication cost Total product(or part) cost is a function of fixed

cost, variable cost, and the total number of products (parts sold):

total part cost= fixed part cost+ variable part cost

X volume of parts

BREAK- EVEN ANALYSIS EXAMPLE:

ASIC FIXED COSTS: