UMG89000 Hardware Introduction ISSUE 22

82
HUAWEI TECHNOLOGIES CO., LTD. All rights reserved www.huawei.com Internal OWH001102 UMG8900 Hardware Introduction ISSUE 2.2

description

Hardware description UMG8900 Huawei

Transcript of UMG89000 Hardware Introduction ISSUE 22

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Internal

OWH001102 UMG8900

Hardware Introduction

ISSUE 2.2

Page 2: UMG89000 Hardware Introduction ISSUE 22

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Upon completion of this course, you will be

able to:

�Master UMG8900’s shelf、 frame and

board’s function, classification and

interface for operation etc

�Understand the inner signaling flow

�Master the concatenation and cables

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References

� UMG8900 Hardware Installation Manual

� UMG8900 Hardware Description Manual

Page 4: UMG89000 Hardware Introduction ISSUE 22

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Chapter 1 OverviewChapter 1 Overview

Chapter 2 Board functionChapter 2 Board function

Chapter 3 Signaling flowChapter 3 Signaling flow

Chapter 4 Concatenation and cablesChapter 4 Concatenation and cables

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R4 Networking

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Shelf and Frame

(1)

(2)

(3)

(5)

(4)

(5) Filter box(4) Board

(3) Integrated fan(2) 9U board(1) Frame lintel

COMPAQ
Note
ram do
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Shelf and Frame

(3) Embedded fan box(2) Mounting angle(1) Frame lintel

(8) DIP switch for setting frame ID(7) Power-in terminal of fan box

(6) Power-out terminal of fan box(5) Interface for alarm cable

(4) Standby power-in terminal of fan box(3) Interface for monitoring cable

(2) Power-in terminal of frame(1) Mounting angle

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Frame classification

� The main control frame: manages and controls the whole UMG8900

equipment and provides clock signals for other frames.

� The central switching frame: implements frame subtending function.

� The service frame : implements service processing and interfacing

functions.

� The extended control frame: It is configured when the networking with

large capacity is required. It is responsible for protocol processing and

connection management, and implements controlling and managing the

service frames.

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Frame configuration

Service frame#2

Main control frame#1

Central switch frame#0

Air defence frame

Power distribution frame

Air defence frame

Dummy panel

Fiber coiler

Service frame#5

Service frame#4

Service frame#3

Air defence frame

Power distribution frame

Air defence frame

Dummy panel

Fiber coiler

Extended control frame#8

Service frame#7

Service frame#6

Air defence frame

Power distribution frame

Air defence frame

Dummy panel

Fiber coiler

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DIP Switch

OFF

1 2 3 4 5 6 7 8

ON

81000ONONONOFF

70111OFFOFFOFFON

60110ONOFFOFFON

50101OFFONOFFON

40100ONONOFFON

30011OFFOFFONON

20010ONOFFONON

10001OFFONONON

00000ONONONON

SW1SW2SW3SW4Frame IDBinary number

DIP switch setting

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Slot distribution

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

O

M

U

O

R

M

P

U

Service board

Front boards slot distribution

O

M

U

R

M

P

U

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

O

Serviceboard

Serviceboard

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Slot distribution

N

E

T

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N

E

T

T

N

U

O

R

T

C

L

U

Service board

Back board’s slot distribution

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

Service board

T

N

U

O

R

T

C

L

U

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Questions

� Please describe the classification, function and location in the shelf

of the UMG8900’s frames.

� How to set the DIP switch?

� Please describe the slot distribution of UMG8900.

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� Frame classification, function

and distribution in shelf

� Slot distribution in frame

� Dip switch setting.

SummarySummary

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Chapter 1 OverviewChapter 1 Overview

Chapter 2 Board functionChapter 2 Board function

Chapter 3 Signaling flowChapter 3 Signaling flow

Chapter 4 Concatenation and cablesChapter 4 Concatenation and cables

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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Hardware system

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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OMU and MPU

board

board

board

Other frame

board

board

board

board

Main control frame

Board

board

board

board

Other frame

MPU

MPU

(Slave)

MPU

MPU

(Master)

OMU

OMU

board

(Slave)

(Master)

(Slave)

(Master)

board

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MPU

� Implementing control information interaction between the boards

and inter-frame control information interaction as well as interface

management in the case of multiple frames subtended.

� Monitoring and managing the status of all boards in the frame.

� Implementing status querying, monitoring and power-on or power-off

management to the equipment through special maintenance module,

and controlling board power-on sequence to avoid impact from

instant current.

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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MGW control subsystem

CMU

PPU

OMU/MPU

LAN-Switch

Gateway control

subsystem

H.248(FE)

MGC(MSOFTX3000)

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CMU

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CMU

� Providing internal interface to connect with the PPU to implement

interaction of H.248 messages.

� Providing interfaces to connect with the RPU, ASU, TNU and TCLU

to control the boards to convert media streams.

� Providing interface to connect with the MPU to implement data

configuration and output alarms, debugging information and logs.

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PPU

�Providing the Mc interface to the

MGC, B interface to the CMU and

internal interfaces to the MPU.

�Receiving H.248 messages

through Mc interface, implementing

H.248 protocol stack processing,

and forwarding the H.248

messages to the CMU.

�Assembling H.248 messages

received from the CMU, then

performing protocol adaptation

according to H.248 packet format

and sending them to the MGC.

Stack for Mc interface Stack for SG function

H.248

SCTP/UDP

IP

SCCP

M3UA

IP

RANAP

SCTP

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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Packet service processing subsystem

ASUTAC

A4L/

EAC/

TAC

RPURPU

E8T/

G1O/

P1H/P4L

E8T/

G1O/

P1H/P4L

OMU/MPU

TCUTCUTCU

ASU

Packet service processing

subsystem

NET

CLK/GE/FE

IPATM

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ASU

ATM Control Plane Protocol

Stack

SCCP

SAAL

MTP3b

AAL2

RANAP/BICC/ISUP

ATM

IuUP/NbUP

ASU

ATM

ATM User Plane Protocol

Stack

UMTS Access Signaling Adaptor is accomplished by ASU and PPUUMTS Access Signaling Adaptor is accomplished by ASU and PPU

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Back board corresponding to ASU

A

S

U

(m)

A

4

L

A

S

U

(s)

B

A

P

A

S

U

(m)

E

A

C

A

S

U

(s)

B

E

A

A

S

U

(m)

T

A

C

A

S

U

(s)

B

T

A

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RPU

Nb UP

UDP

IP

RTP RTCP

IP

UDP

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Back board corresponding to RPU

R

P

U

(m)

P

4

L

R

P

U

(s)

B

A

P

R

P

U

(m)

E

1

G

R

P

U

(s)

B

G

E

R

P

U

(m)

E

8

T

R

P

U

(s)

B

F

E

R

P

U

(m)

P

1

H

R

P

U

(s)

B

A

P

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NET

MNET

TCL

U

MNET

MBLU

FE+GE

Main Control

(1#)

(0#)

(8#)

2#

TDM

F

E

F

E(2#~7#)

3# 4# 5# 6# 7#

FE+GE+TDM FE+GE+TDM

MNET

MBLU

MBLU

MBLU

MBLU

MBLU

MBLU

MBLU

MBLU

MBLU

MBLU

MBLU

MNET

MTNU

MNET

MTNU

MNET

TDM

TCL

U

Central Switch

Service

Extension Control

Service Service Service Service Service Service

Page 33: UMG89000 Hardware Introduction ISSUE 22

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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TDM service processing subsystem

E32/T32/

S2L/S2E

OMU/MPU

VPUVPUTCU

E32/T32/S2L/S2E

TDM service processing subsystem

TNU/

TCLU

3*TDM

Packet processing subsystem

TDM

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TDM service processing subsystem

� MTNU

� It provide switching and subtending function, it has the master

station compare with the TCLU, it can provide all of the TDM

service switching include the frame TDM service switching which

the MTNU in.

� TCLU

� It provide switching and subtending function, but it can only

provide the frame’s TDM service switching which the TCLU in.

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TNU

�The TNU, together with TDM service interface boards,

composes the T-S-T switching network for the whole

TDM system.

�Implementing one-plus-one backup. The subtending

optical fiber provides one-plus-one protection.

Page 37: UMG89000 Hardware Introduction ISSUE 22

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TCLU

�The TCLU, together with interface boards,

composes the switching network for the same

subrack.

�Implementing one-plus-one backup. The subtending

optical fiber provides one-plus-one protection.

Page 38: UMG89000 Hardware Introduction ISSUE 22

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

Page 39: UMG89000 Hardware Introduction ISSUE 22

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TCU

� The TransCode Unit (TCU) provides voice coding/decoding

resources and echo cancellation resources, implements voice

packetization at TDM side, processes voice datagram, and

implements tone playing function

� The Echo Cancellation Unit (ECU) in the UMG8900 is used to

implement echo cancellation function for the voice signals.

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S2L

�Implementing clock and data recovery of two 155-M

optical interfaces.

�Processing overheads of regenerator section and

multiplex section of optical signals and checking

communication through optical channel.

�Implementing mapping, demapping of SDH and

processing overheads of high-order path and low-order

path.

�Processing E1*63*2 framing and implementing DS0

switching of level-one TDM service.

�Implementing access of 4-k TDM service.

ACT

ACT

LINK

LINK

RX0

RX1

TX0

TX1

Page 41: UMG89000 Hardware Introduction ISSUE 22

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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SPF

�It is responsible for SIGTRAN protocols processing such as M3UA/M2UA/

SCTP/IP/ MAC protocols

�It can process 4 2-Mbit/s links and 64 64-kbit/s links of SS7 signaling over MTP2

layer, or 64 channels of V5 protocol or 128 channels of PRA protocol.

SEP UMG8900 MSOFTX3000

S7UP

MTP3

S7UP

MTP3

MTP2

MTP1 MTP1

MTP2M2UA

SCTP

IP

M2UA

SCTP

IP

MAC MAC

SS7 IP

M2UA-NIF

TDM IP

Page 43: UMG89000 Hardware Introduction ISSUE 22

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem 2.9 Cascading subsystem

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Clock subsystem

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CLK

�CLK is the system clock board, responsible for receiving line clock

signals extracted by interface boards and external synchronous

clock signals provided by BITS.

�Each MGW frame is configured with two NET boards. In the main

control frame, the clock boards provide 16-kHz clock signals to the

NET boards of the frame through the backplane. In other MGW

frames, the clock boards provide 16-kHz clock signals to the NET

boards through the distributed cables.

�The CLK also outputs external synchronous clock signals.

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Chapter 2 Board functionChapter 2 Board function

2.1 Hardware system introduction2.1 Hardware system introduction

2. 2 Operation and maintenance subsystem 2. 2 Operation and maintenance subsystem

2.3 Gateway control subsystem 2.3 Gateway control subsystem

2.4 Packet service processing subsystem 2.4 Packet service processing subsystem

2.5 TDM service processing subsystem 2.5 TDM service processing subsystem

2.6 Service resource subsystem 2.6 Service resource subsystem

2.7 Signaling forwarding subsystem 2.7 Signaling forwarding subsystem

2.8 Clock subsystem 2.8 Clock subsystem

2.9 Cascading subsystem2.9 Cascading subsystem

Page 47: UMG89000 Hardware Introduction ISSUE 22

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Cascading subsystem

M

B

L

U

MMPU/MNET/MTNU

Central switch frame

3xTDM+2xGE+1xFE

M

F

L

U

M

B

L

U

M

F

L

U

MMPU/MNET/TCLU

Slave frame 1

M

T

C

U

M

S

2

L

M

A

S

U

M

A

4

L

MMPU/MNET/TCLU

Slave frame 6

M

T

C

U

M

S

2

L

M

A

S

U

M

A

4

L

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BLU

Page 49: UMG89000 Hardware Introduction ISSUE 22

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FLU

� The Front Link Unit (FLU) is the front subtending board of

UMG8900 in the case of multiple frames subtended.

� A couple of FLUs can provide 8-k time-slot of TDM data

subtending channel and 2x1.25 G of GE data subtending

channel for the corresponding back subtending board BLU.

� FLU has no interface.

Page 50: UMG89000 Hardware Introduction ISSUE 22

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Questions

� Please describe the umg8900’s hardware classification and each

class’ function

� Please describe UMG8900’s functions and interfaces

Page 51: UMG89000 Hardware Introduction ISSUE 22

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� UMG8900’s hardware classification

and each class’ function

� UMG8900’s board’s function and

interfaces

SummarySummary

Page 52: UMG89000 Hardware Introduction ISSUE 22

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Chapter 1 OverviewChapter 1 Overview

Chapter 2 Board functionChapter 2 Board function

Chapter 3 Signaling flowChapter 3 Signaling flow

Chapter 4 Concatenation and cablesChapter 4 Concatenation and cables

Page 53: UMG89000 Hardware Introduction ISSUE 22

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Chapter 3 Signaling flowChapter 3 Signaling flow

3.1 Service signaling flow3.1 Service signaling flow

3.2 Clock signaling flow3.2 Clock signaling flow

3.3 Loading signaling flow3.3 Loading signaling flow

3.4 Alarm signaling flow3.4 Alarm signaling flow

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Service signaling flow

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Chapter 3 Signaling flowChapter 3 Signaling flow

3.1 Service signaling flow3.1 Service signaling flow

3.2 Clock signaling flow3.2 Clock signaling flow

3.3 Loading signaling flow3.3 Loading signaling flow

3.4 Alarm signaling flow3.4 Alarm signaling flow

Page 56: UMG89000 Hardware Introduction ISSUE 22

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Clock extraction

M

C

L

K

M

C

L

K

M

N

E

T

M

N

E

T

M

E

3

2

M

E

3

2

2048kbit/s

2048KHz

1.5GHz 1.5GHz

GPS/GLONASSBITS

8KHz

Main

Control

Frame

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Clock distribution

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Chapter 3 Signaling flowChapter 3 Signaling flow

3.1 Service signaling flow3.1 Service signaling flow

3.2 Clock signaling flow3.2 Clock signaling flow

3.3 Loading signaling flow3.3 Loading signaling flow

3.4 Alarm signaling flow3.4 Alarm signaling flow

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FTP server OMULMT

C

L

K

T

N

U

N

E

T

N

E

T

T

N

U

A

4

L

P

4

L

S

2

L

E

3

2

T

C

U

A

S

U

O

M

U

O

M

U

R

P

U

E

8

T

G

1

O

FE crossover network cable RS232 cabel

FE crossovernetwork cable

FE control bus

master/ slave

FTP service hyper terminal

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OMU embedded BAM

O

M

U

O

M

U

N

E

T

N

E

T

main control

frame

M

P

U

M

P

U

N

E

T

N

E

T

central exchange

frame

T

C

L

U

T

C

L

U

B

L

U

F

L

U

T

N

U

T

N

U

1*FE+2GE+*TDM

master/slaveFE bus

master/slave FE bus

se

rvic

e

bo

ard

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OMU embedded BAM

TT

CC

LL

UU

TT

CC

LL

UU

NN

EE

TT

NN

EE

TT

MM

PP

UU

MM

PP

UU

OMU

OMU

NET

NET

main control frame

MPU

MPU

NET

NET

central exchange frame

TCLU

TCLU

FLU

BLU

FLU

BLU

NET

NET

MPU

MPU

TCLU

TCLU

service frame

TNU

TNU

1*FE+2GE+3*TDM

service

board

master/slave

FE bus

master/slaveFE bus

master/slaveFE bus

NET

NET

MPU

MPU

TCLU

TCLU

master/slaveFE bus

extended control frameservice frame

master/slave

FE bus

Page 62: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 62All rights reserved

Chapter 3 Signaling flowChapter 3 Signaling flow

3.1 Service signaling flow3.1 Service signaling flow

3.2 Clock signaling flow3.2 Clock signaling flow

3.3 Loading signaling flow3.3 Loading signaling flow

3.4 Alarm signaling flow3.4 Alarm signaling flow

Page 63: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 63All rights reserved

Alarm path

O

M

U

O

M

U

N

E

T

N

E

T

T

N

U

T

N

U

C

L

K

A

4

L

M

A

S

U

P

4

L

M

S

2

L

M

E

3

2

T

C

U

R

P

U

T

C

U

FE bus

Mbusserv

ice

board

LMT

crossover networkcable

Note: when LMT is connected

with the host through LanSwitch,

the straight-thru cable is usedserv

ice

board

master/ slave

master/ slave

Page 64: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 64All rights reserved

Alarm path

OMU

OMU

NET

NET

main control frame

MPU

MPU

NET

NET

central exchange frame

TCLU

TCLU

BLU

FLU

TNU

TNU

1*FE+2GE+*TDM

master/slave

FE bus

master/slave

Mbus bus

service

b oard

RPU

Page 65: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 65All rights reserved

Alarm path

OMU

OMU

NET

NET

main control frame

MPU

MPU

NET

NET

centralexchangeframe

TCLU

TCLU

FLU

BLU

FLU

BLU

NET

NET

MPU

MPU

TCLU

TCLU

NET

NET

MPU

MPU

TCLU

TCLU

service frame

TNU

TNU

1*FE+2GE+*TDM

se

vic

ebo

ard

master/slave

FE bus

master/slaveFE bus

NET

NET

MPU

MPU

TCLU

TCLU

extended control frameservice frame

master/slaveMbus

master/slaveMbus

master/slaveMbus

Page 66: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 66All rights reserved

Questions

� Please describe the all kinds of signaling flow

Page 67: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 67All rights reserved

� Service signaling flow

� Clock signaling flow

� Loading signaling flow

� Alarm signaling flow

SummarySummary

Page 68: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 68All rights reserved

Chapter 1 OverviewChapter 1 Overview

Chapter 2 Board functionChapter 2 Board function

Chapter 3 Signaling flowChapter 3 Signaling flow

Chapter 4 Concatenation and cablesChapter 4 Concatenation and cables

Page 69: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 69All rights reserved

Chapter 4 Concatenation and cables Chapter 4 Concatenation and cables

4.1 Cascading cable distribution4.1 Cascading cable distribution

4.2 Clock cable distribution4.2 Clock cable distribution

4.3 Monitoring cable distribution4.3 Monitoring cable distribution

Page 70: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 70All rights reserved

Two frames cascading

OM

U

MN

ET

TN

U

TN

U

MP

U

MP

U

TC

LU

TDM

FEGE

CLK

CLK

MN

ET

OM

U

TC

LU

MN

ET

MN

ET

Page 71: UMG89000 Hardware Introduction ISSUE 22

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Two frames cascading

Page 72: UMG89000 Hardware Introduction ISSUE 22

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More than three frames cascading

Page 73: UMG89000 Hardware Introduction ISSUE 22

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More than three frames cascading

( )

( )

( )

( )( )

( ) ( )

( ) ( )

( ) ( )

( ) ( )

( ) ( )

Page 74: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 74All rights reserved

Chapter 4 Concatenation and cables Chapter 4 Concatenation and cables

4.1 Cascading cable distribution4.1 Cascading cable distribution

4.2 Clock cable distribution4.2 Clock cable distribution

4.3 Monitoring cable distribution4.3 Monitoring cable distribution

Page 75: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 75All rights reserved

Clock extraction

M

C

L

K

M

C

L

K

M

N

E

T

M

N

E

T

M

E

3

2

M

E

3

2

2048kbit/s

2048KHz

1.5GHz 1.5GHz

GPS/GLONASSBITS

8KHz

Main

Control

Frame

Page 76: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 76All rights reserved

Clock cable distribution

Page 77: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 77All rights reserved

Chapter 4 Concatenation and cables Chapter 4 Concatenation and cables

4.1 Cascading cable distribution4.1 Cascading cable distribution

4.2 Clock cable distribution4.2 Clock cable distribution

4.3 Monitoring cable distribution4.3 Monitoring cable distribution

Page 78: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 78All rights reserved

Monitoring cable distribution

D B 1 5

D B 1 5

D B 15

D B 9

D B 9

D B 9

P ow e r d is tr ib u tio n fram e

S e rv ic e fram e

C e n tra l s w itc h fram e

M a in c o n tro l fram e

A ir d e fle c to r

F a n b o x

A ir d e fle c to r

F a n b o x

F a n b o x

D B 1 5

D B 1 5

D B 1 5

D B 1 5

D B 9

D B 9

D B 9

P ow e r d is tr ib u tio n fram e

A ir d e fle c to r

F a n b o x

A ir d e fle c to r

F a n b o x

F a n b o x

D B 1 5

S e rv ic e fram e

S e rv ic e fram e

S e rv ic e fram e

M a in c o n tro l c a b in e t S e rv ic e c a b in e t

Page 79: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 79All rights reserved

Questions

� If there are 4 frames how to cascade them?

Page 80: UMG89000 Hardware Introduction ISSUE 22

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� Cascading cable distribution

� Clock cable distribution

� Monitoring cable distribution

SummarySummary

Page 81: UMG89000 Hardware Introduction ISSUE 22

HUAWEI TECHNOLOGIES CO., LTD. Page 81All rights reserved

� Board function

� Signaling flow

� Concatenation and cables

SummarySummary

Page 82: UMG89000 Hardware Introduction ISSUE 22

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