ULTRA LOW POWER BOOTH MULTIPLIER USING ASYNCHRONOUS LOGIC€¦ · ULTRA LOW POWER BOOTH MULTIPLIER...

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ULTRA LOW POWER BOOTH MULTIPLIER USING ASYNCHRONOUS LOGIC Jiaoyan Chen 1 , Dilip Vasudevan 2 , Michel Schellekens 2 And Emanuel Popovici 1 1 Embedded Systems Group, Department Of Electrical And Electronics Engineering, University College Cork, Cork, Ireland 2 CEOL Department Of Computer Science, University College Cork, Cork, Ireland ASYNC’12 May 7-9, Denmark

Transcript of ULTRA LOW POWER BOOTH MULTIPLIER USING ASYNCHRONOUS LOGIC€¦ · ULTRA LOW POWER BOOTH MULTIPLIER...

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ULTRA LOW POWER

BOOTH MULTIPLIER

USING ASYNCHRONOUS

LOGIC Jiaoyan Chen1, Dilip Vasudevan 2,

Michel Schellekens2 And Emanuel

Popovici1 1Embedded Systems Group, Department Of Electrical And

Electronics Engineering, University College Cork, Cork, Ireland 2CEOL Department Of Computer Science, University College

Cork, Cork, Ireland

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Contents

Motivation

Background – Booth Multiplier

Positive Feedback Charge Sharing Logic

General Operation

Power Estimation

PFCSL Booth Multiplier

Results (Power, Area)

Conclusion & Future Work

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Motivation

Low Power Requirement in Embedded Systems

Dynamic

Power

Lower Voltage Supply, Avoid Unwanted Switches, Adiabatic Logic

and etc.

Static

Power

Power Gating, Multi-threshold and etc.

Target: Low Power Parallel Multiplier ( Booth Radix-4 Array Multiplier)

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Background – Booth Multiplier

Structure

Partial Product

Generator

Adder Block

Array-Based

Regular

Architecture

Balanced

Capacitive

Distribution

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PositiveFeedbackChargeSharingLogi

c

PFCSL= PFAL (Positive Feedback Adiabatic

Logic) +

Charge Sharing Technology

PFCSL VS PFAL

Power

Clock

DC Supply (No overhead of

power clock network)

Specifically designed Power

Clock

Energy

Recycling ~50% ~60%

Speed Run @ 100MHz Not Efficient in High-Speed

Applications

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PositiveFeedbackChargeSharingLogi

c

General Operation

1) VPC(i) to VDD, VPC(i-1) to Ground.

2) VPC(i) Shares the ENERGY with VPC(i+1),

meeting @ VDD/2

3) VPC(i+1) to VDD, VPC(i) to Ground.

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PositiveFeedbackChargeSharingL

ogic

Power Estimation

Charge Sharing

Due to the Balanced Distribution, ~50% Energy

transferred from one stage to the next.

1 1 1 2 2 2Q CV CV C V

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Signal Transition Diagram

Four-Phase

Handshaking Model

Controlled by C-

element

PFCSL Handshaking

Model

Controlled by

Dynamic-AND Ctrl1

Ctrl2

Ctrl3

Ctrl4

Ctrl1

Ctrl2

Ctrl3

Ctrl4

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Two Controlled Latch

Normal D-Latch is NOT suitable in PFCSL

circuits.

Two Controlled Latch is introduced.

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Sharing

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PFCSL Booth Multiplier

Only ONE set of Y(i)

is fetched at each

time.

Smaller Area

Lower Power

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Results Comparison – ADDER

One-Bit Full Adder

(VDD=1V, 45nm TSMC)

Spee

d

Static Dynam

ic

PFAL (Non-

Adiabatic)

PFCSL

100M

Hz

325n

W

550nW 520nW 266nW

~ 20% 52% 49% /

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Dynamic Power

Static Power

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Results Comparison – Multiplier

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Dynamic Power

Static Power

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Results Comparison – Multiplier

Area Comparison

(Transistor Numbers)

PPG Communicati

on

Circuits

Adders Latches Total

PFCSL 1830 280 6231 4300 12641

STATIC 6544 154 6952 3440 17090

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Conclusion & Future Work

New Logic family – PFCSL

New structure of PPG, Booth Multiplier

Power and area improvements

In the future, implement into 8051

microcontroller design. Fabricate it!!!

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Acknowledgements

This work was funded by the Science

Foundation Ireland under Grant number

07/IN.1/1977.

The authors also would like to thank

Synopsys, Ireland for their generous support in

this project.

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Thank you！

Questions？

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