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2004 IEEE Asia-Pacific C onference on Advan ced System Integrated Circuits(AP-AS1 C200 4)/ Aug. 4-5, 20 044-3

A Low-Power Booth Multiplier Using Novel Data Partition MethodJongsu Park, San Kim and Yong-Surk Lee

Processor Laboratory, Department of Electrical and Electronic Engineering, Yonsei University134 Shinchon-dong, Seodaemun-gu, Seoul, KoreaE-mail:jspark@dubiki.yonsei.ac.kr

AbstractThe Booth algorithm has a characteristic that the Boothalgoriihm produces the Booth encoded products with a valueof zero when input data stream have sequentially equalvalues. Th erefore, parrial products have greate r chances obeing zero when the one with a smaller dynamic range of twoinputs is used as a multiplier. To minimize greater switchingactivities of partial products, we propose a novelmultiplication algorithm and its associated architecture. Theproposed algorithm divides a multiplication expression intofour multiplication expressions, and each multiplication iscomputed independently. Finally, the results o eachmultiplication are ad ded Therefore, the exchanging rate otwo input data calculations can be higher duringmultiplication. Implementation results show the proposedmultiplier can maximally save about 20% in terms o powerdissipation than the prev iou s Booth multiplier.

I. INTRODUCTIONDigital signal processing (DSP) is one o f core technologies

necessary for the next generation of multimedia and mobilecommunication systems [ I ] . Most DSP applications involveaddition and multiplication arithmetic operations. Forexample, DCT, FFT, wavelet transform, and OFDM areessential DSP algorithms used for image and videoprocessing, audio signal processing and mobilecommunications [2][3][4]. Currently, many portableinformation devices are batlery-powered. The multiplicationprocess is complex and dissipates a large amount of powerdue to the need for summations of the partial products.Therefore, low-power multiplication is a key concern ofhattely-powered multimedia devices.In a CM OS circuit, power consumption can he reduced byusing a smaller switching activity in the circuit as expressedin the following equation ( I ) .

Ps",,tc*i"gaCVAf , , (1)Where a is the switching activity parameter, c is theloading capacitor, Vdd is the supply voltage, and Fclk s theoperating frequency. The symbol aC can also be viewed aseffective switching activities when measured at the capacitornode during the charging and discharging. The onlyparameter which can he reduced in an algorithmic level is theswitching activity. Therefore, minimizing the switchingactivity in the algorithmic level during the multiplicationprocess should he considered first before the complex andexpensive process of implementing a multiplier is attempted

~ 5 1 .Many researchers have proposed methods to reduce powerconsumption by modifying conventional multiplicationalgorithms [1][6][7][81[91[lOl[111[12].In order to reduce the increased amount of power

consumption, we propose a novel data partition method and amultiplication algorithm by modifying the low power Boothmultiplier [12].The organization of the remainder of the paper is asfollows: Section 2 describes the basics of radix-4 Boothalgorithm. Sections 3 and 4 describe an existingmultiplication and the proposed multiplication, respectively.Section 5 shows experimental results and finally, conclusionsare discussed in Section 6.

11. RADIX-4 BOOTH ALGORITHMThe radix-4 Booth algorithm is a powerful method toincrease the speed of the radix-2 Booth algorithm, sincegreater numbers of bits are inspected and eliminated duringthe total number of cycles necessary to obtain the product.The operation multiplication needs two inputs and they area multiplicand and a multiplier. To realize low-complexity 2'scomplement multiplication, the radix-4 Booth algorithm can

he applied to encode one of two inputs, X, . If data series ofdata are used for Booth encoding, a datum ofX. is partitionedinto a large number of 3-bit groups. The 2's complement ofX,with a word length of W , which can be represented by

j= a

E- ,= 2x;,, 2"

1 4

Here, W is assumed to he an even number. Whenconsidering the other input datum of E multiplied by X;,Equation ( 2 ) can he modified intoW-I

W-I= y B ( x j , , , y ) x 2 2 ' (3 )

I=O

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2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004)/ Aug. 4-5,2 004As shown in Equation (3), the Booth encoded product,B(Xj,,,YJ is a value of -2Y, -Y, 0, Y and 2Y. We can observethat a two input multiplier is replaced with the Booth encodedproduct. As shown in Table 1, the Booth encoded product iszero when three consecutive h its have the same value (0 or 1) .The Booth encoded product with a value of zero does notproduce a partial product. Therefore, we must produce greater

Booth encoded product with a value of zero to reduce powerdissipation.Table 1 Rad ix 4 Booth Encoded Product

111. PREV IOU S MUL TIPLIERA. Dynamic Range and th e Booth Encoded P roductFirst of all, we must understand the concept of dynamicrange. Dynamic range means sequential binary data changes.For example, 0000 or 1 11 have the smallest dynamicrange. However, 0101 or 1010 have large dynamic ranges.For the Booth encoded result to have with a smallerdynamic range between two inputs, partial products have agreater chance of equaling zero. Therefore we do not needany additional computation, and we can reduce powerdissipation if we find a scheme that produces more zeroresults during the Booth encoded products, since the numberof partial products during the multiplication can b e decreased.B. Shens Multiplication AlgorithmShen et al. proposed a multiplication algorithm used forlow power dissipation [LO]. The multiplication algorithmconcentrated on reducing the amount of switching activity ofpartial products, As explained in Table 1, the Booth encodedresult with a smaller dynamic range produces more partialproducts with a value of zero. Therefore, the one with asmaller dynamic range between the two inputs must be themultiplier instead o f a multiplicand.The comparator shown in Fig. 1 compares the effectivedynamic range between two inputs and the switcherexchanges between two inputs if the dynamic range of amultiplicand is less than the multiplier. Then, themultiplicand and the multiplier of the switcher outputs areused as the conventional multiplier inputs.The limitation of this algorithm is that actual input datastreams exchange may occur infrequently because thismethod compares the entire number of bits calculatedbetween two input data streams during the overall dynamicrange comparison.

SwitcherwI I#DI,LBOI UultlDIIeIFig. 1 Multiplication proposed in [12]

I 11110101x 10110110 = (1111x l 0 l l ) X 100000000 I= (1 I I 1 x 01 O) x 10000= (0101x 101 ) x 10000= (0101x 01IO)x 1

I IFig. 2 Example of multiplication with smaller number o f

IV. PROPOSED MULTIPLIERbits

A. Multipl icat ion In put Data Par t i t ioningW e propose a low-power multiplication process appliedwith enhanced power efficiency than the previous method[12]. The previous method simply compares the entirenumber of bits between two input data sourcessimultaneously. Therefore, it has a less chance of tw o inputdata exchange for Booth encoding than the proposed methodin which the two input data are divided into a large number ofterms with smaller bits. For example, in order to increase thechance of data exchanges occur during multiplication, themultiplication process can be modified as shown in Fig. 2.The two inputs used for a multiplication are divided into theupper part and the lower pm . As shown in Fig. 2, (1 11 10101x 101 10000) is not exchanged in the previous m ultiplicationscheme. However, this data is exchanged in the proposedmultiplication.With the proposed scheme, the chance of the exchangescan be increased because four terms of a multiplication with asmaller number of bits than those of the original input arecompared for Booth encoding. Therefore, the proposedmultiplication can increases the chance of partial productbecoming ze ro and reduces the overall power dissipation withlittle additional hardware. The proposed multiplier also uses ahigher speed parallel multiplication architecture with smallerbits than the exi sting Booth multipliers.

B. Architecture of the Proposed Mu ltiplierFig. 3shows one example of the proposed multiplicationarchitecture where two input data streams are divided intoupper and low er parts.

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2004 IEEE A sia-Pacific Conference on Ad vanced System Integrated Circuits(AP-ASIC 2004)/Aug. 4-5,2004

MissAmerica

We compared the power dissipation of the proposedmultiplier with existing Booth multiplers (Shens [12], Yus[IO], and Ahns [ I I]). We evaluated pow er dissipation levelsof the proposed layouted multiplier using a Synopsys PrimePower tool. Tables 3 and 4 show the overall power analysisresults of the four multipliers when applied to FFT andWavelet transform of images. Power dissipation of theproposed m ultiplier used for the D SP algorithms was reducedmaximally by ahout 7% (Shen), 1 5% (Ahn) and 20% (Yu) onaverage, respectively. The reason why the exchange ratio isnot the same as the power dissipation reduction ratio is thatthe input data exchange ratio is based only on the dyanmicrange of the partitioned input data. Therefore, when twopartitioned input data streams are exchanged, all partialproducts for the Booth encoding may not be zero.

Proposed Shens YUS AhnsMultiplier Multiplier Multiplier Multiplier16.73 17.81 20.72 19.16

Le. 16.08 17.46 19.56 18.56FlanerGardenTableTennis

Table 4 Power analysis for wav elet transform application

18.07 20.06 19.4668216.54 17.39 19.25 18.11

VI. CONCLUSIONWe proposed a lo w-po wer multi plier using a modifiedBooth-algorithm. In order to reduce pow er dissipation, wepartititioned two multiplication input data streams intosmaller hits so that a higher probability of partial productsbecoming zero occurs for a lower switching rate. Whereas theoverall area of the proposed multiplier is increased up to 9%,

the power dissipation ratio of the proposed m ultiplier can bereduced maximally by about 20% of the total amount ofpower dissipation when compared with the existing Boothmultiplier. Therefore, the proposed multiplication process canbe applied to a low power design for use in portablemultimedia inform ation devices and SoC designs, especiallywhen low power consumption and high rates of speed areprimary design constraints.

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