UCHOLA design tang - University of...
Transcript of UCHOLA design tang - University of...
Dual HOLA Design for FTK Project
Mel ShochetA t K liAnton KapliyFukun Tang Daping WengDaping Weng
Presentation for Dual HOLA Board Design Reviewg
University of ChicagoEnrico Fermi Institute
J l 18 2011July 18, 2011
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Dual HOLA Card
Dual HOLA for ATLAS DAQ and FTK
MezzanineData Port
Optical Optical link1 CERN HOLA
ATLAS DAQAltera Cyclone IV
EP4CGX15
Dual HOLA Card
FPGAWith built in
pTransceiver
HOLA LDC
built‐in Serdes Optical
Transceiver
Optical link2CERN HOLA LDCLDC
FTK
Brief Design Specification:Data Input at Data Port: 32b@40MHz = 1.28GbpsData output to Serdes: 32b@50MHz = 1.6GbpsLi R t f O ti l Li k ( ith 8B/10B) 2 0GbLine Rate of Optical Links (with 8B/10B) = 2.0Gbps
Link1 (to ATLAS DAQ): Full S‐Link protocol implemented on transceiver.
Links designed to run 1.6‐2.5Gbps
p pLink2 (to FTK):
Transmitter: Full S‐Link protocol implementationReceiver: Only “Flow Control” used.
Number of Dual HOLA card in production: 250F. TANG
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UCHOLA Schematic (1/6 ‐‐‐ Top Level)
Top Level Schematic and FPGA Power Pin Connections
6 LV Powers required for FPGA:• P3V3• VCCA2V5• VCCINT1V2• VCCLGXB1V2• VCCHGXB2V5• VCCDPLL1V2
FPGAFPGA
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UCHOLA Schematic (2/6 –FPGA Configuration)
FPGA
• Serial EPROM Configuration (EPCS4)
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UCHOLA Schematic (3/6 ‐‐‐ S‐Link Data Port & FPGA IOs)
Power_on Reset
FPGAFPGA
• Slink Data Port and FPGA I/Os
50MHz Transceiver Reconfig. Clock
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UCHOLA Schematic (4/6 ‐‐‐Clocks & Optical Transceivers)
• Optical Transceivers
T i R f Cl k G
FPGA
• Transceiver Reference Clock Generators
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UCHOLA Schematic (5/6—Low Voltage Powers)
• LV DC/DC Module• 3.3V to 2.5V• 3.3V to 1.2V
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UCHOLA Schematic (6/6—Low Voltage Powers)
• LV DecouplingLV Decoupling
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PCB LAYER STACK‐UP & IMPEDANCE CONTROL
Stack up and trace routing are designed for the best signal integrityStack‐up and trace routing are designed for the best signal integrity
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Dual HOLA Prototype PCB (Top View)
Board Size: 149 x 74mm
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Dual HOLA Prototype PCB (Bottom View)
Board Size: 149 x 74mm
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Static & BERT Tests
• Low power consumption: [email protected] (2 Watts Total) with 2 optical transceivers.
• BERT: Error free with 1.35E15 data tested for dual channels.
• Test setup: With CERN’s PCI/HOLA test setup a 7dbTest setup: With CERN s PCI/HOLA test setup, a 7db multimode 850nm attenuator is inserted in each optical fiber for both transmitters and receiversoptical fiber for both transmitters and receivers.
• See Anton’s report for details
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Dual HOLA Production Board
Two modifications have been made from the prototype board:p yp
(1) Incorporating with S‐link HW specification, move two optical transceivers 10mm to themove two optical transceivers 10mm to the right edge of the card.
(2) Disconnect Power‐on Reset Enable signal from 1.2V power supply.1.2V power supply.
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Dual HOLA Top Side View
Component height clearance area
These 2 connectors will not be installed in production version.
41mm
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HOLA Hardware Clearance SpecificationRefer to S‐link specification page 44
Slink HW specification: 31mm from the right edge of the board)
31mm
41mm
Prototype card violates S‐link clearance specification byPrototype card violates S‐link clearance specification by extending optical transceivers 10mm inside the card!
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Signal Integrity
• We did not see any noticeable affects on the signal integrity from SI simulation by moving g g y y gthe optical transceivers 10mm to the right edge of the board (FPGA transceivers nowedge of the board. (FPGA transceivers now only drive differential lines of 31mm with a rate of 2Gbps (21mm in the prototype card)rate of 2Gbps. (21mm in the prototype card).
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Removing “Power_good” (1.2V) Enable Signal
1 2V is not high1.2V is not high enough to enable “power‐on RESET”. We disconnected it in e d sco ec edprototype card test.(pin‐3 has internal pull‐up)p p)
No connection to 1.2V in the production boardsproduction boards
Ab h ill t ff t f ti l f !Above change will not affect any functional performance!
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Summaryy
• Approval of Production Runpp
• Purchase order of PCB/Components
• PCB assembly
• Production board testsProduction board tests
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Acknowledges
• Special thanks to Stefan Haas of CERN for his constant psupports and advices on the schematics and PCB designs, as well as test setups. Also thank him for providing us HOLA source and test bench firmware codes.HOLA source and test bench firmware codes.
• Thank Ted Liu of Fermilab for his very valuable advices on the Dual HOLA prototype board tests.
• Thank many others including Arrow Electronics and Altera• Thank many others including Arrow Electronics and Alteratechnical support teams for the valuable discussions and assistances for the FPGA timing model simulations.
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