Typical Transimpedance-limiting amplifier...

Jose Silva-Martinez

1

Typical Transimpedance-limiting amplifier

interfaces

Many circuits are discussed in Razavi’s textbook “ Design of

Integrated Circuits for Optical Communications”; check it for detailed

discussions

Use previously discussed techniques for analyzing frequency

limitations, power consumption and noise floor

Peaking techniques may help, but pay special attention to group

delay!

Power consumption is a major issue, even if dynamic circuits are

used!

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Typical Transimpedance-limiting interface

Iin {0.1-50 mA}; RF {0.5-1 kΩ}

Limited TIA bandwidth smoothes the input current Iin and hence V1

Small signal at the output of TIA

4-5 stages with voltage gain of 4-8 dB/stage is required

Offset voltages are accumulated offset canceller is required

Gain/stage is not well controlled under PVT variations AGC system

Vb

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Transimpedance amplifier based on Resistive Feedback

Stability could be an issue

3 poles in a loop!

Poles are not far from each other

Rf is usually in the range of 500-1kΩ

Does this help?

If so, trade-offs?

Always advisable?

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4

Transimpedance amplifier based on Resistive

Feedback

Interesting output stage!

RE1<<RF

Ve3~ IinRF

Additional gain due to R2?

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Option II

Peaking network can be a simple capacitor

Double check amplifier’s group delay

Pole-zero matching is an issue: Significant ripple may result

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Option II + single-differential output stage

Single-ended output at R6

Fully-differential at nodes A and B

Why source degeneration?

Why R6 is split in two pieces?

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With adjustable feedback resistor and DC control

R1C1 are a low-frequency filter to extract the DC value (offset) of Vout; it can be compared with a reference (not shown) to have better control.

You may want to use a power detector and control the gain

M3 and M4 provides a DC feedback

Base current of Q1 can be provided by M2 to minimize VRF

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Cherry-Hooper amplifier

Fully differential amplifier

First topology requires a CMFB

2nd topology does not require CMFB but it is not isolated from VDD!•Voltage headroom forces us to reduce RD•Trade-off with voltage gain of M3

Stability issues for very HF applications (to be discussed in class)

power consumption could be an issue

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Cherry-Hooper amplifier

Fully differential amplifier

First topology does not require CMFB

2nd topology requires CMFB!

Noise and stability are always relevant issues

Again: two poles in a loop!

Stability issues for very HF applications; power consumption

Small

signal

swing

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10

Modified Cherry-Hooper amplifier having

low-output impedance and current re-use

Gain is still dominated by

gm1RF

Output impedance is

dominated by re3!

Bias current of Q1 is re-used by

Q3 to provide low output

impedance

Nice topology but may require

excessive voltage headroom

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11

Amplifiers using CMOS Transistors!

Inductive peaking increases frequency response but please evaluate group delay ripple!

Expensive solution in terms of silicon area

Lp may extend amplifier’s bandwidth by 70-80 %

Lp provides partial rejection to HF supply noise: better HF PSRR

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12

Amplifiers using CMOS transistors!

Limiting amplifier consists of several stages in cascade

Frequency response is limited by parasitic capacitors

-3dB frequency reduces inversely proportional to the number of stages!

The capacitive loaded source follower generate a “negative capacitor” introducing HF zero-pole that may help

Drawback: complexity and power (current-mode circuit)

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LF Voltage gain=Gm1*RF

Be careful with the bias network: voltage drop through RF

Midterm question: What about noise due to M2?

Pay attention to the parasitic nodes and parasitic capacitors

Double check loop stability

CMOS Amplifiers: Cherry-Hooper

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Integrator

Transimpedance Amplifier

Transimpedance Amplifier

composed by M1, M2, R2 and RF

M4 provides extra gain control

M3 is the typical source follower

R3, C2 and A1 operates as an

integrator that control M4

•Effect on M4 resistance?

•Effect of R1?

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The parasitic pole at the output determines the – 3dB freq=1/R1C1

Output voltage is late by approximately 0.69*R1C1 seconds if your

input signal is a sharp pulse

Delay is within 0.69*R1C1 and R1C1 secs depending on the type of

input signal

The issue of group delay and parasitic poles

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As previously discussed you can use pole-

zero pairs to optimize bandwidth

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Using active inductors to optimize amplifier’s

bandwidth

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“Active inductor”

In practice: Zero-Pole pair; noise & Power

Using active inductors to optimize to

optimize amplifier’s bandwidth

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Comparison of amplifier’s bandwidth and noise

ISCAS-99

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Single-ended circuits have poor PSR and generate significant

amount of power noise.

Minimize these effects by reducing the bond-wire inductor.

Main frequency component is determined by rate speed

Practical issues: On-chip VDD is not a true VDD

Nice interpolating circuit; used in many applications as

frequency multiplier

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Single-ended circuits have poor PSR and generate significant amount

of power noise. Minimize these effect by reducing the bond-wire

inductor.

Positive feedback!VDD, VSS, GND are not ideal (zero impedance) terminals! You always

have resistors, capacitors and inductors everywhere!

Practical issues: On-chip GND is not a real GND

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Significant portion of the glitches

are due to the gate switching,

CGD and CGS!

Errors are again reduced by

symmetry!

IB-icIc’

~ IB+Ic’-Ic

icIc’

VP VQ

M1-off

M2-on

M1-on

M2-off

Ic and Ic’ currents

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Fully Differential circuits have better PSR and generate (much) less

amount of power noise.

Minimize these effect by improving your layout.

Current-mode logic is clean but…power hungry!

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Practical issues: Packaged chips is another issue!

Hard to manage (transmission line) without decent

impedance matching!

Power hungry and noisy guys!

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Practical issues: Far-End crosstalk is an issue as

well

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Low-Voltage, Low-Power Circuits for

Data Communication Systems

Analog/Mixed Signal Center

Texas A&M University, EE Dept.

College Station, TX, 77843, USA

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Motivation

LVDS drivers and receivers: Consume more than 30% of the chip’s total

power consumption!

Different supply voltages for core and I/O;

Low-voltage LVDS drivers low-power consumption; Reduced EMI

and cost; Simplified circuit and PCB design, etc.

TL

R

X M

U

X

1

n

16

....

....

....

T

XD

M

U

X

1

n

16

............

10Gb/s

625Mb/s

............

............

10Gb/s

Chip I Chip II

core coreI/O I/O

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mV50Differential load,

Rload

=1001%

Change in VOD

between “0”

and “1”|VOD|

%10RO

mismatchRO

ps40010020%-80% rise and fall timestR, tF


Rload

=1001%

Change in VOS

between “0”

and “1”|VOS|

14040Output impedance, single

endedRO


Rload

=1001%Output offset voltagesVOS


Rload

=1001%Output differential voltages|VOD|

UnitsMaxMinConditionsParameterSymbol

Standards: IEEE Draft P802.3ae/D5.0; IEEE Std 1596.3-1996.

LVDS Standards and Driver Specifications

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Example: VDD=1.6V, Vocm=1.25V, |Vo|=0.16—Vop/Von,max=1.41V;

Only 190mV for PMOS current source and PMOS switches!

Design challenges—Not enough headroom in VDD direction!

Typical LVDS Driver and the Design Challenges

for Low-Voltage Supplies

D

DD

D

ocmV

opV onV

bI

bI

biasV

cmfbV

D

D

D

DM1 M2

M3M4

M5

M6bI

onVopV ocmV

GND

VDD

1.25V1.41V

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Principle: Remove the top PMOS switches; Use two current sources.

Advantages: Simple; Fast.

Disadvantage: Double static current consumption!

Double Current Sources (DCS) LVDS

bI

bI2

D D

ocmV

bI

opV onV ocmV

biasV

cmfbV

D D

opV onV

M1 M2

M3 M4

M5 2Ib

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Principle: Replace the constant current sources by switchable current

sources!

Advantages: Minimum Static current consumption!

? How to implement the switchable current sources ?

Switchable Current Sources (SCS) LVDS

Driver

D D

Switchable

Current

Source

Switchable

Current

Source

opVocmV

onV

bI

D D

Ib

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VON provides the desired voltage that produces ID=Ib;

? How to generate VON ?

? How to pull up/down Vgate quickly ?

SCS LVDS Driver: Concept

biasV

D D

ocmVopV

onV

D

DONV

DIM1 M2

M3 M4

M5

Switchable

Current Sources

S1

S2

gateV

Ib

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Current mirror is used to produce VON and ID;

Active pull-up/down circuits provide “coarse” control over Vgate;

Buffer Buf-A isolates DC VON from the switches; “Fine” control;

Amplifier amp fixes the drain voltage.

SCS LVDS Driver with Active Pull Up/Down

refDV _

ONVM6

M7

refI

Switchable Current Source

Control Module

Amp

cmfbV

D D

CM

FB

ocmVopV

onV

DIM1 M2

M3 M4

M5

Switchable

Current Sources

refocmV _

SCS LVDS Driver Core

D

DBuf-A

S1

S2

Pull

Up/

Down

Pull

Up/

Down

gateV

D D

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SCS LVDS Driver with Passive Pull Up/Down

refDV _

ONVM6

M7

refI

Switchable Current Source

Control Module

Amp

cmfbV

D D

CM

FB

ocmVopV

onVD D

ppC ppCDIM1 M2

M3 M4

M5

Switchable

Current Sources

refocmV _

SCS LVDS Driver Core

D

DBuf-A

S1

S2

gateV

VDD

ppC

gsC

Data

GND

VDD

VON

VOFF

Data

Vgate

gateV

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LVDS Driver Simulation Configuration

Iout

LVDS

Driver

RT-T

D

D

RT-R

OV

OV

VssCload

Model of the

Load (ESD,

bonding wire,

and package)

iV

iV

oV

oV

VSS

VSS

VSS

VSS

VD

D

ESDBonding

wire Package (3 sections)

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tt (Vdd=1.8V, temp=27o), data rate=1.25Gb/s, pattern=101010

DCS LVDS Driver Simulation Results

Vocm 200mV

Vod 312mV

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tt (Vdd=1.8V, temp=27o), data rate=625Mb/s, pattern=101010

SCS LVDS Driver Simulation Results

ONV

D

opVD

ppCDIM1

M3

Switchable

Current Sources

D

DBuf-A

S1

S2

gateV

VDD

ppC

gsC

Data

GND

VDD

VON

VOFF

Data

Vgate

gateV

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tt (Vdd=1.8V, temp=27o), data rate=625Mb/s, pattern=101010

SCS LVDS Driver Simulation Results

Vocm 50mV

Vod 312mV

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LVDS Driver Chip Micrograph

SCS

LVDS

Driver

DCS

LVDS

Driver

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DCS LVDS driver eye diagram (data rate = 680Mb/s)

DCS LVDS Driver Experimental Results200m

V/d

iv

500ps/div trise300ps

Vod

3

20

mV

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DCS LVDS driver eye diagram (data rate = 1.0Gb/s)

DCS LVDS Driver Experimental Results200m

V/d

iv


Vod

3

20

mV

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DCS LVDS driver eye diagram (data rate = 680Mb/s)

SCS LVDS Driver Experimental Results2

00m

V/d

iv


Vod

3

20

mV

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DCS LVDS driver eye diagram (data rate = 1.0Gb/s)

SCS LVDS Driver Experimental Results200m

V/d

iv


Vod

3

20

mV

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Comparison Among the DCS and SCS

Experimental Results

DCS is faster than SCS: The maximum data rates that DCS and SCS

can operate are 1.4Gb/s and 1.2Gb/s respectively;

Compared to DCS, SCS eye diagrams present larger jitter and

narrower open eyes, mainly due to:

Finite rising and falling time of the gate voltage and drain current;

SCS drain current presents small variations;

SCS presents larger charge injection effects.

SCS is more power efficient than DCS: At 625Mb/s, the current

consumption is 8.4mA and 12.8mA for SCS and DCS, respectively.

DCS consumes 52% more current;

Both DCS and SCS work great for 10Gb/s tranceivers and are

compliant to the standards!

Jose Silva-Martinez

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Comparison of Several LVDS Drivers

Boni Jamasb DCS SCS

Technology0.35mm

CMOS

0.18mm

CMOS

0.35mm

CMOS

0.35mm

CMOS

Output Voltage Swing (mV) 412 200 320 320

Static Power Consumption (mW) 43 23 23 12.8

Maximum Data Rate (Mb/s) 1200 622 1400 1200

Supply Voltage (V) 3.3 1.8 1.8 1.8

With same signal swing, SCS LVDS driver reduces the power

consumption by 60% compared to the previously reported realizations!

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Two low-voltage, low-power ICs have been designed, fabricated, and

tested;

The linear phase filter achieves a large linear signal swing because of

the optimal design of the OTA and the novel CM control;

The filter’s power efficiency is around 31%, which is much better than

the previous realizations (less than 10%);

Both DCS and SCS LVDS are suitable for low-voltage applications

because of the novel structures.

SCS LVDS driver achieves both low-voltage operation and low-power

consumption; It reduces the power consumption by 60% and it is

compliant to the standards.

Conclusions

Typical Transimpedance-limiting amplifier...

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