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- Grow gate oxide throughthermal oxidation

- Deposit Doped Polysilicon

Step (h): n-implantation for

source & drain (self-alignment)

Step (i) p-implantation

Step (j)

- Grow phosphorus glass

- Etch glass to form contact cut

- Evaporating alumni

Etch Polysilicon

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3.3 CMOS Process Enhancement (Interconnection)

3.3.1 Metal Interconnect

* CMOS circuit = CMOS logic process + Signal/Power/Clock-routing

layers- Second-layer of metal (VIA1=M1 to M2)

- Note: M1 must be involved in any contact to underlying areas

(polysilicon, diffusion)

- Process steps for two-metal process (Omitted)

3.3.1.2 Poly Interconnect

- Polysilicon layer is commonly used as interconnection of signals.

- Reduce resistance of polysilicon to make long-distance

interconnection

1. EtchIsolationlayer

2.Form a VIA

Contact

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- Combine polysilicon with a refractory metal (Silicon + Tantalum)

3.3.1.3 Local Interconnection

- Local Interconnection allow a direct connection between ploysilicon

and diffusion , alleviating the need for area-intensive contacts and metal

- Example: Use of Local Interconnect in SRAM (save 25%)

=20-40/square =1-5/square Make long-distance

(for interconnect)

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3.3.2 Circuit elements

1. Resistor

- Polysilicon (undoped) in static memory cell

- Resistive metal (Nichrome) to produce high-value, high-qualityresistors in mixed-mode CMOS circuits

2. Capacitors

- Polysilicon capacitor

- Memory capacitor (3-dimensional to increase cap/area)

- Example:

1. Trench capacitor (Fig3.18 (a))

2. Fin-type capacitor (Fig3.18 (b))

Process Cross

SectionGeometry

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