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Technische Universitt Mnchen

Chip Multicore ProcessorsTutorial 7

Institute for Integrated Systems

Theresienstr. 90

Building N1www.lis.ei.tum.de

S. Wallentowitz


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Institute for Integrated SystemsChip Multicore Processors

Tutorial 7

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S. Wallentowitz

Task 7.1: Memory Overhead of Cache Coherency

Given is the sketched system, which

integrates processor cores and their

caches. Each of the caches has size 1.

The cores share a last level cache of size

2. All cache blocks are of size. A memoryof size is connected to the system.

L1 L1 L1

Dir L2

Mem

Cache coherency can either be snooping-

based or directory-based. Snooping adds 2extra bits to the caches and the directory

implementation requires 3 bits plus a bitvector.


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Tutorial 7

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7.1 a) Calculate the required memory bits for

snooping- and directory-based coherency

L1 L1 L1

Dir L2

Mem


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Tutorial 7

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7.1 b) Calculate the extra memory of an embedded

system with 32 MB memory, 32 kB L1 cache and256 kB L2 cache. The cache blocks are of 4 words.

L1 L1 L1

Dir L2

Mem


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Tutorial 7

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7.1 c) Calculate the extra memory of a desktop system

with 4096 MB memory, 512 kB L1 cache and 4 MBL2 cache. The cache blocks are of 8 words.

L1 L1 L1

Dir L2

Mem


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Tutorial 7

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Task 7.2: Basics of Cache Coherency

Three caches use snooping-based cache coherency with a shared bus.

Complete the states of the cache entries according to the MSI protocol for

the given operations.

Invalid Shared

Modified

CPU Read Miss

(Place read miss on bus)

CPUWriteMiss

(Placew

ritemissonbus)

Hit

Invalidate Read Hit

Write

Miss(WriteMi

ss)

Write Miss

All actions on cache lines

Write-back cache

Processor triggered Events

Cache actions

Bus triggered Events

Cache actions

Read Miss


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Institute for Integrated SystemsChip Multicore Processors Tutorial 7 8

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7.2 a)

t operation C0 C1 C2

0 I I I

(1) READ

1

(1) WRITE

2


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Institute for Integrated SystemsChip Multicore Processors Tutorial 7 9S. Wallentowitz

7.2 a)


2 I M I

(0) READ

3

(2) WRITE

4


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7.2 a)


4 I I M

(2) READ

5

(0) READ

6

(0) WRITE


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7.2 b)


0 I I I

(1) READ

1

(1) WRITE

2

Do the same according to the MESI protocol


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7.2 c) According to you, what extensions does a bus need to supportsnooping-based cache coherency (write back caches)?


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7.2 d) For MSI and MESI sketch the valid state combinationsfor one entry in two caches.

M S IM

S

I

M E S I

M

E

S

I

Tutorial07 Solution

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