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Transistor Sizing for Radiation Hardening

Quming Zhou and Kartik MohanramDepartment of Electrical and Computer Engineering

Rice University, Houston, TX 77005E-mail: {quming, kmram}@rice.edu

Abstract

This paper presents an efficient and accurate numer-ical analysis technique to simulate single event upsets(SEUs) in logic circuits. Experimental results that showthe method is accurate to within 10% of the results ob-tained using SPICE are provided. The proposed methodis used to study the ability of a CMOS gate to tolerateSEUs as a function of injected charge and transistorsizing (aspect ratio W

L ). A novel radiation hardeningtechnique to calculate the minimum transistor size re-quired to make a CMOS gate immune to SEUs is alsopresented. The results agree well with SPICE simula-tions, while allowing for very fast analysis. The tech-nique can be easily integrated into design automationtools to harden sensitive portions of logic circuits.

1 Introduction

In the next decade, technology trends – smaller fea-ture sizes, lower voltage levels, higher operating fre-quencies, reduced logic depth – are projected to causean increase in the soft error failure rate in integratedcircuits. While memories have historically been the fo-cus for soft error failure rate reduction, recent studiesindicate that the soft error failure rate in logic will in-crease to an extent where it will become comparable topresent-day unprotected memory elements [Cohen 99],[Shivakumar 02]. As a result, there is an urgent needfor techniques to estimate and reduce the soft errorfailure rate in logic circuits.

As the complexity of designs increase, the currentpractice of addressing the soft error robustness of alogic circuit following physical design will result in in-creased iterations in the design cycle. While SPICE-based characterizations of library cells after back-annotation are extensively used today, such techniquesare inherently computationally expensive and incorpo-rating them into logic synthesis engines and other de-sign automation tools presents significant challenges.

There is a need for techniques to incorporate SEU-

robustness metrics into the design cycle at higher levelsof design abstraction, i.e., earlier in the design cycle,to realize inherently robust circuits. By working witha model that accurately captures the effects of a SEUfor simulation purposes at the gate level, the compu-tational bottleneck can be significantly alleviated. Thepurpose of this paper is to develop one such model forefficient and accurate analysis, and to show how thatcan be used to harden logic gates by transistor sizing.The following are the contributions of this paper:

1. An accurate model coupled with efficient numeri-cal analysis to simulate SEUs in CMOS logic gatesis presented. The transient voltage response iscomputed by solving the non-linear Riccati differ-ential equation using the Runge-Kutta method.

2. The sizes of gates driving a node and the amountof capacitance at the node determine the magni-tude and duration of the SEU transient. A noveltransistor sizing method to harden a CMOS gateto SEUs is presented. This technique can be usedwith logic synthesis tools to identify and hardenhighly susceptible gates in a design, along the linesof the technique presented in [Mohanram 03].

The rest of this paper is organized as follows. In Sec-tion 2, we discuss previous literature and discuss themotivation for this paper in greater detail. In Section3, we present the model and the numerical techniquefor SEU analysis. In Section 4, we discuss the effectsof transistor sizing on SEU immunity and present anefficient technique to size transistors for radiation hard-ening in logic circuits. In Section 5, we present experi-mental results for the methods described in Sections 3and 4. Section 6 is a conclusion.

2 Motivation and previous work

Several papers have addressed the problem of modelingand estimating the voltage transient that results at alogic gate following a SEU. An efficient and accurate

1

estimation of the rise time, the fall time, and the du-ration of the resulting transient voltage pulse is highlydesirable. In [Dharchoudhury 94], the simulation timeinterval was divided into several independent segments(time intervals). A piecewise quadratic function (i.e., aquadratic function for each time segment) was used toapproximate the double exponential waveform for thecurrent pulse used to model a SEU at a node (Section 3,Equation 2). In [Dahlgren 95], although the current atthe node where the particle strike occurs is modeled bya double exponential function, the contribution fromthe from the τβ time constant (Section 3, Equation 2)was ignored. Other methods proposed in literature aremainly used for fault injection and simulation. There,accuracy is compromised for speed of computation, ren-dering them unsuitable for use in cases where accuracyis desirable.

In this paper we present a method to estimate thetransient voltage waveform that is not just faster thantraditional SPICE-based approaches but also highly ac-curate. Besides this, the other main motivation forthis paper is the development of a fast transistor siz-ing method to eliminate the effects of a SEU at a logicgate by examining the relation between the transistorsize and the injected charge. A large transistor candissipate (sink) the injected charge as quickly as it isdeposited, so that the transient does not achieve suf-ficient magnitude and duration to propagate to gatesin the fanout. Moreover, since the voltage disturbanceis a finite energy transient effect, the injected chargeQ also needs to be factored in when selecting the opti-mal transistor size. There is a trade-off however, sinceincreasing the transistor size will impact not just areabut also power consumption and delay. The proposedtechnique can be used to balance overhead costs (area,power, delay) to choose the minimal transistor size toachieve the desired level of SEU immunity.

3 Modeling and analysis

Figure 1 illustrates the CMOS circuit used to explainthe modeling and analysis in this paper. Cout is theoutput capacitance at node N and is obtained by scal-ing the unit output capacitance Cunit by the transistorsize W

L . Cp is the lumped parasitic capacitance (inter-connect and fanout) at node N . The total capacitanceassociated with node N is given by

CL = Cp + Cunit

(

W

L

)

(1)

For the rest of this paper, we focus on the voltageVout(t) at node N , since its magnitude and duration

a

b

a b

Cout CpIin

...

Node N

Vout (t)

Figure 1: Example circuit

will determine how the disturbance propagates throughgates in its transitive fanout in the logic circuit to theprimary outputs or latches.

Iin(t) denotes the double exponential current pulseproduced as a result of a particle strike at N . Iin(t)has been approximated by a double exponential cur-rent pulse injected into the site of the particle strike[Messenger 82], [Dharchoudhury 94]:

Iin(t) =Q

(τα − τβ)

(

e(−t/τα) − e(−t/τβ))

(2)

In the above equation, Q is the amount of injectedcharge (positive or negative) that is deposited as a re-sult of a particle strike, τα represents the collectiontime-constant of the junction, and τβ accounts for theion-track establishment time-constant. τα and τβ areconstants dependent on several process-related factors.

In this paper, we only consider the worse case tran-sient effects to logic values 0 and 1. A transient to 1 (0)refers to the case when the steady-state logic value atN is 0 (1) in the fault-free case and a SEU generates apositive (negative) transition to 1 (0) at N . The rest ofthis section discusses the response of the NAND gateat node N when a SEU causes a transient to 1. Theanalysis for a SEU that causes a transient to 0 is sym-metrical, with the use of pMOS transistor equations.Note that the pMOS transistors, whose inputs are atlogic value 1, are off and hence do not figure in the anal-ysis here. We set both inputs of the NAND gate to 1,so that the voltage is 0 at N in the fault-free case. Fora transient to 1 in the NAND gate, the site for injec-tion of current source Iin(t) can be one of the internalnodes or the output of the gate. Since any disturbanceinternal to the gate has to propagate through one (ormore) series transistors before reaching the output ofthe gate, the magnitude of the pulse will be reduced (orfade out altogether) during this propagation. Thus, theworst case occurs when the site for charge injection isthe output of the gate (i.e., node N).

Note that the amplitude of the transient pulse at N

given by Vout(t) is limited by the forward bias volt-age on the diode between the drain and the body of

the pMOS transistor. For a transient to 1, the drainto body diode that is reverse-biased under normal op-erating conditions may switch to forward-bias if thetransient pulse rises above VDD + Vdiode. We focus oncomputing Vout(t) in the 0 to VDD + Vdiode range forthe rest of this discussion.

Depending on the region of operation of the nMOStransistor, the voltage pulse Vout(t) is given by the so-lution to the following differential equation:

CLdVout

dt= Iin(t) −

(

W

L

)

· ID(Vout) (3)

where

ID(Vout) = β · (2(VGS − VT,n)Vout − Vout)2

(4)

for Vout < (VDD − VT,n) (linear) and

ID(Vout) = β · (VGS − VT,n)2

(5)

for (VDD −VT,n) ≤ Vout < (VDD +Vdiode) (saturation).

VT,n is the threshold voltage of the nMOS transistor,Iin(t) is the injected current, VGS equals VDD, W

L isthe aspect ratio of the nMOS transistor, and CL is theload capacitance at node N (as explained in Equation1). The transconductance β is not a constant but afunction of Vout(t) and this has to be accounted forin the numerical analysis method presented in Section3.1. A detailed explanation of how β is determined andapproximated is presented in the appendix.

3.1 Numerical analysis for Vout(t)

Given the initial condition Vout(0) = 0, the above dif-ferential equation is a non-linear Riccati differentialequation of the form

dVout

dt= a(t) · V 2

out + b(t) · Vout + c(t) (6)

whose closed form solution usually requires knowledgeof a particular solution [Kayssi 92]. Since a particularsolution cannot be obtained in this case, the standardmethod of solving this differential equation is based ona power series expansion. An infinite power series so-lution for the transient response of an inverter, whenno transient current of the form Iin(t) is injected intothe system, was proposed in [Shih 92]. Computationof the terms of an infinite power series is expensive inpractice; moreover, it is very difficult to directly cal-culate the coefficient terms if more than a third orderpolynomial is used to approximate the solution.

We employ the fourth-order Runge-Kutta method[Nakamura 93] to calculate the numerical solution for

Equation 3. The basic idea behind the Runge-Kuttamethod is that the value of the dependent variable,voltage Vout(t) in this case, can be determined at thenext desired value of the independent variable, time t,by calculating several intermediate values. Note thatdue to the parasitic and load capacitances at node N

and the circuit inertia, the nature of the voltage wave-form Vout(t) is smooth and continuous. As a result, itis highly suitable for solution using the Runge-Kuttamethod. The fourth-order Runge-Kutta formulation isgiven by

Vout(tn+1) =

Vout(tn) +h

6(k1 + 2k2 + 2k3 + k4) + O(h5)

(7)

where h is the time step,

f(t, Vout) =dVout

dt

k1 = f(tn, Vout(tn)),

k2 = f(tn + 0.5h, Vout(tn) + 0.5k1),

k3 = f(tn + 0.5h, Vout(tn) + 0.5k2), and

k4 = f(tn + h, Vout(tn) + k3)

The solution for Vout(tn+1) is accurate to the fourthorder. In Section 5, we present results that show thatthe solution obtained using the proposed method is ac-curate to within 10% of the results obtained using Level49 SPICE simulations.

4 Sizing for SEU immunity

In this section, we describe an efficient method to com-pute the minimum transistor size

(

WL

)

minrequired to

limit the maximum value of the transient pulse Vout(t)at node N to a pre-specified value. We denote this limiton Vout(t) by VSEU . For the rest of this discussion, weassume this limit on the peak value VSEU is VDD

2 (thatis VIH for gates in the transitive fanout). Note that themethod is equally applicable for any other limit on thepeak value of Vout(t). As Vout(t) rises from 0 to VDD

2 ,the nMOS transistor is in the linear region of operation.The cross-coupled nature of the differential Equation 3implies that there is no closed form expression for theinstant tmax when Vout(t) reaches VDD

2 . However, sincetmax occurs after the injected current Iin(t) reaches itsmaximum, it is possible to use the following iterativeprocedure to compute tmax.

The first step is to determine a suitable search inter-val for tmax. The maximum value of Iin(t) occurs at a

Vout

ttmax

2

DDV

Linear approximation for Vout(t)

0 Vout 0.5VDD and 0 t tmax

Figure 2: Linear approximation to compute(

WL

)

min

time instant tstart that is given by

tstart =

(

τα · τβ

τα − τβ

)

· ln(τα

τβ) (8)

from Equation 2. This can be used as the beginningof the search interval for tmax, since tmax ≥ tstart.tmax is located in the interval [tstart, tref ], where tref

is bounded by the clock period of the logic circuit.If VDD

2 is the maximum value of Vout(t) at time tmax,two conditions must be satisfied by Equation 3. Thefirst is that the slope dVout

dt must equal 0, i.e.,

Iin(tmax) −

(

W

L

)

ID

(

VDD

2

)

= 0 (9)

Rearranging this, we have(

W

L

)

min

=Iin(tmax)

ID(VDD

2 )(10)

where(

WL

)

minis the minimum transistor size required

to limit the magnitude of the transient pulse at nodeN to VDD

2 . The second condition is that the integralof both sides of Equation 3 over the interval [0, tmax]must be equal, i.e.,

(Cunit ·

(

W

L

)

min

+ Cp)

∫

VDD2

0

(

dVout

dt

)

dt =

∫ tmax

0

Iin(t)dt −

(

W

L

)

min

·

∫ tmax

0

ID(Vout)dt

(11)

Since ID(Vout) is a non-linear equation that dependson Vout(t), we use the following approximation to sim-plify the integration. We assume that the voltageVout(t) rises from 0 to the peak value of VDD

2 linearlyas shown in Figure 2, i.e.,

Vout(t) =

(

VDD

2

)

·

(

t

tmax

)

for 0 ≤ t ≤ tmax (12)

As a result, ID is just a function of time t and Equation11 is directly integrated to get a non-linear equation in

(

WL

)

minand tmax. This, along with Equation 10, can

be solved using the bisection method [Nakamura 93]over the interval [tstart, tref ] to determine both un-knowns tmax and

(

WL

)

min. In Section 5, we present

experimental results that use this method to determine(

WL

)

minthat are in excellent agreement with those ob-

tained using SPICE.

5 Experimental results

The SPICE library used for all simulation is theTSMC 0.18 micro library distributed by [MOSIS]. Thetransconductance parameter β, for a range of transis-tor sizes, is an input from SPICE to the proposed setup(as explained in the appendix). The unit output ca-pacitance Cunit was also determined using SPICE andscaled according to Equation 1. We used τα = 0.2nsand τβ = 0.05ns in all our experiments.

5.1 Calculation of Vout(t)

In Figure 3, we present a comparison between threesets of curves for Vout(t). Each set of curves corre-sponds to different amounts of charge injected (i.e.,SEUs of different strengths) as annotated in the figure.The transistor size remained fixed in all the cases. Thesolid curve in each set was obtained using the numeri-cal analysis method described in Section 3.1, while thedashed curve was obtained from SPICE simulations. Itis clear that for fixed transistor sizing, SEUs of greatermagnitude produce transients of larger swing and du-ration at the output of the gate in comparison to SEUsof smaller magnitude. It is also clear that the proposednumerical analysis technique is very accurate and thatthe results vary by less than 10% from those obtainedby Level 49 SPICE simulations.

0 0.5 1 1.5 20

0.5

1

1.5

2

2.5

Q = 0.03 , 0.15 , 0.3 pC with W = 4

Q = 0.3pC

Q = 0.15pC

Q = 0.03pC

Vo

ltag

eVout(t)

V

Time t ns

Proposed Technique

SPICE

Fixed sizing = 4L

W

Figure 3: Vout(t) for varying charge and fixed WL

In Figure 4, we present a similar comparison betweenthree sets of curves for Vout(t). The only change fromFigure 3 is that the three sets of curves correspondto different aspect ratios (different W

L s) for the nMOStransistors, while the total injected charge (i.e., themagnitude of the SEU) remains constant. It is clearthat for fixed SEU magnitude, increasing the transis-tor size has the desired effect of reducing the magnitudeand duration of the transient voltage pulse at the out-put of the gate.

In Figure 5, we varied the width of the transistor con-tinuously for three different values of charge injectedinto the node N . The pulse width of the transient,given by the time that Vout(t) exceeds VDD

2 was mea-sured for each of the cases. It is clear that there is anexcellent agreement between the results obtained us-ing proposed numerical analysis method and those ob-tained using SPICE simulations. It is also clear that asthe transistor size increases, the magnitude and dura-tion of the transient voltage pulse (as measured aboutVDD

2 ) decreases and for large enough sizing, becomeszero. This observation can be exploited to radiationharden gates by sizing transistors, as described in thenext section.

0 0.5 1 1.5 20

0.5

1

1.5

2

2.5

W = 4 , 8 , 10 with 2(exp(−t/0.2)−exp(−t/0.05))

Fixed charge Q = 0.3pC

Vo

ltag

eVout(t)

V

Time t ns

Proposed Technique

SPICE8

L

W

4L

W

10L

W

Figure 4: Vout(t) for varying width and fixed charge

Note that for Q = 0.4pC and WL = 4, the magnitude

of the transient pulse exceeds VDD +Vdiode significantlywhen the proposed model is used. While this is a lim-itation of the model, it is not in the region of interestas far as the transient response is concerned because ofits severe nature.

5.2 Sizing for SEU immunity

In Figure 6, we present the minimum transistor aspectratio W

L needed to limit the peak of the voltage tran-

4 5 6 7 8 9 10 11 12 130

0.2

0.4

0.6

0.8

1

1.2

1.4

Proposed Technique

SPICE

Transistor sizingL

W

Q = 0.2pC Q = 0.3pC

Q = 0.4pC

Tra

nsi

ent

puls

e w

idth

(ns)

Figure 5: Transient pulse width vs.(

WL

)

sient to VDD

2 for different values of injected charge. Thesolid curve represents the results obtained using themethod proposed in Section 4 while the dotted curverepresents the results obtained from SPICE. It is clearfrom the figure that the proposed method, whose re-sults are in excellent agreement to those obtained us-ing SPICE, has the twin advantages of accuracy andcomputational efficiency. The number of iterations todetermine

(

WL

)

minusing the bisection method for an

error tolerance of 0.001ns and tref = 1ns is 7. Theroutines were implemented in C and can easily be inte-grated into a logic synthesis tool that sizes transistorsfor radiation hardening.

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

5

10

15

20

25

30

35

40

Injected charge with Q (pC)

Injected charge Q (pC)

Min

imu

m s

ize

for

SE

U i

mm

un

ity

W L

Proposed Technique

SPICE

Figure 6: Sizing for SEU immunity

6 Conclusions

In the future, as designs become more complex and asthe soft error failure rate of logic circuits becomes un-acceptably high, there will be a need for simulation anddesign automation techniques for radiation hardening.This paper described an efficient and accurate tech-nique to simulate SEU effects in logic gates. A noveltechnique for transistor sizing to reduce SEU suscep-tibility that is very accurate in comparison to SPICEwas also described. An area for future research is toinvestigate how this sizing technique can be used toselectively target the most sensitive nodes in a logiccircuit.

References

[Cohen 99] N. Cohen, et al., “Soft Error Considera-tions for Deep-Submicron CMOS Circuit Applica-tions,” Intl. Electron Devices Meeting Technical Di-gest, pp. 315-318, 1999.

[Dahlgren 95] P. Dahlgren and P. liden, “A Switch-level Algorithm for Simulation of Transients inCombinational Logic,” Proc. Intl. Sym. on Fault-Toleran Computing, pp. 207-216, 1995.

[Dharchoudhury 94] A. Dharchoudhury, et al., “FastTiming Simulation of Transient Fault in Digital Cir-cuits,” Proc. Intl. Conf. on Computer-Aided De-sign, pp. 719-726, 1994.

[Kayssi 92] A. I. Kayssi, et al., “Analtical TransientResponse of CMOS Inverters,” IEEE Trans. onCircuits and Systems, Vol. 39, pp. 42-45, Jan. 1992.

[Messenger 82] G. C. Messenger, “Collection of Chargeon Junction Nodes from Ion Tracks,” IEEE Trans.on Nuclear Science, Vol. NS-29, pp. 2024-2031,Dec. 1982.

[Mohanram 03] K. Mohanram and N. A. Touba,“Cost-Effective Approach for Reducing Soft ErrorFailure Rate in Logic Circuits,” Proc. Intl. TestConference, pp. 893-901, 2003.

[MOSIS] http://www.mosis.org

[Nakamura 93] S. Nakamura, Applied Numerical Meth-ods in C, Prentice Hall, 1993.

[Shih 92] Y. H. Shih and S. M. Kang, “Analytic Tran-sient Solution of General MOS Circuit Primitives,”IEEE Trans. on Computer-Aided Design, Vol. 11,pp. 719-731, Jun. 1992.

[Shivakumar 02] P. Shivakumar, et al., “Modeling theEffect of Technology Trends on the Soft Error Rateof Combinational Logic,” Proc. Intl. Conference onDependable Systems and Networks, pp. 389-398,2002.

Appendix

VDS

(V)

Tra

nsc

on

du

ctan

ceß

(A V

-2)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.82.5

3

3.5

4

4.5

5

5.5x 10

−5 Ids & Beta; Gain=Beta*(W/L); W = 4, 16, 64

16L

W

64L

W

4L

W

Figure 7: Transconductance β(VDS) for a NAND gate

The transconductance β of a NAND gate is not con-stant but varies significantly with VDS and to a smallextent with the transistor size W

L . We remove the

dependence on WL by averaging over the three curves

shown in Figure 7. We define two linear functions tomodel the dependence of β on VDS , one for the re-gion 0 ≤ VDS ≤ 1.2 V and the second for values ofVDS > 1.2 V. This is an empirical model that is usedin Equation 3 in the paper.