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![Page 1: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/1.jpg)
Optimization Challengesin Transistor Sizing
Chandu Visweswariah
IBM Thomas J. Watson Research Center
Yorktown Heights, NY
Acknowledgments
The entire EinsTuner team at IBM, especially Andy Conn of the Applied Mathematics department at IBM Research
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Two acts focusing on optimization• Act I: what we have done with existing
nonlinear optimization techniques– what is EinsTuner?– how does it work?– what is its impact?
• Act II: what we would love to do and currently cannot– numerical noise– capacity– robustness, scaling, weighting, degeneracy– recursive minimax support– mixed integer continuous problems
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Act I: What is EinsTuner?• A static, formal, transistor sizing tool geared
towards custom high-performance digital circuits– static: based on static transistor-level timing
analysis, so implicitly takes into account all paths through the logic
– custom: timing based on real time-domain simulation of all possible transitions through each clump of strongly-connected transistors
– formal: guaranteed optimal• “local” according to engineers• “global” according to mathematicians
– transistor-level, therefore inherently flat– see DAC ’99, ICCAD ’99, SIAM J. Opt 9/99
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Features of EinsTuner• Extensive (sweeping and fine-grained)
grouping, ratio-ing and no-touch commands
• 25K transistor capacity (60K variables)
• Allows delay, area, ratio, input loading, slew and transistor width constraints
• Allows minimization of delay, area or linear combination thereof
• Easy-to-use; full GUI support; good fit into (semi-custom and custom) methodologies
• Timer benefits such as accuracy for custom circuits, pattern-matching, state analysis
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EinsTuner: formal static optimizer
Embedded time-domain simulator
SPECS
Static transistor-level timerEinsTLT
Nonlinearoptimizer
LANCELOT
Transistor andwire sizes
Function andgradient values
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Components of EinsTuner
Read netlist; create timing graph (EinsTLT)Formulate pruned optimization problemFeed problem to nonlinear optimizer (LANCELOT)
Snap-to-grid; back-annotate; re-time
Solve optimization problem, call simulatorfor delays/slews and gradients thereof
Obtain converged solution
Fast simulation and incrementalsensitivity computation (SPECS)
12
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![Page 8: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/8.jpg)
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Digression: minimax optimization
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![Page 9: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/9.jpg)
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Springs and planks analogy
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Springs and planks analogy
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![Page 12: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/12.jpg)
Algorithm demonstration: inv3
![Page 13: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/13.jpg)
Algorithm demonstration: 1b ALU
![Page 14: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/14.jpg)
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Constraint generation
![Page 15: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/15.jpg)
Statement of the problem
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![Page 16: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/16.jpg)
LANCELOT• State-of-the-art general-purpose
nonlinear optimizer
• Trust-region method
• Exploitation of group partial separability; augmented Lagrangian merit function
• Handles general linear/nonlinear equalities/inequalities and objective functions
• Simple bounds handled by projections
• Several choices of preconditioners, exact/inexact BQP solution, etc.
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LANCELOT algorithms
Simple bounds
a
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Trust-region
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![Page 18: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/18.jpg)
Demonstration of degeneracy
z
![Page 19: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/19.jpg)
Demonstration of degeneracy
z
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![Page 20: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/20.jpg)
Why do we need pruning?
![Page 21: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/21.jpg)
Pruning: an example
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![Page 22: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/22.jpg)
Block-based vs. path-based timing
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Detailed pruning example
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11
12
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14
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![Page 24: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/24.jpg)
Detailed pruning example
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Detailed pruning example
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![Page 26: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/26.jpg)
Detailed pruning example
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Detailed pruning example
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![Page 28: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/28.jpg)
Detailed pruning example
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![Page 29: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/29.jpg)
Detailed pruning example
9 11,14
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![Page 30: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/30.jpg)
Detailed pruning example
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Detailed pruning example
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Pruning vs. no pruning
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No time to mention...• Simultaneous switching
• Tuning of transmission-gate MUXes
• Adjoint sensitivity computation
• The role of pattern matching
• Strength calculations/symmetrized stacks
• State analysis
• Detection of impossible problems
• Latches
• Uncertainty-aware tuning
![Page 34: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/34.jpg)
EinsTuner impact• Better circuits
– 15%+ on previously hand-tuned circuits!
• Improved productivity in conjunction with semi-custom design flow (see Northrop et al, DAC ’01)
• Better understanding of tradeoffs– lifts designers’ thinking to a higher level
• Currently being applied to third generation of z-series (S/390) and PowerPC microprocessors to benefit from EinsTuner
![Page 35: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/35.jpg)
What we could do with a robust, fast,high-capacity, noise-immune,
degeneracy-immune, easy-to-use,non-finicky nonlinear optimizer
Act II: If only...
What we areable to do
Rich source ofresearch problems
![Page 36: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/36.jpg)
Open research problems
Voltage
Time
• Immunity to numerical noise
![Page 37: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/37.jpg)
Numerical noise• Need a formal basis for optimization in the
presence of inevitable numerical noise
• Formal methods for measuring noise level
• Tie all tolerances to a multiple of noise level– tolerances for bounds– tolerances for updating multipliers, etc.– stopping criteria
• Currently our optimization is a race against noise and the conclusion is not pleasing!
• All optimization decisions noise-based
![Page 38: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/38.jpg)
Numerical noise• Inject various types of
noise (correlated and uncorrelated) with different amplitude into function and gradient evaluation of analytic optimization problems
• Easy experimentation thus possible to test theories of noise-immune optimization
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Capacity• Today, our biggest problem has about
30,000 transistors, 70,000 variables and 70,000 constraints
• Runs for as long as a week!
• We go to great lengths to reduce problem size– in the tuner code– in the pre-processor– in our methodology
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What higher capacity would permit• Tuning of larger macros
• Early mode considerations
• Manufacturability– replicate constraints and variables at each
process corner– rich possibilities in choice of objective function
• Explicit (circuit) noise constraints
• Benefits of explicit grouping constraints in post-optimality analysis
![Page 41: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/41.jpg)
Digression: noise constraints
• Combine Harmony and EinsTuner– essential for dynamic circuits (see TCAD 6/00)– replace rules-of-thumb by actual noise
constraints for static circuits
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![Page 42: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/42.jpg)
Robustness• Scaling
– requires unit change in all variables to have roughly same order of magnitude of impact
– need non-uniform trust-region; would subsume 2-step updating [Conn et al, SIAM J. Opt. 9/99]
– very difficult in general
• Weighting– essential in any large-scale optimizer– need problem-size-dependent weights
• Sensitivity to choices should be minimized– finicky behavior not helpful in engineering
application
![Page 43: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/43.jpg)
Ease of use• Nonlinear optimizers should stop assuming
they are the “master” program
• There is no standard API for nonlinear optimization packages
• Aspects such as error/message handling and memory management are important; FORTRAN does not help
• Not easy to help the optimizer with domain-specific knowledge– e.g., availability of information about Lagrange
multipliers in recursive minimax problems
![Page 44: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/44.jpg)
Mixed integer/continuous problems• Assignment of low threshold voltage
devices
• Swapping pin order in multi-input gates (combinatorial problem)
• Working from a discrete gate library
• Discrete choice of taper ratios
• In general, the type of re-structuring that a logic synthesis program may consider
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Recursive minimax support
• Need a way to force “timing correctness”– arrival times and slews at lowest feasible value– one of them tight at every stage– product of slacks = 0?
.
.
.
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Degeneracy and redundancy• Nonlinear optimizers easy to mislead
• Most engineering problems have plenty of inherent degeneracy and redundancy
• Can optimizers be made less sensitive to degeneracy?
• Example:
is degenerate because
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![Page 47: Optimization Challenges in Transistor Sizing Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY Acknowledgments The entire.](https://reader030.fdocuments.in/reader030/viewer/2022020417/56649f135503460f94c27317/html5/thumbnails/47.jpg)
Practical considerations• Detection of impossible problems
– bound problems– obviously impossible constraints– not-so-obviously impossible constraints that need a
little function evaluation to detect
• Post-optimality analysis– final values of Lagrange multipliers can be used to
give the designer guidance on obtaining further improvement
– may need to re-solve for multipliers at end– information needs to be collected and presented to
designer in nice form– formulation of problem may change to take
advantage of this analysis
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Conclusion (Act I)• Can robustly carry out static circuit tuning
• Consistent and high-quality results
• Improvement in designers’ productivity
• Moves designers’ thinking to a higher level
• Presently impacting third generation ofz-series (S/390) and PowerPC microprocessors
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Conclusion (Act II)• Open problems in nonlinear optimization
whose solution will have a real impact– numerical noise– capacity– robustness, scaling, weighting– ease of use, common API– discrete variables– support for recursive minimax problems– degeneracy– post-optimality analysis– detection of impossible problems