Transistor Characterization and Modeling and the Use of Embedding Device Models for the Design of Microwave Power Amplifiers

Patrick Roblin1, Francisco J. Martinez-Rodriguez1,2, Hsiu Chen Chang1, Chenggang Xie3 and Jose I. Martinez-Lopez2

1Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USA 2Facultad de Ingenieria, Universidad Nacional Autonoma de Mexico, Mexico City 04510, Mexico

3Rockwell Collins, Cedar Rapids, IA 52498, USA

Abstract — Circuit-based large-signal device models remain extensively used to design integrated and hybrid microwave circuits. It has been recently demonstrated that device models can also be profitably applied under the form of a nonlinear embedding device model to help with the synthesis of multi-transistor power amplifiers (PA) such as Doherty PAs. In this paper we shall discuss this new design process from device modeling to PA design. First an example of an Artificial Neural Network (ANN) SOS-MOSFET model directly extracted from large-signal measurements will be reviewed and its companion ANN nonlinear embedding device model presented. Nonlinear embedding device models can be implemented for other models such as the Angelov model to design PAs. A general methodology for designing two-transistor Doherty or Chireix PAs using an embedding device model will be presented and preliminary simulation results on the design of a GaN Chireix amplifier using an Angelov nonlinear embedding device model will be reported.

Index Terms — Device modeling, embedding device model, Chireix power amplifiers.

I. INTRODUCTION

Circuit-based large-signal device models remain the tool of choice to design integrated and hybrid microwave circuits using circuit simulation. It has recently been demonstrated that device models can also be profitably used under the form of a nonlinear embedding device model to help with the synthesis of multi-transistor power amplifiers (PA) [1-2]. In this paper we shall discuss the associated design process starting from the device modeling to the PA design process. First an example of an artificial neural networks (ANN) SOS-MOSFET model directly extracted from large-signal measurements will be reviewed and its companion ANN nonlinear embedding device model presented. Nonlinear embedding device models can be implemented for other models such as the Angelov model to design PAs [1]. A general methodology for designing two-transistor PAs such as Doherty or Chireix PAs using an embedding device model will be presented. Finally, preliminary simulation results on its application to the design of a GaN Chireix amplifier using an Angelov nonlinear embedding device will be reported.

II. DEVICE MODELING

The development of a circuit-based microwave device model is usually an intensive process. However with the advent of NVNAs, circuit-based nonlinear microwave models can nowadays be extracted for a targeted range of operation from a few large-signal measurements [3-7]. An example of SOS-MOSFET model with memory effects extracted from a single 10 ms real-time active load pull (RTALP) was recently reported [8]. The efficient phase sweeping of the RTALP drastically reduces the number of large-signal measurements needed for the model development and verification while maintaining the same intrinsic voltage coverage as in conventional passive or active load–pull systems. The bias dependence of the charges and the current-voltage (IV) characteristics are simultaneously extracted from these measurements using ANNs. Memory effects associated with the parasitic bipolar effect was also extracted that way for improved modeling accuracy. Similarly other memory effects (self-heating, trapping) can be implemented in ANN models for GaN devices [5].

III. EMBEDDING DEVICE MODEL

A general topology for an FET without memory effect for simplicity is shown in Fig. 1. A nonlinear transfer network like the one shown in Fig. 2 can be developed to move the voltages and the currents from the IV current-source reference plane (red) to b) the intrinsic (green), c) the extrinsic (cian), d) the package (blue) and e) the testbed (black) reference planes depending on the needs or application targeted.

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The embedding transfer network in Fig. 2 has the same function as ABCD parameters for linear circuits in the frequency domain but applies instead to nonlinear circuits operating in the time-domain. Combining the transfer network with the IV characteristics like is shown in Fig. 2 yields the embedding device model. Note that self-heating or trapping models can be included as part of the current-voltage plane circuit if the device is affected by low-frequency memory effects.

Fig. 2: The embedding device model realized by combining the Embedding Transfer Network and the IV characteristics of the FET. Self-heating is also included as part of the IV.

Conceptually an embedding device model can be realized by using negative resistances, capacitances, inductance and charges to negate and eventually de-embed the device back to its IV characteristics. This “anti-circuit” implementation is not, however, usually possible in commercial harmonic balance simulators due to stability issues. The reader is referred to [1] for an example of a

practical circuit implementation for the Angelov embedding device model.

Fig. 3: Conceptual realization of an embedding device model from a) the intrinsic current-voltage (IV) reference planes (internal and external red boxes) to the b) extrinsic reference planes (blue box).

An embedding device model for the ANN device model mentioned in Section II and reported in [8], can be similarly implemented by replacing the nonlinear analytic IV and charge expressions of the Angelov model by neural networks used to represent them. To test the functionality of this ANN embedding device model it is sufficient to drive the ANN device model by the ANN embedding device model as shown in Fig. 4. The mutual consistency between these two types of ANN model is demonstrated in Fig. 5 for the targeted intrinsic load lines (a) and projected extrinsic load lines (b) of an SOS-MOSFET.

Fig. 1: Device model including the (a) the current source (red), (b) the intrinsic (green), (c) the extrinsic (cian), (d) the package (blue) and(e) the tesbed (black) reference planes.

0 0.5 1 1.5 2 2.5 3 3.5 4-0.05

0

0.05

0.1

0.15

0.2

vDS(t) (V)

i DS(t

) (A

)

FET model

embedding device

Fig. 4: Embedding device model (left) connected to the device model (right) to test their consistency.

0 0.5 1 1.5 2 2.5 3 3.5 4-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

vDS(t) (V)

i DS(t

) (A

)

FET model

embedding device

Fig. 5. Targeted intrinsic load lines (a) and extrinsic load lines (b) as predicted by the ANN embedding device model (blue line) and verified using the ANN device model (red thick dashed-line).

1. Model-Based Embedding PA Design

The design of single transistor PAs using nonlinear embedding has been extensively investigated [9-10] and multiple PA designs were successfully demonstrated [11-13]. These original embedding PA design approaches relied on combining measured low-frequency loadlines and the charge models separately extracted so as to account for memory effects. In this paper we are focusing instead on the model-based embedding PA design which uses an embedding device model [1] and assumes that a reliable

device model (including low-frequency memory effects if needed) has already been developed using for example the model topologies discussed in Section II.

Our focus in this work is on the design of two-transistor Doherty and Chireix PAs. An account for the Doherty PA has been already reported [2] but a new and general treatment for the redesign of the Doherty or Chireix combiner after nonlinear embedding is given here. The strategy is as follow. In the conventional textbook case, the two transistors are replaced by their IV characteristics as shown in Fig. 6 (a). The two transistor outputs are then combined together using a 3-port loss-less reciprocal network and delivered to the load LR as shown in Fig. 6 (a) for the textbook case. Typically these circuits involve an inverter (Doherty) or offset lines (Chireix, Doherty) and some transformers to realize the optimal impedance targeted at the fundamental frequency. The harmonic termination is assumed to be accounted with a separate network (not shown) before the combiner. Class F operation is selected for the Chireix PA example. The intrinsic reflection coefficients for the Chireix amplifier are shown in Fig. 7 (black and purple circles) under Chireix load modulation. The details of the ideal Chireix combiner used will be reported elsewhere. The extrinsic load impedances at the fundamental required at the package planes for the upper and lower transistors as predicted by the embedding device model from the desired intrinsic loads are shown using blue and green circles.

The question arises now on how to develop the combiner to maintain the desired intrinsic Chireix load pull action. Care must be taken to achieve both the correct large-signal impedance and signal injection since the two FET devices are interacting. ijY parameters can be defined

for this two-port network (red box) at the peak and backoff points. It can be verified (see Appendix) that a reciprocal lossless 3-port can be extracted only if the 2-port ijY parameters are reciprocal 2112 YY = and the

following loss constraint holds:

{ } { } { }22112

12 ReReRe YYY = This holds even if a complex load LZ is used instead of a

real load LR . Some small departures from these conditions are usually observed due to the nonlinear nature of the embedding process. For the 2-port ijY parameter extraction,

focus is placed on the large-signal FET operation at the peak and back-off points. Nonetheless the reciprocity and

(a)

(b)

constraint lead to an over-determined system of equations. An analytic least square extraction or a geometrical average can then be used to obtain ijY parameters verifying exactly

these constraints. Once ijY parameters verifying these

constraints are obtained, the resulting 3-port loss-less reciprocal circuit can then be synthesized exactly from them by using, for example, three different 2-port circuits as shown in Fig. 6 (c). Analytic expressions are also derived for this process.

Fig. 6: (a) Combiner used for the textbook FET IV and (b) new 3-port combiner with the full FET model. The circuit in (c) shows a realization of the 3-port combiner using three 2-port circuits.

Let us consider a 6 dB backoff Chireix PA operating in class F and based on the FET IV characteristics. The trajectories under Chireix load modulation of the internal Gi and external (projected) Gp reflection coefficients are shown in Fig. 7 at the fundamental ω and harmonics frequencies. Both of the paths of this Chireix PA are seen to exhibit the same reflection coefficients Gi(ω) and Gp(ω) at the peak (θ=0) and backoff (θmax) outphasing angles.

Fig. 7 Required extrinsic load reflection coefficients Gp(ω)

(blue and green circles) at the fundamental for the upper and lower transistors predicted by the embedding device model from the intrinsic load reflection coefficients Gi(ω) (black and purple circles) under Chireix load modulation with the FET IV.

Applying the extracted 3-port loss-less combiner circuit

to the Chireix PA using the full FET model, the internal and external Chireix load modulation shown in Fig. 8 can still be observed despite the approximate solution obtained to

enforce the required reciprocity and loss constraints. However, note that the paths of the outphasing Chireix PA no longer exhibit exactly the same reflection coefficients at the peak (θ=0) and backoff (θmax) outphasing angles.

Fig. 8 Resulting extrinsic Gp(ω) (blue and green circles) and intrinsic Gi(ω) (black and purple circles) load reflection coefficients obtained with the device model when using the Chireix combiner analytically extracted from the embedding data obtained in Fig. 7.

Fig. 9 Simulated efficiency obtained for a 6 dB Class F Chireix PA using: 1) the IV characteristic only (top blue line) and 2) the full FET models with the synthesized 3-port network (center red line). The ideal Chireix efficiency with Class B operation is also shown for reference (bottom black line).

The efficiency (middle red line) obtained with the full FET model while using the synthesized loss-less reciprocal network is shown in Fig. 9 to have degraded by 6% compared to the efficiency obtained using the FET IV. The ideal Chireix PA with Class B operation is also shown for reference (bottom black line).

IV. CONCLUSION

In this paper we have reviewed the design of multi-transistor PA using an embedding device model. The

Device Model

Embedding Device Model

application of this method to the design of a two-path Doherty or Chireix amplifier was then discussed. For the the Doherty or Chireix combiner circuit to be implemented at the fundamental frequency using a loss-less circuit, the equivalent two-port network extracted at the peak and backoff points must satisfies both a reciprocity constraint and a loss constraint. Some small departures from these conditions are usually observed due to the nonlinear nature of the embedding process. An approximate design enforcing these constraints can then be developed for the Doherty or Chireix combiner so that the transistors operate close to the targeted internal mode of operation at the peak and backoff points.

ACKNOWLEDGEMENT

This work was supported by the National Science Foundation (NSF) Collaborative under Grant ECS-1129013 and by Rockwell Collins under a project grant.

REFERENCES

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[2] Haedong Jang, Patrick Roblin, Christophe Quindroit, Yiqioa Lin and Robert Pond, “Asymmetric Doherty Power Amplifiers Designed Using Model-Based Nonlinear Embedding,” IEEE Trans. Microwave Theory and Techniques, Vol. 62, pp. 3436-3451, No. 12, Dec. 2014.

[3] M. C. Curras-Francos, “Table-based nonlinear HEMT model extracted from time-domain large-signal measurements,” IEEE Trans. Microwave Theory and Techniques, vol. 53, no. 5, pp. 1593–1600, 2005.

[4] J. Xu, D. Gunyan, M. Iwamoto, A. Cognata, and D. Root, “Measurement-based non-quasi-static large-signal FET model using artificial neural networks,” in Microwave Symposium Digest, 2006. IEEE MTT-S International, pp. 469–472, 2006.

[5] J. Xu, J. Horn, M. Iwamoto, and D. E. Root, “Large-signal FET model with multiple time scale dynamics from nonlinear vector network analyzer data,” in Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International, pp. 417–420, 2010.

[6] D.-P. Schreurs, J. Verspecht, S. Vandenberghe, and E. Vandamme, “Straightforward and accurate nonlinear device model parameterestimation method based on vectorial large-signal measurements,” IEEE Trans. Microwave Theory and Techniques, vol. 50, no. 10, pp. 2315–2319, 2002.

[7] M. Curras-Francos, P. Tasker, M. Fernandez-Barciela, Y. Campos-Roca, and E. Sanchez, “Direct extraction of nonlinear FET QV functions from time domain large signal measurements,” IEEE Microwave and Guided Wave Letters, vol. 10, no. 12, pp. 531–533, 2000.

[8] Youngseo Ko, P. Roblin, A. Zarate-de Landa, Apolinar Reynoso-Hernandez, D. Nobbe, C. Olson, F.J. Martinez, “Artificial Neural Network Model of SOS-MOSFETs Based on Dynamic Large-Signal Measurements,” IEEE Trans. Microwave Theory and Techniques, vol. 62, no. 3, pp. 491-501, 2014.

[9] A. Raffo, F. Scappaviva, and G. Vannini, “A new approach to microwave power amplifier design based on the experimental characterization of the intrinsic electron-device load line,” IEEE Trans. Microwave Theory and Techniques, vol. 57, no. 7, July 2009.

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[13] V. Vadal`a, A. Raffo, S. Di Falco, G. Bosi, A. Nalli, and G. Vannini, ”A loadpull characterization technique accounting for harmonic tuning,” IEEE Trans. Microwave Theory and Techniques, Vol. 61, No. 7, pp. 26952704, Jul. 2013.

APPENDIX

The 3-port combiner used by the 2-path Doherty or Chireix PAs is a reciprocal loss-less device which admits the following Y-parameter representation:

where the 3-port Y-parameters ijy are pure imaginary. The 2-port network defined in Fig. 6 (a) admits thus the following Y-parameters:

where the loaded 2-port and 3-port Y-parameters are related by the simple relationship:

(1)

(2)

(3)

The 2-port network is lossy and thus the 2-port Y-parameters klY feature a non-zero klR real part:

3332231133

3232221122

3132121111

vyvyvyivyvyvyi

vyvyvyi

++=++=++=

2221122

2121111

vYvYivYvYi

+=+=

{ } { } . Im Re

andwith klklklkl

klklkl

YIYRIjRY

==+=

.1

1

1

33

223

2222

33

23131212

33

213

1111

yRRyyY

yRRyyyY

yRRyyY

L

L

L

L

L

L

+−=

+−=

+−=

Now since the terms LR , 213y , 2

23y and 2313 yy are real, and

the kly pure imaginary, we have the following identities:

From (1), (2) and (3) we have the following ratios:

(4)

(5)

Equating (4) and (5) we obtain the final identity: 1211

212 RRR =

or equivalently:

{ } { } { } . ReReRe 22112

12 YYY =

The same constraint is also required if a complex load

LZ is used instead of the real load LR .

. 222222

121212

111111

RyYRyYRyY

=−=−=−

. 12

22

13

23

1212

2222

12

11

23

13

1212

1111

RR

yy

yYyY

RR

yy

yYyY

==−−

==−−