TPS2384 - Texas Instruments

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FEATURES APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION

PSE

+48 V

SCLSDA - ISDA - O

TPS2384

OptionalMSP430Micro-

Controller

+48 VReturn

Spare Pair

Singnal Pair

Singnal Pair

Spare Pair

TPS2375

ILIMCLASS DC/DC

Converter

RJ45 RJ45Up to 100 m

of CAT 5

TPS2384SLUS634D–NOVEMBER 2004–REVISED MARCH 2007

QUAD INTEGRATED POWER SOURCING EQUIPMENT POWER MANAGER

• Ethernet Enterprise Switches• Quad-Port Power Management With IntegratedSwitches and Sense Resistors • Ethernet Hubs

• SOHO Hubs• Compliant to IEEE 802.3af Standard• Ethernet Mid-Spans• Operates from a Single 48-V Input Supply• PSE Injectors• Individual Port 15-bit A/D

• Auto, Semi-Auto and Power ManagementOperating Modes

The TPS2384 is a quad-port power sourcing• Controlled Current Ramps for Reduced EMIequipment power manager (PSEPM) and isand Charging of PD's Bulk Capacitancecompliant to the Power-over-Ethernet (PoE) IEEE

• I2C Clock and Oscillator Watchdog Timers 802.3af standard. The TPS2384 operates from a• Over-Temperature Protection single 48-V supply and over a wide temperature

range (–40°C to 125°C). The integrated output• DC and DC Modulated Disconnecteliminates two external components per port (FET• Supports Legacy Detection for Non-Compliant and sense resistor) and will survive 100-V transients.

PD's Four individual 15-bit A/D converters are used to• Supports AC Disconnect measure port resistance, voltage, current and die

temperature making PSE solutions simple and• High-Speed 400-kHz I2C Interfacerobust. The TPS2384 comes with a comprehensive• Comprehensive Power Management Software software solution to meet the most demanding

Available applications which can serve as a core for all PoE• Operating Temperature Range –40°C to 125°C system designs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright © 2004–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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DESCRIPTION (CONTINUED)


The TPS2384 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply.These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought outseparately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for poweringexternal loads up to 2 mA. For more demanding loads it is highly recommended to use external buffers toprevent system degradation. When the TPS2384 is initially powered up an internal Power-on-Reset (POR)circuit resets all registers and sets all ports to the off state to ensure that the device is powered up in a knownsafe operating state.

The TPS2384 has three modes of operation; automode (AM), semi-automode (SAM) and power managementmode (PMM).• In auto mode the TPS2384 performs discovery, classification and delivery of power autonomously to a

compliant PD without the need of a micro-controller.• In semi-automode the TPS2384 operates in automode but users can access the contents of all read status

registers and A/D registers through the I2C serial interface. All write control registers are active except for D0through D3 of Port Control register 1 (Address 0010) for limited port control. The semi-auto mode allows theTPS2384 to detect valid PD's without micro-controller intervention but adds a flexibility to perform powermanagement activities.

• Power management mode (with a micro-controller) allows users additional capabilities of discoveringnon-compliant (legacy) PDs, performing AC Disconnect and advanced power management system controlthat are based on real time port voltages and currents. All functions in this mode are programmed andcontrolled through read/write registers over the I2C interface. This allows users complete freedom indetecting and powering devices. A comprehensive software package is available that mates the power of theTPS2384 with the MSP430 micro-controller.

TPS2384 integrated output stage provides port power and low-side control. The internal low-side circuitry isdesigned with internal current sensing so there are no external resistors required. The output design ensures thepower switches operate in the fully enhanced mode for low power dissipation.

The I2C interface allows easy application of opto-coupler circuitry to maintain Ethernet port isolation when aground based micro-controller is required. The TPS2384 five address pins (A1–A5) allow the device to beaddressed at one of 31 possible I2C addresses. Per-port write registers separately control each port state(discovery, classification, legacy, power up, etc) while the read registers contain status information of the entireprocess along with parametric values of discovery, classification, and real-time port operating current, voltageand die temperature.

The proprietary 15-bit integrating A/D converter is designed to meet the harsh environment where the PSEPMresides. The converter is set for maximum rejection of power line noise allowing it to make accuratemeasurements of line currents during discovery, classification and power delivery for reliable powermanagement decisions.

TheTPS2384 is available in either 64-pin PowerPAD™ down (PAP) or 64-pin PowerPAD™ up (PJD) packages.

ORDERING INFORMATION

TEMPERATURE RANGE PACKAGED DEVICES (1)

TA = TJ TQFP – 64 (PAP) (2) TQFP – 64 (PJD) (2)

–40°C to 125°C TPS2384PAP TPS2384PJD

(1) The PAP and PJD packages are available taped and reeled. Add R suffix to device type(e.g.TPS2384PAPR) to order quantities of 1000 devices per reel.

(2) PAP = PowerPad™ down, PJD = PowerPad™ up.

2 Submit Documentation Feedback


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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS (1)

RECOMMENDED OPERATING CONDITIONS

ELECTRO STATIC DISCHARGE (ESD) PROTECTION

ELECTRICAL CHARACTERISTICS


over operating free-air temperature range (unless otherwise noted) (1) (2)

VALUE UNIT

V10 current sourced 100 µA

V3.3 current sourced 5 mA

Applied voltage on CINT#, CT, RBIAS –0.5 to 10

Applied voltage on SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, MS, PORB, WD_DIS, –0.5 to 6 VALT_A/B, AC_LO, AC_HI

Applied voltage on V48, P#, N# –0.5 to 80

TJ Junction operating temperature –40 to 125

Tstg Storage temperature -55 to 150 –55 to 150 °C

Tsol Lead temperature (soldering, 10 sec.) 260

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

THERMAL RESISTANCE THERMAL RESISTANCEPACKAGE JUNCTION TO CASE θJC JUNCTION TO AMBIENT θJA

PAP 0.38°C/W 21.47°C/W

PJD 0.38°C/W 21.47°C/W

(1) Thermal Resistance measured using 2-oz copper trace and copper pad solder following layout recommendation in TI PublicationPowerPAD Thermally Enhance Package Technical Brief SLMA002.

PARAMETER MIN TYP MAX UNIT

VDD Input voltage, V48 44 48 57 V

TJ Junction temperature -40 125 °C

MAX UNIT

Human body model 1.5

CDM 1 kV

Machine model 0.2

V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power Supply

V48 quiescent current Off mode (all ports) 4 9 12mA

V48 quiescent current Powered mode (all ports) 10 14

V10, internal analog supply ILOAD = 0 9.75 10.5 11.5V

V3.3, internal digital supply ILOAD = 0 to 3 mA 3 3.3 3.7

V3.3 short circuit current V = 0 3 12 mA

V6.3, internal supply ILOAD = 0 5 6.3 7

V2.5, internal reference supply ILOAD = 0 2.46 2.5 2.54 V

Input UVLO 26 32

Internal POR time out(I2C) After all supplies are good I2C activity is valid 8 ClockPulsesInternal POR time out (Port) After all supplies are good Port active to I2C commands 66000

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www.ti.comTPS2384SLUS634D–NOVEMBER 2004–REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS (continued)V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)


Port Discovery

Port off #P to #N input resistance 400 600 kΩ

Discovery open circuit voltage 22 30

Discovery 1 voltage loop control 70 µA < IPORT < 3 mA 2.8 4.4 V

Discovery 2 voltage loop control 70 µA < IPORT < 3 mA 8.8 10

Discovery current limit P = N = 48 V 3 4 5 mA

Auto-mode discovery resistance 19 26.5acceptance Band

Auto-mode discovery resistance low end 0 15 kΩrejection

Auto-mode discovery resistance high end 33rejection

Discovery1,2 A/D conversion scale factor 100 µA < IPORT < 3 mA 5.30 6.10 6.75 count/µA

Discovery1,2 A/D conversion time IPORT= 120 µA ms

Port Classification

Classification voltage loop controll 100 µA < IPORT < 50 mA 15 17.5 20 V

Classification current limit P = N = 48 V 50 60 100

Class 0 to 1 detection threshold 5.5 6.5 7.5

Class 1 to 2 detection threshold 13 14.5 16mA

Class 2 to 3 detection threshold 21 23 25



Count/mClassification A/D conversion scale factor 375 424 475 A

Classification A/D conversion time IPORT = 50 mA 18 22 ms

Port Legacy Detection

Legacy current limit P = N = 48 V 2.6 3.5 4.3 mA

Legacy voltage A/D conversion scale 100 mV < VPORT < 17.5 V 1365 1400 1445 Count/Vfactor

Legacy A/D conversion time 0 V < VPORT < 15 V 18 22 ms

Port Powered Mode

Port on resistance 20 mA < IPORT < 300 mA 1.3 1.8 Ω

Over current threshold (ICUT) 350 375 400RBIAS = 124 kΩ, CT = 220 pF, –25 ≤ TJ≤ 105

Output current limit (ILIM) 425 450 mA

Disconnect timer current threshold RBIAS = 124 kΩ, CT = 220 pF 7.5 10

TMPDO, disconnect detection time RBIAS = 124 kΩ, CT = 220 pF, ILOAD < current threshold 300 400 ms

Port output UV 42.0 42.7 44.0V

Port output OV 54 55 56

Over current time out (TOVLD) RBIAS = 124 kΩ, CT = 220 pF 50 75

Short circuit time out (TLIM) RBIAS = 124 kΩ, CT = 220 pF 50 75 msRBIAS = 124 kΩ, CT = 220 pF, After port enabled andTurn--off delay from UV/OV faults 3ramped up

Count/mPort current A/D conversion scale factor 20 mA < IPORT < 56 V 31 36.41 40 A

Port curent A/D conversion time IPORT < 300 mA 18 22 ms

Port voltage A/D conversion scale factor 335 353 370 Count/V45 V < VPORT < 56 V

Port voltage A/D conversion time 18 22 ms

Port temperature A/D conversion (17500 - counts)/16 °C




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SLUS634D–NOVEMBER 2004–REVISED MARCH 2007

ELECTRICAL CHARACTERISTICS (continued)V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted)


Port Disable Mode

Port N voltage P = 48 V 47 V

AC LO and AC HI Specification

AC_LO, AC_HI – low output voltage 0 0.5

AC_LO – high output voltage 3.0 5.0 V

AC_HI – high output voltage 5.0 7.0

Digital I2C DC Specifications

SCL, SDA_I, A1–A5 ,WD_DIS, ALTA/B, 1.5 VMS, PORB logic input threshold

SCL, SDA_I input hysteresis 250mV

MS, PORB input hysteresis 150

WD_DIS,ALTA/B, MS, PORB input Input voltage 0.5 to 3 V 50 kΩpulldown resistance

A1–A5 pull-down current 10 µA

SDA_O logic high leakage Drain = 5 V 100 nA

SDA_O logic low ISINK = 10 mA 200 mV

INTB logic high leakage Drain = 6 V 10 µA

INTB logic low ISINK = 10 mA 200 mV

Digital I2C Timing

SCL clock frequency 0 400 kHz

SCL high 0.6Pulse duration

SCL low 1.3

Rise time, SCL to SDA 0.300

Fall time, SCL to SDA 0.300

Setup time, SDA to SCL 0.250µs

Hold time, SCL to SDA 0.300 0.900

Bus free time between start and stop 1.3

Setup time, SCL to start condition 0.6

Hold time, start condition to SCL 0.6

Setup time, SCL to stop condition 0.6




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TPS2384 SINGLE PORT BLOCK DIAGRAM

Two8 BitsStatus

Register

UV/OVComparators

Two8 BitsStatus

Register

AutoSeq

Logic

A2DRegisters

ResistorVoltageCurrent

&Die Temp

AnalogControlCircurty

Diff Amp(Fix Gain)

Loop Cntri AmpDetect/Class Modes

LCAPower Mode

ThermalDetector

OVIThld

OVI

Max IThld

600 kW





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TERMINAL FUNCTIONS

TERMINAL

NO. I/O DESCRIPTIONNAME

PAP PDJ

Power and Ground

48-V input to the device. This supply can have a range of 44 to 57 V. This pin should be decoupledV48 60 5 I with a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible.

10-V analog supply. The 10-V reference is generated internally and connects to the main internalV10 58 7 O analog power bus. A 0.1-µF de-coupling capacitor should terminate as close to this node and the

AG1 pin as possible. Do not use for an external supply.

6.3-V analog supply. A 0.1-µF de-coupling capacitor should terminate as close to this pin and theV6.3 59 6 O AG1 pin as possible. Do not use for an external supply.

3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic powerV3.3 24 41 O bus. A 0.1-µìF de-coupling capacitor should terminate as close to this node and the DG pin as

possible. This output can be used as a low current supply to external logic.

2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference powerV2.5 54 11 O bus. This pin should not be tied to any external supplies. A 0.1-µF de-coupling capacitor should

terminate as close to this node and the RG pin as possible. Do not use for an external supply.

Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should beAG1 57 8 GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three

de-coupling capacitors tied to V48, V10 and V6.3.

Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of theAG2 61 4 GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be

tied together directly for the best noise immunity.

Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to theDG 23 42 GND common copper 48-V return plane.

Reference ground. This is a precision sense of the external ground plane. The integration capacitor(CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also beRG 56 9 GND used to form a printed wiring board ground guard ring around the active node of the integrationcapacitor (CINT). It should tie to common copper 48-V return plane.

Port Analog Signal

P1 7 58 IPort Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially withP2 10 55 Irespect to each Port N pin. Optionally, if the application warrants, this high-side path can be

P3 39 26 I protected with the use of a self-resetting poly fuse.P4 42 23 I

N1 6 59 I

N2 11 54 I Port negative. 48-V load return pin. The low side of the load is switched and protected by internalcircuitry that limits the current.N3 38 27 I

N4 43 22 I

RET1 5 60 I

RET2 12 53 I48 V return pin.

RET3 37 28 I

RET4 44 21 I

CINT1 4 61 IIntegration capacitor This capacitor is used for the ramp A/D converter signal integration. Connect A

CINT2 13 52 I 0.027- µF capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene,polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used withCINT3 36 29 Iincreased conversion error.

CINT4 45 20 I





TERMINAL FUNCTIONS (continued)

TERMINAL

NO. I/O DESCRIPTIONNAME

PAP PDJ

Analog Signals

This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. Whenthe CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description).

The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of theCT 53 12 I device. This internal clock is used for the internal state machine, integrating A/D counters, POR time

out, faults and delay timers of each port. Using a 220-pF capacitor for CT and a 124-kΩ resistor forRBIAS sets the internal clock to 245 kHz and ensure IEEE 802.3af compliance along with maximizingthe rejection of 60-Hz line frequency noise from A/D measurements.

Bias set resistor. This resistor sets all precision bias currents within the chip. This pin will regulate to1.25V (V2.5/2) when a resistor is connected between RBIAS and RG. This voltage and RBIASgenerate a current which is replicated and used throughout the chip. This resistor also works inRBIAS 55 10 I conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistorshould be connected RG. RBIAS is a high impedance input and care needs to be taken to avoidsignal injection from the SYN pin or I2C signals.

This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0V to 3.3V pulse of the internal clock which can be used to drive other TPS2384 SYN pins forSYN 52 13 I/O elimination of a timing capacitor. When the CT pin is grounded this pin becomes an input pin that canbe driven from a master TPS2384 or any other clock generator signal.

AC_LO 51 14 O Totem-pole output pin for AC Disconnect excitation.

AC_HI 50 15 O Totem-pole output pin for AC Disconnect excitation.

Digital Signals

SCL 25 40 I Serial clock input pin for the I2C interface.

Serial data input pin for the I2C interface. When tied to the SDA_O pin, this connection becomes theSDA_I 26 39 I standard bi-directional serial data line (SDA)

Serial data open drain output for the I2C interface. When tied to the SDA_I pin, this connectionSDA_O 27 38 O becomes the standard bi-directional serial data line (SDA). This is a open drain output that can

directly drive opto-coupler.

The WD_DIS pin disables the watchdog timer function when connected to 3.3 V. The pin has internalWD_DIS 22 43 I 50-kΩ resistor to digital ground. The watchdog timer monitors the I2C clock pin (SCL) and the internal

oscillator activity in power management mode and only the internal oscillator activity in auto mode.

INTB 20 45 O This is an open-drain output that goes low if a fault condition occurs on any of the 4 ports.

When this input is set to logic low there is no back-off time after a discovery failure. When this pin setALTA/B 21 44 I to a logic high there is a back-off time (approximately 2 seconds) before initiating another discovery

cycle. This pin has an internal 50-kΩ resistor pull-down to digital ground.

A1 28 37 I

A2 29 36 I Address 1 through 5 These are the I2C address select inputs. Select the appropriate binary addressA3 30 35 I on these pins by connecting to chip ground for a logic low or tying to the V3.3 pin for a logic high.

Each address line has an internal current source pull-down to digital ground.A4 31 34 I

A5 32 33 I

The MS pin selects either the auto mode (MS low) or the power management mode, PMM, (MShigh). This pin can be held low for controller-less standalone applications. When MS is low and the

MS 63 2 I POR timing cycle is complete the chip will sequentially Discover, Classify and Power on each port.When MS is set high the ports are controlled by register setting via the I2C bus. The MS pin has aninternal 50-kΩ resistor pull-down to analog ground.

This pin can be used to override the internal POR. When held low, the I2C interface, all the statemachines, and registers are held in reset. When all internal and external supplies are withinspecification, and this pin is set to a logic high level, the POR delay will begin. The I2C interface andPORB 62 3 I registers will become active within 70 µs of this event and communications to read or preset registerscan begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin hasan internal 50-kΩ resistor pull-down to analog ground.




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CONNECTION DIAGRAM

TPS238464 Pin Power Pad

TQFP_PAP


(1) NIC = No internal connection. Pins are floating.

(2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection fromunused pins.

(3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.




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LASER MARKERPIN 1 IDENTIFIER

POWERPADOUTLINE

TOP VIEWTPS2384

64 PIN POWER PADUP

TQFP - PJD


(1) NIC = No internal connection. Pins are floating.

(2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection fromunused pins.

(3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.




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AUTO MODE FUNCTIONAL DESCRIPTION

Auto Mode


Auto mode (AM, MS = 0) operation is the basic approach for applying power to IEEE compliant PD’s. When AMhas been selected the TPS2384 automatically performs the following functions:• Discovery of IEEE 802.3af compliant powered devices (PD's)• Classification• Power delivery• Port over/under voltage detection• Port over current detection (350 mA < IPORT < 400 mA• Port maximum current limit (400 mA < IPORT < 450 mA)• DC Disconnect (5 mA < IPORT < 10 mA)• Thermal shutdown protection (TSD), (TJ > 150°C)• Internal oscillator watchdog

In AM the contents of all read registers are available via the I2C interface. In addition all control registers exceptfor the function bits can be written. This supports a semi-automode where the TPS2384 auto detects compliantPD's while a host can access the A/D registers and class information and then implement power management(including turning a port off, responding to faults, etc).

The write registers that are still active in AM are:• All ports disable – Common Control register 0001b• Over/Under Voltage Faults – Common Control register 0001b• Software reset – Common Control register 0001b• Disconnect disable – Port Control 1 register 0010b• Discovery fault disable – Port Control 1 register 0010b• Port enable – Port Control 2 register 0011b

For Alternative B, semi-auto mode implementations which will manipulate the all Ports Disable or Port Enablebits, please contact the factory for additional application information.




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Auto Mode Functional Description

UpdateClass Register

PortPwrUpdate Reg

A2D V/IMeasurements

300 ms<t <400 msMPDO

OVI = Over Current FaultU/O V = Under or Over Voltage FaultTSD = Thermal Shutdown FaultTMPDO = PD Maintain Power Dropout Time LimitTED = Error Delay Timing


AUTO MODE FUNCTIONAL DESCRIPTION (continued)

Figure 1. The Basic Flow for Auto Mode




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AM Discovery



The TPS2384 uses a four-point measurment technique using two low level probe signals (typically 4.4 V and 8.8V) during the discovery process to determine whether a valid PD is present. The use of a multipoint detectionmethod for the PD resistor measurement allows accurate detection even when series steering diodes arepresent. The low level probe voltages also prevent damage to non-802.3 devices. When a valid PD has beendetected the TPS2384 moves to classification. If a valid PD has not been detected the TPS2384 continues tocycle through the discovery process. The waveform in Figure 2 shows typical N-pin waveforms for the discoveryof a valid PD and the failure to discovery due to a discovery resistor of 15 kΩ and 33 kΩ.

Figure 2.




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AM Classification



After a successful discovery of a valid PD theTPS2384 enters the classification function that identifies the powerlevel based on the PD's current signature. The classification current level is measured at a reduced terminalvoltage of 17.5 V. During classification the power dissipation can be at its highest; therefore, to prevent overtemperature shutdown in auto mode only one port classifies at a time. When multiple ports successfully discoverand proceed to classification at the same time the auto sequencer processes each request separately allowingonly one port to enter classification. Figure 3 shows all 4 ports successfully detecting a valid PD at the sametime and than the classification of each port occurring separately.

Figure 3.




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0or1

0or1or2

0or2or31 2

0 10 20 30 40 6050

4

3

2

1

0



Upon completion of classification the port classification register is updated. In AM mode this information is notused but for semi-auto mode the class information can be used for power management. Figure 4 shows actualclass currents and the class assignment which were stored in the register. These assignments are compliantwith the IEEE 802.3af Standard

Figure 4.




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AM Power Delivery

AM Faults and INTB Output



After successfully discovery and classification of a valid PD the power is delivered by controlling the current tothe PD until its current requirements are met or until the internal current limit is reached (approximately 425 mA).The power switch is fully enhanced after 500 µs. Figure 5 show the voltage and the current that is being appliedto the PD during power-up and reaching the PD load of 250 mA.

Figure 5.

After power has been applied to the PD the TPS2384 automatically enters the current and voltage samplemode. The sample mode performs 31 current measurements and 1 voltage measurement. Each measurementtakes approximately 18 ms to complete. The port remains powered and the current/voltage measurement cyclecontinues until a fault condition occurs. The current and voltage measurements are both stored in the A/Dcurrent and voltage registers and can be accessed through the I2C pins. This allows power management in theAM if it is desired.

AM faults are:• Port under and over voltage faults• Over current faults• Under current (DC Disconnect) fault• Thermal shutdown (TSD) fault• Watchdog timer faults (disabled via WD_DIS pin)

Any one of the first four fault conditions listed above causes the port to shut down, and a 3-bit fault code to belatched into the affected port's Status Read 1 register (addr = 0100b). Watchdog faults cause all four ports toshut down. Faulted ports are temporarily disabled after a fault has been detected and latched.

The INTB pin is an open-drain, active-low output which is asserted if a fault condition occurs on any of the fourports. This indication is asserted for any of the port faults which result in a code displayed in the port statusregister (the faults listed in Table 8). In automode, the fault latch, the status register fault bits, and consequently,INTB assertion, are cleared by expiration of the 750-ms TED timer.




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Over/Under Voltage Fault



Over/under voltage faults are only processed after port powerup has completed (voltage/power ramp to PD isdone). The TPS2384 measures the voltage between the P and N pin and if this voltage drops below the undervoltage threshold (typically 43 V) or increases above the over voltage threshold (typically 55 V) the voltage timeris turned on. When the voltage timer reaches its time-out limit that is set between 2 ms to 5 ms thecorresponding port is turned off and the UV/OV fault code generated in the Port Status 1 register. If theover/under voltage condition is removed prior to the voltage timer reaching its limit the timer is reset and waitsfor the next event. Figure 6 shows a voltage fault lasting for more then 2 ms that has caused the port toshutdown.

Figure 6.




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Over Current or Current Limit Faults



Over current or current limit faults are conditions when the load current that is being sensed trips either the ICUTcomparator (350 mA to 400 mA) or the ILIM comparator (400 mA to 450 mA) and turns on the current fault timer.When the over current timer reaches its time out limit that is set between 50 ms to 75 ms the corresponding portis turned off and the over current fault code generated in the Port Status 1 register. If the over current conditiongoes away prior to the over current timer reaching its limit the timer is reset and waits for the next event.Figure 7 shows an over current fault lasting more than 50 ms that has caused the port to shut off.

Figure 7.




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Under Current Fault (DC Modulated Disconnect)



Under current fault (dc modulated disconnect) is a condition when the load current that is being measured dropsbelow 7.5 mA and turns on the disconnect timer. If the disconnect timer reaches its time out limit that is setbetween 300 ms to 400 ms the corresponding port is turned off and the load disconnect fault code generated inthe Port Status 1 register. If the under current condition goes away prior to the disconnect timer reaching its limitthe timer is reset and the port remains powered.

Figure 8 shows DC Disconnect event. In this setup the load current was set right above the 7.5-mA threshold.The duty cycle of the load was then adjusted until the off period exceeded the disconnect time out, causingturn-off of the port. The time-out period was > 300 ms.

Figure 8.




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POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION

Power Management Mode (PMM)

13 Funcitons


Power management mode (PMM) has been designed to work efficiently with simple low-cost microcontrollerssuch as those in the MSP430 family.

The power management mode uses 13 self-contained functions to completely control the device operation. Yousimply write/read through the I2C pins and wait for the function done bit to be set. If an A/D measurement wasperformed during the function the results can be accessed by going to the read mode and addressing the properregister.

• Disable: Disable the port and reset all functions.• Discovery 1: Enable the Discovery 1 condition which applies a 4.4 V across the PD and measure and store

the resulting current.• Discovery 2: Enable the Discovery 2 condition which applies a 8.8 V across the PD and measure and store

the resulting current.• V Sample: Measure the voltage between the P and N pins and store the result in the A/D voltage register.• Legacy: Enable the 3.5-mA current source for measuring capacitance and measure the voltage across the P

and N terminals and store the result in the A/D voltage register.• Classify: Enable the classification condition which applies 17.7 V across the PD and measure and store the

resulting current.• Rup Pwr: Turn on the output switch while controlling the current being delivered to the PD until the PD

current needs are met or the max current is reached.• C Sample: Continuous cycle of 31 current measurements and 1 voltage measurement. After each

measurement the contents of the appropriate register are updated.• Rdwn: Turn off the output switch while controlling current until output current reaches 0 mA.• AC LO: Turns on low side output FET and measures voltage between P and N pin and store result in A/D

voltage registers.• AC HI: Turns on high side output FET and measures voltage between P and N pin and store result in A/D

voltage registers.• ISample: Measure the current and store the result in the A/D current register.• TSample: Measure the internal die temperature and store the result in the A/D temperature register.

Conversion times for A/D measurements performed as part of the functions listed above are generally asshown in the typical values in the Electrical Characteristics table. However, conversion time is somewhatdependant on the magnitude of the input signal being measured. Power management mode applicationsshould take precautions to test the A/D DONE bit (MSB of the high byte) of the pertinent results registerbefore accepting or using the returned value. A logic 1 at this bit location indicates the conversion iscomplete. Also, once an A/D conversion is in process on a given port, subsequent function calls to that portshould wait until the currently executing conversion is complete. Commands written prior to completion maycause the results of the initial conversion to be written to the register of the subsequent function.




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Decoder

Dis

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0000

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1

0001

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VS

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POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued)

Figure 9.




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PMM Discovery 1



PMM Discovery 1 function waveforms for the N and CINT pins are shown in Figure 10. The measurement isbeing performed using 25-kΩ impedance between the P and N pin. The Discovery 1 voltage is allowed to settlefor approximately 5 ms before the A/D begins integrating. The voltage on the CINT pin shows the A/D cycle.There are four distinct regions to any A/D cycle: precharge (to a known starting voltage), charge, coarsedischarge, and fine discharge. CINT pin is very high impedance therefore extreme care must be taken to avoidany noise or leakage affecting this pin. For the measurements where CINT voltage is shown a buffer was usedto prevent performance degradation. The A/D measurement time is approximately 18 ms. The entire Discovery 1function takes approximately 22 ms to complete. At the end of the A/D cycle the Discovery 1 current is stored inthe Discovery Current Register and the function done bit is set. The applied Discovery 1 voltage level remainsuntil a new function is called. The data for this measurement remains stored in the Discovery Current Registeruntil another Discovery 1 or 2 function is called.

Figure 10.




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PMM Discovery 2



PMM Discovery 2 function waveforms for the N and CINT pins are shown in Figure 11. Again the measurementis being performed using 25 kΩ impedance between the P and N pin. The Discovery 2 function was called aftera Discovery 1 function so the voltage ramps from 4.4 V to 8.8 V below the P pin. The Discovery 2 voltage isgiven 5 ms to settle before the A/D begins to integrate. At the end of the A/D cycle the Discovery 2 current isstored in the Port Discovery Current Register and the function done bit is set. The applied Discovery 2 voltagelevel remains until a new function is called. The data for this measurement remains stored in the DiscoveryCurrent Register until another Discovery 1 or 2 function is called.

Figure 11.




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PMM Classification

PMM Legacy

0 60 110

5000

4500

3000

2500

2000

500

0

10 30 40 80 100

4000

1000

90705020

1500

3500

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PMM Classification function looks similar to Discovery 1 and 2 except that the voltage between the P and N pinsregulates to approximately 17.5 V. At the end of the A/D cycle the classification current is stored in the PortCurrent Register and the done bit is set. The applied classification level remains until a new function is called.The data for this measurement remains stored in the Port Current Register until either the Classify or ISamplefunction is called.

As indicated in the flow diagram of Figure 1, the TPS2384 in AM only performs classification at one port at atime. Similarly, PMM applications should take care to ensure that only one port per device is put into theclassification mode at any one time to limit power dissipation in the package.

PMM Legacy function is used to detect PDs that are non compliant. Legacy detection uses a current source(typically 3.5 mA) as a test current while the A/D measures the average voltage for approximately 18 ms. Thewaveform shown in Figure 12 is the Legacy function charging a 10-µF capacitor. The capacitance charges to avalue that is no greater than 20 V below the P port voltage. As the capacitor is charging the A/D is accumulatingcounts in the voltage A/D register. Figure 13 shows the relationship between port capacitance and the number ofcounts. A user can characterize non-compliant PD's signatures and use the Legacy function to recognize thesedevices.

Figure 12. Figure 13.




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PMM Rup Pwru



PMM Rup Pwr function turns on the port power by ramping up the current that is being delivered to the load in acontrolled fashion. The output current ramps from 0 mA to ILIM (typically 425 mA) in approximately 500 µs.Figure 14 shows the output voltage and current turning on for a 250-mA load.

Figure 14.




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PMM RDWN

t - Time - 100 s/divm



PMM RDWN function turns off the port power by ramping down the current in a controlled fashion. The outputcurrent ramps from ILIM (typically 425 mA) to 0 mA in approximately 300 µs. Figure 15 shows the output voltageand current shutting down for a 250-mA load.

Figure 15.




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MISCELLANEOUS FUNCTIONAL DESCRIPTION

PMM Faults

Watchdog Timer


PMM faults are the same as those shown in the AM Faults and INTB Output section. In PM mode, the portunder- and overvoltage and under-current faults can be disabled by writing to the control bits in the appropriateregister. Monitoring for these fault conditions is enabled by default after device POR or other reset operation.The enable state of these features can be toggled by writing to the corresponding control bit as defined belowand in Table 4 and Table 5.

The PMM faults are:• Port under- and over-voltage faults (disable via Common Control register 0001b, bit D2)• Overcurrent fault (cannot be disabled)• Under-current (DC Disconnect) fault (disable via Port Control register 0010b, bit D4)• Thermal shutdown (TSD) fault (cannot be disabled)• Watchdog fault (disable via WD_DIS pin)

Any one of these faults causes the port to shutdown. Once a fault has occurred the port can not be repowereduntil a Disable function is sent. The Disable function clears the fault latch and the fault register.

INTB pin operation is essentially the same in PMM as in AM, with the following exceptions:• For load under-current to generate a fault shutdown and status indication, the condition of load current less

than the threshold must be detected by the continuous sample (C_SAMPLE) function (0111b).• In PMM only, a Watchdog timer fault also asserts INTB.

TPS2384 has two watchdog timers. One monitors the I2C clock and the other monitors the internal clock. Whenautomode is selected and the watchdog timer has not been disabled only the internal clock ismonitored. When inpower management mode and the watchdog timer has not been disabled then both the I2C and internal clocksare monitored. If there is no I2C clock activity for approximately two seconds then all ports are disabled. Thereare three means to enable ports after a I2C clock fault and they are:

1. Hard power reset2. PORB pulse3. Writing a software reset to the Common Control register

In both auto mode and power management mode if the internal oscillator is lost for more than 20 ms all portsare disabled.

Loss of these signals is considered catastrophic since the system loses its ability to talk to each port. Thereforethe watchdog timers disabling all ports protects the system.

This function can be easily over ridden by setting the WD_DIS pin high.




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I2C Interface Description


The serial interface used in the TPS2384 is a standard 2-wire I2C slave architecture. The standard SDA line ofthe I2C architecture is broken out into independent input and output data paths. This feature simplifies earthgrounded controller applications that require opto-isolators to keep the 48-V return of the Ethernet power systemfloating. For applications where opto-isolation is not required, the bidirectional property of the SDA line can berestored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line as the TPS2384 isalways accessed as a slave device and it never masters the bus.

Data transfers that require a data-flow reversal on the SDA line are 4-byte operations. This occurs during aTPS2384 port read cycle where a slave address byte is sent, followed by a port/register address byte write. Asecond slave address byte is sent followed by the data byte read using the port/register setup from the secondbyte in the sequence.

The I2C interface and the port read write registers are held in active reset until all input voltages are withinspecifications (V10, V6.3, V3.3 and V2.5) and the internal POR timer has timed out (see electricalspecifications).

The I2C read cycle consists of the following steps 1 through 14 and is shown in Figure 16:1. Start Sequence (S)2. Device address field3. Write4. Acknowledge5. Register/Port address6. Acknowledge7. Stop8. Start9. Device address field10. Read11. Acknowledge12. Data Transfer13. Acknowledge14. Stop

Data write transfers to the TPS2384 do not require a data-flow reversal and as such only a 3-byte operation isrequired. The sequence in this case would be to send a slave device address byte, followed by a write of theport/register address followed by a write of the data byte for the addressed port.

The I2C write cycle consists of the following steps 1 through 9 and is also shown in Figure 16:1. Start Sequence (S)2. Device address field3. Write4. Acknowledge5. Register/Port address6. Acknowledge7. Data for TPS23848. Acknowledge9. Stop




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Start/Stop

Chip Address

SCL

SDA

Clo

ck

Da

ta1

Va

lue

Clo

ck

Da

ta1

Va

lue

Clo

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Da

ta0

Va

lue

Clo

ck

Da

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Va

lue

Write Cycle

SDA_I

ReadCycle

SDA_O

A7 A6 A5 A4 A3 A2 A1 A0 D7 R3 R2 R1 R0 D2 P1 P0 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0 D7 R3 R2 R1 R0 D2 P1 P0 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

Sta

rtB

it DeviceAddress

R/W=0

R/WBit

Register/Port

Address

Data from

Master to

TPS2384

Sto

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it

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DeviceAddress

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Bit

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it

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it

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Bit

Ack

Bit

Ack

Bit

Ack

Bit

Ack

Bit

Ack

Bit

Ack

Bit

START/STOP SEQUENCE

STOP

CONDITION(P)

START

CONDITION(S)

SDA_O

SDA_I


The high-to-low transition of SDA_I while SCL is high defines the start condition. The low to high transition ofSDA_I while SCL is high defines the stop condition. The master device initiates all start and stop conditions.

The first serial packet is enclosed within start and stop bits, consists of a 7-bit address field, read/write bit, andthe acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field.Five of the seven address bits are used by the TPS2384. The value of the sixth and seventh bit is ignored andnot used by the TPS2384.

The address field of the TPS2384 is 8 bits long and contains 5 bits of device address select and a read/write bitas and two spare bits per Table 1. The leading two bits are not used and are reserved for future port expansion.The five device address select bits follow this plan. These bits are compared against the hard-wired state of thecorresponding device address select pins (A1–A5). When the field contents are equivalent to the pin logicstates, the device is addressed. These bits are followed by LSB bit, which is used to set the read or writecondition (1 for read and 0 for write). Following a start condition and an address field, the TPS2384 respondswith an acknowledge by pulling the SDA_O line low during the 9th clock cycle if the address field is equivalent tothe value programmed by the pins. The SDA_O line remains a stable low while the 9th clock pulse is high.

Figure 16. I2C Read/Write Cycles




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Chip Addressing

Port/Register Cycle

Data Write Cycle

Data Read Cycle


Table 1 shows the bit assignments during the addressing cycle.

Table 1. Address Selection Field

BIT FUNCTION

A7 Future expansion (value not compared)

A6 Future expansion (value not compared)

A5 Device address. Compared with pin A5




A1 Device address LSB. Compared with pin A1

A0 Read/Write

After the chip address cycle, the TPS2384 accepts eight bits of port/register select data as defined in Table 2.The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internalregister for the follow-on data read or write operation. After latching the eight-bit data field, the TPS2384 pullsthe SDA_O line low for one clock cycle, for the acknowledge pulse.

For a data write sequence, after the Port/Register address cycle, the TPS2384 accepts the eight bits of data asdefined in the tables below. The data is latched into the previously selectedWrite Register, and the TPS2384generates a data acknowledge pulse by pulling the SDA_O line low for one clock cycle. Common registerfunctions act on all ports simultaneously. Per port registers are specific to the target port only.

To reset the interface, the host or master subsequently generates a stop bit by releasing the SDA_I line duringthe clock-high portion of an SCL pulse.

For a data read sequence, after the register acknowledge bit, themaster device generates a stop condition. Thisis followed by a second start condition, and retransmitting the device address as described in chip addressabove. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2384 againresponds with an acknowledge pulse. The address acknowledge is then followed by sequentially presentingeach of the eight data bits on the SDA_O line (MSB first), to be read by the host device on the rising edges ofSCL. After eight bits are transmitted, the host acknowledges by pulling the SDA_I line high for one clock pulse.The completed data transfer is terminated with the host generating a stop condition.




www.ti.comTPS2384


Table 2. Register/Port Addressing Map

BIT FUNCTION STATE PRESETSTATE

D7 Unused 0 0

D6 Register select MSB 0000 = Common Read — Port fault status, chip ID and rev.0001 = Common Control Write — Software reset, ports disable and AC Disc.D5 Register select Bit 20010 = Port Control Write 1 — Function calls; misc. fault disables

D4 Register select Bit 1 0011 = Port Control Write 2 — Port enable; A/D control0100 = Port Status Read 1 — Fault status; device Class info.0101 = Port Status Read 2 — Function and other status0110 = Discovery Current – Lower Bits — A/D resistance results0111 = Discovery Current – Upper Bits — A/D resistance results 00001000 = Voltage – Lower Bits – A/D voltage results1001 = Voltage – Upper Bits — A/D voltage results

D3 Register select LSB 1010 = Current – Lower Bits — A/D current results1011 = Current – Upper Bits — A/D current results1100 = Temperature – Lower Bits — A/D temperature results1101 = Temperature – Upper Bits — A/D temperature results1110 = unused1111 = Common Write – Test mode selections — timer disables, discovery control, etc.

D2 Unused 0 0

D1 Port address MSB 00 = port 101 = port 2 0010 = port 3D0 Port address LSB11 = port 4

Table 3. Common Read, Register Select = 0000


Port 4 general 0 = no faultD7 0Fault status 1 = port fault (1) (2)

Port 3 general 0 = no faultD6 0Fault status 1 = port fault(1) (2)



D3 00 = rev --01 = rev 1Chip rev Varies10 = rev 2D211 = rev 3

D1 00 = TPS2384101= future useChip ID 1010 = TPS2384D011 = reserved

(1) PMM faults cleared by Disable function.(2) AM faults cleared by TED timer.





Table 4. Common Write, Register Select = 1111 (Test Register) (1)


D7 Unused 0 0

0 = normal operationD6 Thermal shutdown test 01 = force TSD condition (all ports off)

0 = normal POR timingD5 POR disable 01 = force POR to a non-reset state

0 = normal (4-ms Discovery 1 and Discovery 2)D4 Discovery timers 01 = timers disable

0 = normal operationD3 Discovery 1 and 2 01 = all 4-port Discovery 1 and Discovery 2 – halt

0 = DC Disconnect timer between 300 ms to 400 ms for loads less than 5 mA (IEEED2 DC Disconnect timer standard) 0

1 = DC Disconnect timer 0 ms for loads less than 5 mA

0 = normal operationD1 TED timer 01 = 750-ms TED timer disable

D0 Unused 0 0

(1) Test mode select; not intended for end--application use.

Table 5. Common Control Write, Register Select = 0001


D7 Unused 0 0

D6 Unused 0 0

0 = activeD5 Thermal shutdown fault (1) 01 = disable

0 = offD4 A high 01 = AC_HI driver on

0 = offD3 AC low 01 = AC_LO driver on

0 = activeD2 Port over/under voltage faults 01 = disable

0 = normal operationD1 All ports disable (2) 01 = all ports shut down (no ramp)

0 = normal operationD0 Software RESET 01 = reset all circuits and start a POR timing cycle

(1) Register 0001, bit D5 operation inhibited after device probe.(2) Consult factory for Alternative B, semi-auto mode implementations which write to bit D1.




www.ti.comTPS2384


Table 6. Port Control Write 1, Register Select = 0010 (One Per Port)


D7 Unused 0 0

D6 Unused 0 0

0 = normal operationD5 Discovery fault disable 01 = disable internal discovery fault limits (19 kΩ to 29.5 kΩ)

0 = DC Disconnect activeD4 DC Disconnect disable 01 = DC Disconnect disable (for AC Disconnect)

D3 Function Bit 3 0000 = Disable function (power down and reset all functions)0001 = Discovery 1 functionD2 Function Bit 20010 = Discovery 2 function

D1 Function Bit 1 0011 = port voltage sample function (V sample)0100 = legacy detection function0101 = classification function0110 = ramp up/power function (rup pwr)0111 = continuous sample function (C sample) 00001000 = ramp power down function (Rdwn)1001 = ac low

D0 Function Bit 0 1010 = ac high1011 = port current sample function (I sample)1100 = die temperature sample function (T sample)1101 = spare1110 = spare1111 = spare

Table 7. Port Control Write 2, Register Select = 0011 (One Per Port)


D7 Unused 0 0

D6 Unused 0 0

D5 Unused 0 0

0 = normalD4 Port Enable (1) 01 = port disable

0 = normalD3 A/D Start 01 = start A/D (self clearing)

0 = normalD2 A/D Abort 01 = abort

D1 Unused 0 0

D0 Unused 0 0

(1) Consult factory for Alternative B, semi-auto mode implementations which write to bit D4.





Table 8. Port Status Read 1, Register Select = 0100 (One Per Port)


0 = normalD7 Discovery Status 01 = discovery fail

0 = normalD6 Function Done Bit 01 = function complete (self clearing by a new function write)

D5 Port Class 000 = class 0001 = class 1D4 Port Class010 = class 2 000011 = class 3D3 Port Class100 = class 4

D2 Fault status (MSB) 000 = no faults001 = UV/OV faultD1 Fault status010 = thermal shutdown fault (TSD)011 = overload current > 50-ms fault 000100 = load disconnect

D0 Fault status (LSB) 101 = reserved for future110 = reserved for future111 = reserved for future

Table 9. Port Status Read 2, Register Select = 0101 (One Per Port)


D7 Unused 0 0

D6 Unused 0 0

D5 Unused 0 0

0 = not activeD4 Watch dog timer 01 = active

0 = not activeD3 A/D status 01 = active (conversion in process)

D2 Function status (MSB) 000 = disabled001 = searchingD1 Function status010 = power delivery011 = fault 000100 = test

D0 Function status (LSB) 101 = other fault110 = undefined111 = undefined




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A/D Results Registers (Discovery Current, Voltage, Current and Temperature)


Table 10. Discovery Current — Lower Bits, Register Select = 0110 (One Per Port)


D7 A/D bit 7 A/D lower bits 0

D6 A/D bit 6

D5 A/D bit 5

D4 A/D bit 4

D3 A/D bit 3

D2 A/D bit 2

D1 A/D bit 1

D0 A/D bit 0

Table 11. Discovery Current — Upper Bits, Register Select = 0111 (One Per Port)


D7 Resistor measurement 0 = measurement active (bit set low at the start of Discovery 1 or Discovery 2) 0complete 1 = measurement complete (bit set high after A/D is completed during Discovery 1 or

Discovery 2)

D6 A/D bit 14 A/D upper bits 0

D5 A/D bit 13

D4 A/D bit 12

D3 A/D bit 11

D2 A/D bit 10

D1 A/D bit 9

D0 A/D bit 8

Table 12. Voltage — Lower Bits, Register Select = 1000 (One Per Port)



D6 A/D bit 6

D5 A/D bit 5

D4 A/D bit 4

D3 A/D bit 3

D2 A/D bit 2

D1 A/D bit 1

D0 A/D bit 0





Table 13. Voltage — Upper Bits, Register Select = 1001 (One Per Port)


D7 Voltage measurement 0 = measurement active (bit set low when A/D begins a voltage measurement) 0complete 1 = measurement complete (bit set high after A/D has completed a voltage

measurement)


D5 A/D bit 13

D4 A/D bit 12

D3 A/D bit 11

D2 A/D bit 10

D1 A/D bit 9

D0 A/D bit 8

Table 14. Current — Lower Bits, Register Select = 1010 (One Per Port)



D6 A/D bit 6

D5 A/D bit 5

D4 A/D bit 4

D3 A/D bit 3

D2 A/D bit 2

D1 A/D bit 1

D0 A/D bit 0

Table 15. Current — Upper Bits, Register Select = 1011 (One Per Port)


D7 Current measurement 0 = measurement active (bit set low when A/D begins a current measurement) 0complete 1 = measurement complete (bit set high after A/D has completed a current

measurement)


D5 A/D bit 13

D4 A/D bit 12

D3 A/D bit 11

D2 A/D bit 10

D1 A/D bit 9

D0 A/D bit 8




www.ti.comTPS2384


Table 16. Temperature — Lower Bits, Register Select = 1100 (One Per Port)



D6 A/D bit 6

D5 A/D bit 5

D4 A/D bit 4

D3 A/D bit 3

D2 A/D bit 2

D1 A/D bit 1

D0 A/D bit 0

Table 17. Temperature — Upper Bits, Register Select = 1101 (One Per Port)


D7 Temperature 0 = measurement active (bit set low when A/D begins a temperature measurement) 0measurement complete 1 = measurement complete (bit set high after A/D has completed a temperature

measurement)


D5 A/D bit 13

D4 A/D bit 12

D3 A/D bit 11

D2 A/D bit 10

D1 A/D bit 9

D0 A/D bit 8




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TPS2384 AC DRIVE APPLICATION SCHEMATIC

AC_HI and LOW w/o External FET Configurations


Figure 17.




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TPS2384 System Block Diagram


TPS2384 AC DRIVE APPLICATION SCHEMATIC (continued)

NOTE: A fuse may be required to provide additional protection if isolation is lost or the low-side current sense fails.

Figure 18.




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TPS2384 Basic 4 PORT (PMM) Isolated Configuration with AC Disconnect

64 62

1

2

3

4

5

6

7

8

9

10

11

12

17 18 19 20

13

14

15

16

21 22 23 24 25 26 27 28 29 30 31 32

61

48

34

33

PO

RB

V10

AG

2

V2.5

RG

Rbia

s

Ct

SY

N

AG

1

V48

P1

N1

RET1

CINT1

P2

N2

RET2CINT

2

P4

N4

CINT4

P3

N3

RET3

CINT3

MS

RET4V

3

DG

SC

L

SD

A_I

SD

A_O

A2

A3

A4

A5

A1

V6.3

ALT

A/B

WD

_D

IS

TPS2384

Quad PSEController

INT

AC

_LO

AC

_H

I

63 60 58 5759 56 54 5355 52 50 4951

47

46

45

44

43

42

41

40

39

38

37

35

36

RJ45-5

Xfo

rmer

0.1

uF

0.1

uF

0.1

uF

124K

220pF

0.027uF

0.027uF

220nF

0.1uF48V BUS

POS NEG

RJ45-5

Xfo

rmer

220nF RJ45-5

Xfo

rmer

RJ45-5

Xfo

rmer

7.5K

7.5K

7.5K

7.5K

68uF

0.027uF

0.027uF

220nF

270

270V

DDCPU

GND CPU

SDA_IN

POR

9.1K

270

SDA_OU

T

INT

SCL

3.9K

3.9K

3.9K

9.1K3.9K

3.9K

0.1

uF

+-

0.5W

0.5W

Open Drain

Open Drain

Open Drain

220nF

AutoFunction


TPS2384 AC DRIVE APPLICATION SCHEMATIC (continued)

TPS2384 basic 4-port isolated configuration with AC Disconnect (PAP pinout shown).

Figure 19.




PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

TPS2384PAP ACTIVE HTQFP PAP 64 160 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PAP

TPS2384PAPG4 ACTIVE HTQFP PAP 64 160 Green (RoHS& no Sb/Br)


TPS2384PAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS& no Sb/Br)


TPS2384PAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS& no Sb/Br)


TPS2384PJD ACTIVE HTQFP PJD 64 160 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PJD

TPS2384PJDG4 ACTIVE HTQFP PJD 64 160 Green (RoHS& no Sb/Br)


TPS2384PJDR ACTIVE HTQFP PJD 64 1000 Green (RoHS& no Sb/Br)


TPS2384PJDRG4 ACTIVE HTQFP PJD 64 1000 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

http://www.ti.com/product/TPS2384?CMP=conv-poasamples#samplebuy








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PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS2384PAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2

TPS2384PJDR HTQFP PJD 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2384PAPR HTQFP PAP 64 1000 367.0 367.0 45.0

TPS2384PJDR HTQFP PJD 64 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

Pack Materials-Page 2

http://www.ti.com/lit/slma002

http://www.ti.com/lit/slma004

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.

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RFID www.ti-rfid.com

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Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2013, Texas Instruments Incorporated

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