Topic 10 Pipe Lining 11

8/6/2019 Topic 10 Pipe Lining 11

http://slidepdf.com/reader/full/topic-10-pipe-lining-11 1/26

Pipeliningin

Digital Systems



Revision of Timing parameters

definition units

delay

clock period T

clock frequency

time from point→ point

rising edge→rising edge

of clock

1

clock period

ns

ns

MHz

latency

throughput

time from input→

output

#output bits/time unit

ns

Mbits/s



Latency

D Q

clk

D Q

clk

Combinational

Logic

Combinational

LogicCombinational

Logic

Combinational

Logic D Q

clk

top-level entity

Latency is the time between input(n) and output(n) i.e. time it takes from first input to first output, second input to second output, etc. Latency is usually constant for a system (but not always) Also called input-to-output latency

Count the number of rising edges of the clock! In this example, 3 rising edges from input to output latency is 3 cycles

Latency is measured in clock cycles (then translated to seconds)

In this example, say clock period is 10 ns, then latency is 30 ns

input output

clk

input input(0) input(1) input(2)

output (unknown) output(0) output(1

8 bits 8 bits

100 MHz



Throughput

D Q

clk

D Q

clk

Combinational

Logic

Combinational

LogicCombinational

Logic

Combinational

Logic D Q

clk

top-level entity

Throughput = (bits per output sample) / (time between consecutive output samples)

Bits per output sample:

In this example, 8 bits per output sample

Time between consecutive output samples: clock cycles between output(n) to output(n+1)

Can be measured in clock cycles, then translated to time

In this example, time between consecutive output samples = 1 clock cycle = 10 ns

Throughput = (8 bits per output sample) / (10 ns) = 0.8 bits / ns = 800 Mbits/s

input output

clk

input input(0) input(1) input(2)

output (unknown) output(0) output(1

8 bits

8 bits

1 cycle betweeeoutput sample



Pipelining—Conceptual

Assuming tCLK2Q

= tS= 0 ns, the critical path is 10 ns, and the

maximum clock frequency is 100 MHz Latency = 2 cycles

D Q

clk

D Q

clk

Combinational

Logic

Combinational

Logic

tLOGIC = 10 ns



Pipelining—Conceptual

Purpose of pipelining is to reduce the critical path of the circuit by inserting anadditional register (called a pipeline register) This splits the combinational logic in half

Now critical path delay is 5 ns, so maximum clock frequency is 200 MHz

Double the clock frequency

However, latency increases to 3 cycles (and area is increased due to additionalregister)

In general, pipelining increases throughput at the cost of increased latency and area/power

D Q

clk

D Q

clk

Combinational

Logic A

Combinational

Logic A

tLOGICA = 5 ns

Combinational

Logic

Combinational

Logic

Combinational

Logic A

Combinational

Logic A

D Q

clk

register splits logic in half

tLOGICB = 5 ns



Pipelining



Pipelining a Function of Unit



Pipelining



Pipelining a function unit



Pipelining in Microprocessors

Key strategy for improving the performance of systems

Provide a form of parallelism (Pipeline parallelism)

Different parts of different computations are being processed at

the same time

In general, blocks A, B, C, … will be different

Although in some applications

eg pipelined multiplier, digital filter, image processing

applications, … some (or all) of them may be identical

Register

A

Register

Register

C

Clock

B

A, B, C – combinatorial blocks



Pipelines

Any modern high performance processor provides an example of a pipelined

system ‘Work’ of processing an instruction is broken up into several sub-tasks, eg

IF - Instruction fetch

ID/OF - Instruction decode and operand fetch

Ex - Execute

WB - Write back

Register

IF

Register

Register

Ex

Clock

ID

OFWB

Instructn

memory

Register

File

Part of a simple pipelined RISC processor



Advanced pipelining :Multipliers - Pipelined

Pipelining will

throughput (results produced per second)

but also

total latency (time to produce full result)

· · · · · ·· · · · · ·

· · · · · ·· · · · · ·

· · · · · ·· · · · · ·· · · · · ·

· · · · · ·

· · · · · · · · · · · ·

Insert registers to

capture partial sums

Benefits

*Simple

*Regular *Register width can vary

-Need to capture operands also!

*Usual pipeline advantages

Inserting a register at every stage may not

produce a benefit!



Multipliers

We can add the partial products with FA blocks

b0

b1

a0a1a2a3

FAFAFAFA

FA

0

FAFAFA

p0p1

b2

FAFAFAFA

product bits

Note that an extra adder is needed

below the last row to add the last

partial products and the carries

from the row above!Carry select adder



Advanced pipelining

Ripple-Carry adder (n=4)



Advanced pipelining

Pipelined Ripple-Carry adder (n=4)



Advanced pipelining



Advanced pipelining 2

Topic 10 Pipe Lining 11

Documents

Transcript of Topic 10 Pipe Lining 11