TMS320C6713 DSK Technical Reference

TMS320C6713 DSK

2003 DSP Development Systems

ReferenceTechnical

TMS320C6713 DSK Technical Reference

506735-0001 Rev. A May 2003

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

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WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2003 Spectrum Digital, Inc.

Contents

1 Introduction to the TMS320C6713 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C6713 DSK Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320C6713 DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.4 DC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.5 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.6 MISC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 Flash ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 LEDs and DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320C6713 DSK and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.6.1 J201, USB Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.2 J8, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.7 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.8 Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the TMS320C6713 DSKB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the TMS320C6713 DSK

About This Manual

This document describes the board level operations of the TMS320C6713 DSPStarter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6713 Digital Signal Processor.

The TMS320C6713 DSK is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320C6713 DSP to determineif the processor meets the designers application requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The TMS320C6713 DSK will sometimes be referred to as the DSK.

Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320C67xx DSP CPU Reference GuideTexas Instruments TMS320C67xx DSP Peripherals Reference Guide

Table 1: Manual History

Revision History

A Alpha Release

1-1

Chapter 1

Introduction to the TMS320C6713 DSK

Chapter One provides a description of the TMS320C6713 DSK alongwith the key features and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-6

Spectrum Digital, Inc

1-2 TMS320C6713 DSK Module Technical Reference

1.1 Key Features

The C6713 DSK is a low-cost standalone development platform that enables users toevaluate and develop applications for the TI C67xx DSP family. The DSK also servesas a hardware reference design for the TMS320C6713 DSP. Schematics, logicequations and application notes are available to ease hardware development andreduce time to market.

The DSK comes with a full compliment of on-board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments TMS320C6713 DSP operating at 225 MHz.

• An AIC23 stereo codec

• 8 Mbytes of synchronous DRAM

• 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration)

• 4 user accessible LEDs and DIP switches

• Software board configuration through registers implemented in CPLD

• Configurable boot options

• Standard expansion connectors for daughter card use

• JTAG emulation through on-board JTAG emulator with USB host interface or external emulator

• Single voltage power supply (+5V)

Figure 1-1, Block Diagram C6713 DSK

Ext.JTAG

AIC23Codec

Hos

t Por

t Int

MUX

MUX

MIC

IN

LIN

E O

UT

HP

OU

T

LIN

E IN

Peripheral Exp

LED DIP

EMIF

HPI

McBSPs

JTAG

0 1 2 30 1 2 3

CPL

D

Memory Exp

PWR

USB

EmbeddedJTAG

JP1 1.26V

JP2 3.3V

END

IAN

BOO

TM 1

BOO

TM 0

6713DSP

SDR

AM

328

Flas

h

8

1 32

ConfigSW3

32

HPI

_EN

4

VoltageReg

JP4

5V


1-3

1.2 Functional Overview of the TMS320C6713 DSK

The DSP on the 6713 DSK interfaces to on-board peripherals through a 32-bit wideEMIF (External Memory InterFace). The SDRAM, Flash and CPLD are all connectedto the bus. EMIF signals are also connected daughter card expansion connectorswhich are used for third party add-in boards.

The DSP interfaces to analog audio signals through an on-board AIC23 codec and four3.5 mm audio jacks (microphone input, line input, line output, and headphone output).The codec can select the microphone or the line input as the active input. The analogoutput is driven to both the line out (fixed gain) and headphone (adjustable gain)connectors. McBSP0 is used to send commands to the codec control interface whileMcBSP1 is used for digital audio data. McBSP0 and McBSP1 can be re-routed to theexpansion connectors in software.

A programmable logic device called a CPLD is used to implement glue logic that tiesthe board components together. The CPLD has a register based user interface thatlets the user configure the board by reading and writing to its registers.

The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide theuser with interactive feedback. Both are accessed by reading and writing to the CPLDregisters.

An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. Theboard is held in reset until these supplies are within operating specifications.

Code Composer communicates with the DSK through an embedded JTAG emulatorwith a USB host interface. The DSK can also be used with an external emulatorthrough the external JTAG connector.



1.3 Basic Operation

The DSK is designed to work with TI’s Code Composer Studio developmentenvironment and ships with a version specifically tailored to work with the board.Code Composer communicates with the board through the on-board JTAG emulator.To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation anddrivers.

After the install is complete, follow these steps to run Code Composer. The DSK mustbe fully connected to launch the DSK version of Code Composer.

1) Connect the included power supply to the DSK.

2) Connect the DSK to your PC with a standard USB cable (also included).

3) Launch Code Composer from its icon on your desktop.

Detailed information about the DSK including a tutorial, examples and referencematerial is available in the DSK’s help file. You can access the help file through CodeComposer’s help menu. It can also be launched directly by double-clicking on the filec6713dsk.hlp in Code Composer’s docs\hlp subdirectory.


1-5

1.4 Memory Map

The C67xx family of DSPs has a large byte addressable address space. Program codeand data can be placed anywhere in the unified address space. Addresses are always32-bits wide.

The memory map shows the address space of a generic 6713 processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of the internal memorycan be reconfigured in software as L2 cache rather than fixed RAM.

The EMIF has 4 separate addressable regions called chip enable spaces (CE0-CE3). The SDRAM occupies CE0 while the Flash and CPLD share CE1. CE2 and CE3 aregenerally reserved for daughtercards.

Figure 1-2, Memory Map, C6713 DSK

Internal Memory

Reserved Spaceor

Peripheral Regs

AddressC67x Family

Memory Type

SDRAM

CPLDFlash

DaughterCard

6713 DSK

InternalMemory

Reservedor

Peripheral

EMIF CE0

EMIF CE3

EMIF CE2

EMIF CE1

0x80000000

0x90000000

0xA0000000

0xB0000000

0x00000000

0x00030000

0x90080000



1.5 Configuration Switch Settings

The DSK has 4 configuration switches that allows users to control the operational stateof the DSP when it is released from reset. The configuration switch block is labeledSW3 on the DSK board, next to the reset switch.

Configuration switch 1 controls the endianness of the DSP while switches 2 and 3configure the boot mode that will be used when the DSP starts executing. Configuration switch 4 controls the on-chip multiplexing of HPI and McASP signalsbrought out to the HPI expansion connector. By default all switches are off whichcorresponds to EMIF boot (out of 8-bit Flash) in little endian mode and HPI signals onthe HPI expansion connector.

1.6 Power Supply

The DSK operates from a single +5V external power supply connected to the mainpower input (J5). Internally, the +5V input is converted into +1.26V and +3.3V usingseparate voltage regulators. The +1.26V supply is used for the DSP core while the+3.3V supply is used for the DSP's I/O buffers and all other chips on the board. Thepower connector is a 2.5mm barrel-type plug.

There are three power test points on the DSK at JP1, JP2 and JP4. All I/O currentpasses through JP2 while all core current passes through JP1. All system currentpasses through JP4. Normally these jumpers are closed. To measure the currentpassing through remove the jumpers and connect the pins with a current measuringdevice such as a multimeter or current probe.

It is possible to provide the daughter card with +12V and -12V when the external powerconnector (J6) is used.

Table 1: Configuration Switch Settings

Switch 1 Switch 2 Switch 3 Switch 4 Configuration Description

Off Little endian (default)

On Big endian

Off Off EMIF boot from 8-bit Flash (default)

Off On HPI/Emulation boot

On Off 32-bit EMIF boot

On On 16-bit EMIF boot

Off HPI enabled on HPI pins (default)

On McASP1 enabled on HPI pins

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe TMS320C6713 DSK.

Topic Page

2.1 CPLD (Programmable Logic) 2-22.1.1 CPLD Overview 2-22.1.2 CPLD Registers 2-32.1.3 USER_REG Register 2-32.1.4 DC_REG Register 2-42.1.5 Version Register 2-42.1.6 MISC Register 2-52.2 AIC23 Codec 2-62.3 Sychronous DRAM 2-72.4 Flash Memory 2-72.5 LEDs and DIP Switches 2-72.6 Daughter Card Interface 2-8



2.1 CPLD (Programmable Logic)

The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable LogicDevice (CPLD) device to implement:

• 4 Memory-mapped control/status registers that allow software control of various board features.

• Control of the daughter card interface and signals.

• Assorted "glue" logic that ties the board components together.

2.1.1 CPLD Overview

The CPLD logic is used to implement functionality specific to the DSK. Your ownhardware designs will likely implement a completely different set of functions or takeadvantage of the DSPs high level of integration for system design and avoid the use of external logic completely.

The CPLD implements simple random logic functions that eliminate the need foradditional discrete devices. In particular, the CPLD aggregates the various resetsignals coming from the reset button and power supervisors and generates a globalreset.

The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industrystandard VHDL (Hardware Design Language) and included with the DSK.


2-3

2.1.2 CPLD Registers

The 4 CPLD memory-mapped registers allows users to control CPLD functions insoftware. On the 6713 DSK the registers are primarily used to access the LEDs andDIP switches and control the daughter card interface. The registers are mapped intoEMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with asimple asynchronous memory interface. The following table gives a high leveloverview of the CPLD registers and their bit fields:

The table below shows the bit definitions for the 4 registers in CPLD.

2.1.3 USER_REG Register

USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on oroff to allow the user to interact with the DSK. The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.

Table 1: CPLD Register Definitions

Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 USER_REG USR_SW3R

USR_SW2R

USR_SW1R

USR_SW0R

USR_LED3R/W

0(Off)

USR_LED2R/W

0(Off)

USR_LED1R/W

0(Off)

USR_LED0R/W

0(Off)

1 DC_REG DC_DETR

0 DC_STAT1R

DC_STAT0R

DC_RSTR

0(No reset)

0 DC_CNTL1R/W

0(low)

DC_CNTL0R/W

0(low)

4 VERSION CPLD_VER[3.0]R

0 BOARD VERSION[2.0]R

6 MISC SCR_5R/W

0

SCR_4R/W

0

SCR_3R/W

0

SCR_2R/W

0

SCR_1R/W

0

FLASH_PAGER/W

0(Flash A19=0)

McBSP1ON/OFFBoardR/W

0(Onboard)

McBSP0ON/OFFBoardR/W

0(Onboard)

Table 2: CPLD USER_REG Register

Bit Name R/W Description

7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)




3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)






2.1.4 DC_REG Register

DC_REG is used to monitor and control the daughter card interface. DC_DET detectsthe presence of a daughter card. DC_STAT and DC_CNTL provide simplecommunications with the daughter card through readable status lines and writablecontrol lines.

The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.

2.1.5 VERSION Register

The VERSION register contains two read only fields that indicate the BOARD andCPLD versions. This register will allow your software to differentiate betweenproduction releases of the DSK and account for any variances. This register is notexpected to change often, if at all.

Table 3: DC_REG Register


7 DC_DET R Daughter Card Detect (1= Board detected)

6 0 R Always zero

5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)

4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)

3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)

2 0 R Always zero

1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)

0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)

Table 4: Version Register Bit Definitions

Bit # Name R/W Description

7 CPLD_VER3 R Most Significant CPLD Version Bit

6 CPLD_VER2 R CPLD Version Bit

5 CPLD_VER1 R CPLD Version Bit

4 CPLD_VER0 R Least Significant CPLD Version Bit

3 0 R Always zero

2 DSK_VER2 R Most Significant DSK Board Version Bit

1 DSK_VER1 R DSK Board Version Bit

0 DSK_VER0 R Least Significant DSK Board Version Bit


2-5

2.1.6 MISC Register

The MISC register is used to provide software control for miscellaneous boardfunctions. On the 6713 DSK, the MISC register controls how auxiliary signals arebrought out to the daughter-card connectors.

McBSP0 and McBSP1 are usually used as the control and data ports of the on-boardAIC23 codec. The power-on state of these bits (both 0s) represents that situation. Set the corresponding McBSP select bit to use the McBSP with a daughter cardinstead.

The Flash and CPLD share CE1 which means that the highest DSP address bit (A21)is used to differentiate between the two. The FLASH_PAGE bit is driven to the Flash asa replacement for that address line which is connected to A19 of the Flash. On astandard DSK, the on-board Flash is not large enough for this bit to be significant.FLASH_PAGE is only useful if the board is re-populated with a larger pin-compatibleFlash chip.

The scratch bits are unused. They can be set to any value.

Table 5: MISC Register


7 SCRATCH_5 R/W Scratch bit 5





2 FLASH_PAGE R/W Flash address bit 19

1 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)

0 MCBSP0SEL R/W McBSP0 on/off board (0 = on-board, 1 = off-board)



2.2 AIC23 Codec

The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for inputand output of audio signals. The codec samples analog signals on the microphone orline inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples backinto analog signals on the line and headphone outputs so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internalconfiguration registers and one to send and receive digital audio samples. McBSP0 isused as the unidirectional control channel. It should be programmed to send a 16-bitcontrol word to the AIC23 in SPI format. The top 7 bits of the control word shouldspecify the register to be modified and the lower 9 should contain the register value. The control channel is only used when configuring the codec, it is generally idle whenaudio data is being transmitted,

McBSP1 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The DSK examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side. Thepreferred serial format is DSP mode which is designed specifically to operate with theMcBSP ports on TI DSPs.

The codec has a 12MHz system clock. The 12MHz system clock corresponds to USBsample rate mode, named because many USB systems use a 12MHz clock and canuse the same clock for both the codec and USB controller. The internal sample rategenerate subdivides the 12MHz clock to generate common frequencies such as48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATEregister. The figure below shows the codec interface on the C6713 DSK.

Figure 2-1, TMS320C6713 DSK CODEC INTERFACE

MIC IN

LINE IN

LINE OUT

HP OUT

ADC

DAC

McBSP1

DSP Format

0 LEFTINVOL1 RIGHTINVOL2 LEFTHPVOL3 RIGHTHPVOL4 ANAPATH5 DIGPATH6 POWERDOWN7 DIGIF8 SAMPLERATE9 DIGACT

15 RESET

Con

trol R

egis

ters

LRCINBCLK

DIN

DOUTLRCOUTFSX2

DX2

CLKXFSR2

CLKR

DR2

CSSCLKSDIN

McBSP0

SPI Format

FSX1

TX1CLKX1

AIC23 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT


2-7

2.3 Synchronous DRAM

The DSK uses a 64 megabit synchronous DRAM (SDRAM) on the 32-bit EMIF. The SDRAM is mapped at the beginning of CE0 (address 0x80000000). Total availablememory is 8 megabytes. The integrated SDRAM controller is part of the EMIF and mustbe configured in software for proper operation. The EMIF clock is derived from the PLLsettings and should be configured in software at 90MHz. This number is based on aninternal PLL clock of 450MHz required to achieve 225 MHz operation with a divisor of2 and a 90MHz EMIF clock with a divisor of 5.

When using SDRAM, the controller must be set up to refresh one row of the memoryarray every 15.6 microseconds to maintain data integrity. With a 90MHz EMIF clock,this period is 1400 bus cycles.

2.4 Flash Memory

Flash is a type of memory which does not lose its contents when the power is turnedoff. When read it looks like a simple asynchronous read-only memory (ROM). Flashcan be erased in large blocks commonly referred to as sectors or pages. Once a blockhas been erased each word can be programmed once through a special commandsequence. After than the entire block must be erased again to change the contents.

The DSK uses a 512Kbyte external Flash as a boot option. It is visible at the beginningof CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to supportthe DSK's 16-bit boot option. However, the software that ships with the DSK treats theFlash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit bootmode. In this configuration, only 256Kbytes are readily usable without softwarechanges.

2.5 LEDs and DIP Switches

The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) thatprovide the user a simple form of input/output. Both are accessed through the CPLDUSER_REG register.



2.6 Daughter Card Interface

The DSK provides three expansion connectors that can be used to accept plug-indaughter cards. The daughter card allows users to build on their DSK platform toextend its capabilities and provide customer and application specific I/O. Theexpansion connectors are for memory, peripherals, and the Host Port Interface (HPI)

The memory connector provides access to the DSP’s asynchronous EMIF signals tointerface with memories and memory mapped devices. It supports byte addressing on32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals likeMcBSPs, timers, and clocks. Both connectors provide power and ground to thedaughter card

The HPI is a high speed interface that can be used to allow multiple DSPs tocommunicate and cooperate on a given task. The HPI connector brings out the HPIspecific control signals.

Most of the expansion connector signals are buffered so that the daughter card cannotdirectly influence the operation of the DSK board. The use of TI low voltage, 5V tolerantbuffers, and CBT interface devices allows the use of either +5V or +3.3V devices to beused on the daughter card.

Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET andDC_DET exist and are accessible through the CPLD DC_REG register. The DSKalso multiplexes the McBSP0 and McBSP1 of on-board or external use. This functionis controlled through the CPLD MISC register.

3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the TMS320C6713 DSKand its connectors.

Topic Page

3.1 Board Layout 3-23.2 Connector Index 3-33.3 Expansion Connectors 3-33.3.1 J4, Memory Expansion Connector 3-43.3.2 J3, Peripheral Expansion Connector 3-53.3.3 J1, HPI Expansion Connector 3-63.4 Audio Connectors 3-73.4.1 J301, Microphone Connector 3-73.4.2 J303, Audio Line In Connector 3-73.4.3 J304, Audio Line Out Connector 3-83.4.4 J302, Headphone Connector 3-83.5 Power Connectors 3-93.5.1 J5, +5 Volt Connector 3-93.5.2 J6, Optional Power Connector 3-93.6 Miscellaneous Connectors 3-103.6.1 J201, USB Connector 3-103.6.2 J8, External JTAG Connector 3-103.6.3 JP3, PLD Programming Connector 3-113.7 System LEDs 3-113.8 Reset Switch 3-11


3-2 TMS320VC6713 DSK Module Technical Reference

3.1 Board Layout

The C6713 DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which ispowered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6713 DSK.

Figure 3-1, TMS320C6713 DSK

J4

J5J6 JP3

J302

J8SW1 SW2J201 D7-10

J304J303J301 J3 J1


3-3

3.2 Connector Index

The TMS320C6713 DSK has many connectors which provide the user accessto the various signals on the DSK.

Note: “*” Not populated

3.3 Expansion Connectors

The TMS320C6713 DSK supports three expansion connectors that follow the TexasInstruments interconnection guidelines. The expansion connector pinouts aredescribed in the following three sections.

The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profileconnectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectorsare designed for high speed interconnections because they have low propagationdelay, capacitance, and cross talk. The connectors present a small foot print on theDSK. Each connector includes multiple ground, +5V, and +3.3V power signals so thatthe daughter card can obtain power directly from the DSK. The peripheral expansionconnector additionally provides both +12V and -12V to the daughter card. Therecommended mating connector, whose part number is TFM-140-32-S-D-LC, is asurface mount connector that provides a 0.465” mated height.

Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin

Table 1: TMS320C6713 DSK Connectors

Connector # Pins Function

J4 80 Memory

J3 80 Peripheral

J1 80 HPI

J301 3 Microphone

J303 3 Line In

J304 3 Line Out

J303 3 Headphone

J5 2 +5 Volt

J6 * 4 Optional Power Connector

J8 14 External JTAG

J201 5 USB Port

JP3 10 CPLD Programming

SW3 8 DSP Configuration Jumper



3.3.1 J4, Memory Expansion Connector

Table 2: J4, Memory Expansion Connector

Pin Signal I/O Description Pin Signal I/O Description

1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin

3 AEA21 O EMIF address pin 21 4 AEA20 O EMIF address pin 20




11 GND Vss System ground 12 GND Vss System ground








27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2

29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0


33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30




41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
















73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable

75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready

77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2



3-5

3.3.2 J3, Peripheral Expansion Connector

Table 3: J3, Peripheral Expansion Connector


1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin





11 N/C - No connect 12 N/C - No connect




19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin

21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source

23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data


27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect

29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data


33 CLKX1 I/O McBSP1 transmit clock 34 CLKS1 I McBSP1 clock source

35 FSX1 I/O McBSP1 transmit frame sync 36 DX1 O McBSP1 transmit data


39 CLKR1 I/O McBSP1 receive clock 40 N/C - No connect

41 FSR1 I/O McBSP1 receive frame sync 42 DR1 I McBSP1 receive data


45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input

47 N/C - No connect 48 EXT_INT5 I External interrupt 5

49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input


53 EXT_INT4 I External interrupt 4 54 N/C - No connect



59 RESET O System reset 60 N/C - No connect


63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control

65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status

67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7

69 ACE3# O Chip enable 3 70 N/C - No connect



75 DC_DET# Vss System ground 76 GND Vss System ground

77 GND Vss System ground 78 ECL KOUT O EMIF Clock




3.3.3 J1, HPI Expansion Connector

Table 4: J1, HPI Expansion Connector



3 GND Vss System ground 4 HPI_RESETn I HPI reset input

5 CLKOUT3 O Clock output3 6 N/C - No connect


9 HD1/AXR1[7] I/O HPI data 1 10 N/C - No connect

11 HD3/AMUTE1 I/O HPI data 3 12 HD0/AXR1[4] I/O HPI data 0

13 HD5/AHCLKX1 I/O HPI data 5 14 HD2/AFSX1 I/O HPI data 2

15 HD7/GP0[3] I/O HPI data 7 16 HD4/GP0[0] I/O HPI data 4

17 GND Vss System ground 18 HD6/AHCLKR1 I/O HPI data 6

19 HD8/GP0[8] I/O HPI data 8 20 GND Vss System ground




27 GND Vss System ground 28 HD15/GP0[15] I/O HPI data 15

29 HDS2z/AXR1[5] I/O Host data strobe 2 30 GND Vss System ground

31 GND Vss System ground 32 HASz/ACLKX1 I/O Host address strobe

33 HDS1z/AXR1[6] I/O Host data strobe 1 34 GND Vss System ground

35 GND Vss System ground 36 HCNTL0/AXR1[3] I/O Host control 1

37 HCSz/AXR1[2] I/O Host chip select 38 GND Vss System ground

39 GND Vss System ground 40 HHWIL/AFSR1 I/O Host half-word select

41 HCNTL1/AXR1[1] I/O Host control 1 42 GND Vss System ground

43 GND Vss System ground 44 HINTz/GP0[1] I/O Host interrupt

45 HRDYZ/ACLKR1 I/O Host Ready 46 GND Vss System ground

47 GND Vss System ground 48 N/C - No connect

49 HR/Wz/AXR1[0] I/O Host R/W strobe 50 N/C - No connect



55 N/C - No connect 56 GND Vss System ground






67 N/C - No connect 68 SCL0 I/O I2C0 Clock


71 GND Vss System ground 72 SDA0 I/O I2C0 Data




79 GND Vss System ground 80 CLKOUT2/GP0[2] I/O GP I/O 0 bit 2


3-7

3.4 Audio Connectors

The C6713 DSK has 4 audio connectors. They are described in the followingsections.

3.4.1 J301, Microphone Connector

The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it ismonaural. The signals on the plug are shown in the figure below.

3.4.2 J303, Audio Line In Connector

The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.

Microphone In

Ground

Figure 3-2, Microphone Stereo Jack

Microphone Bias

Left Line In

Ground

Figure 3-3, Audio Line In Stereo Jack

Right Line In



3.4.3 J304, Audio Line Out Connector

The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.

3.4.4 J303, Headphone Connector

Connector J4 is a headphone/speaker jack. It can drive standard headphones or a highimpedance speaker directly. The standard 3.5 mm jack is shown in the figure below.

Left Line Out

Ground

Figure 3-4, Audio Line Out Stereo Jack

Right Line Out

Left Headphone

Ground

Figure 3-5, Headphone Jack

Right Headphone


3-9

3.5 Power Connectors

The C6713 DSK has 2 power connectors. They are described in the followingsections.

3.5.1 J5, +5 Volt Connector

Power (+5 volts) is brought onto the TMS320C6713 DSK via the J5 connector. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. TheA diagram of J5 is shown below.

3.5.2 J6, Optional Power Connector

Connector J6 is an optional power connector. It will operate with the standard personalcomputer power supply. To populate this connector use a Molex #15-24-4041. Thetable below shows the voltages on the respective pins.

Table 5: J6, Optional Power Connector

Pin # Voltage Level

1 +12 Volts

2 -12 Volts

3 Ground

4 +5 Volts

PC Board

J5+5V

Ground

Front ViewFigure 3-6, TMS320C6713 DSK Power Connector

WARNING !Do not plug into J5 and J6 at the same time.



3.6 Miscellaneous Connectors

The C6713 DSK has 3 additional connectors to aid the user in developing with thisproduct. They are described in the following sections.

3.6.1 J201, USB Connector

Connector J201 provides a Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the DSK. This allows for code development and debugwithout the use of an external emulator. The signals on this connector are shown in thebelow.

3.6.2 J8, External JTAG Connector

The TMS320C6713 DSK is supplied with a 14 pin header interface, J8. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.The pinout for the connector is shown in the figure below.

Table 6: J201, USB Connector

Pin # USB Signal Name

1 USBVdd

2 D+

3 D-

4 USB Vss

5 Shield

6 Shield

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 3-7, J8, JTAG INTERFACE


3-11

3.6.3 JP3, PLD Programming Connector

This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for theprogramming of the CPLD. This connector is not intended to be used outside thefactory.

3.7 System LEDs

TheTMS320C6713 DSK has four system light emitting diodes (LEDs). TheseLEDs indicate various conditions on the DSK. These function of each LED is shown inthe table below.

3.8 Reset Switch

There are three resets on the TMS320C6713 DSK. The first reset is the power onreset. This circuit waits until power is within the specified range before releasing thepower on reset pin to the TMS320C6713.

External sources which control the reset are push button SW2, and the on boardembedded USB JTAG emulator.

Table 7: System LEDs

Reference Designator Color Function On Signal

State

D4 Green USB Emulation in use. When External JTAG Emulator is used this LED is off.

1

D3 Green +5 Volt present 1

D6 Orange RESET Active 1

DS201 Green USB Active, Blinks during USB data transfer 1

A-1

Appendix A

Schematics

This appendix contains the schematics for the TMS320C6713 DSK.Board components with designators over 200 (e.g. DS201, R211) are partof Spectrum Digital’s embedded JTAG emulator and are not included inthese schematics.


A-2 TMS320C6713 DSK Module Technical Reference

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B 9 D3

B 10

C11

B12

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2

G2 F 2 A7 B 7 A6 B 6 Y11

D10

Y 12

E MU

0EM

U1

EMU

2EM

U3

EMU

4EM

U5

TDO

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XR0_

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CLK

IN

CLK

MO

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PLLH

V

RES

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NM

I

GP7

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GP6

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INT6

GP5

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1 133 4 7 8 11

2 5 6 9 10

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24 121 5 16 1 9 20 23

1OE

2OE

1A1

1 A2

1 A3

1A4

1A5

1B1

1 B2

1 B3

1B4

1B5

2A1

2 A2

2A3

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D

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5067

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Tues

day,

Apr

il 29

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3

Title

Size

Doc

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t Num

ber

Rev

Dat

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of

T EA1

1

T D23

T D22

TEA1

5

TEA5

TEA1

2

T D26

TD21

T D20

TD11

TD9

TD7

T D4

T BE

2n

T EA3

T D31

T D28

TD27

TEA4

T D29

T D18

TD3

TEA8

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T D5

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3n

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6

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TD13

TD5

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TD15

T D8

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TD6

T D12

T D14

T D0

TEA2

TEA3

T EA4

T EA5

TEA6

TEA7

T EA8

TEA9

TEA1

0TE

A11

T EA1

2TE

A13

T EA1

4T E

A15

T EA1

6TE

A17

T EA1

8

T EA2

0TE

A19

EA21

EA20

EA19

EA18

EA17

EA16

EA15

EA14

EA13

EA12

EA11

EA10

EA9

EA8

EA7

EA6

EA5

EA4

E A3

EA2

ED0ED1ED2ED3ED4ED5ED6ED7ED8ED9ED10ED11ED12ED13ED14ED15ED16ED17ED18ED19ED20ED21ED22ED23ED24ED25ED26ED27ED28ED29ED30ED31

TEA2

1TE

A20

TEA1

9TE

A18

TEA1

7TE

A16

TEA1

5TE

A14

TEA1

3TE

A12

TEA1

1TE

A10

TEA9

TEA8

TEA7

TEA6

TEA5

TEA4

T EA3

TEA2

TD0TD1TD2TD3TD4TD5TD6TD7TD8TD9TD10

TD19

TD17

TD14

TD16

TD12

TD18

TD13

TD11

TD15

TD25

TD22

TD29

TD23

TD20

TD24

TD21

TD28TD27TD26

TD31TD30

TCE

0n

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DR

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RN

8B33

RN

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RN

8C33

RN

12H

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RN

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RN9

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RN7

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RN6H 33

RN4B 33

RN5F 33RN5E 33RN5D 33

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C95

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RN3A 33

RN3G 33

RN5C 33

RN4D 33

RN6A 33

RN3D 33

RN6C 33

RN

8F33

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RN4A 33RN5H 33

RN6E 33

RN3E 33

RN6D 33

RN4G 33

RN4C 33

RN4F 33

RN3F 33

RN4H 33

RN4E 33

RN5G 33

RN6B 33

RN3H 33

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RN

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2 4 66 6 5 64 63 62 6 1 60 2 7 26 2 523 22 6 8 672071 1 6 1 9 18 1 759 28 8 6 7 2 5 8 4 4 8 4 7 8 52 4 6 38 3 2 12 6

4 3 2 9 1 5 1 8 1 7 5 55 4 9 41 3 5 9 3

2 1 7 0 697 3 5 7 3 0 14

DQ

0D

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17

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A 9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1

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CKE

CS

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M1

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V SS

VSS

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V SSQ

VSSQ

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VSSQ

V SSQ

VSSQ

V SSQ

V DD

V DD

VDD

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V DDQ

VDDQ

VDDQ

VDDQ

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VDDQ

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NC

NC

NC

NC

NC

NC

RN

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U18Y1

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EA21

EA20

EA19

EA18

EA17

EA16

EA15

EA14

EA13

EA12

EA11

EA10

E A9

EA8

EA7

EA6

E A5

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EA3

EA2

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HO

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10

R48

33

R47

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A M29

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10 1 3 14

1 61 81920212 2232 42 53 7 4 627

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1 529 3 1 33 35 38 4 0 42 4 4 30 3 2 34 36 39 41 4 3 4 51 7

A 14

A15

A 16

A13

A12

A11

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6D

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DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

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A17

RN

9H33

R59

10K

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12E

33



MC

BSP

5067

32A

TMS3

20C6

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B

513

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

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of

DR

1

DX1

F SX1

F SR

1

CLK

R1

CLK

X1

DCI

SO-4

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CLK

S1

CLK

S0

CLK

R0

DR

0

FSR

0

F SX0

DX0

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DC

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0

DC

_CLK

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DC

_CLK

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DC

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DC

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DC

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A IC

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0

SCL0

SDA0

DC

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TL_C

LKX0

DC

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CTL

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DC

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DG

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DG

ND

DG

ND

DG

ND

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R27

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G3

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R0

CLK

R0/

ACLK

R0

CLK

X0/A

CLK

X0

DR0

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0_0

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FSR

0/AF

SR0

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CLK

S/SC

L1C

LKR

1/AX

R0_6

CLK

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MU

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1/SD

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X1AX

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1 A

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1 B2

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D

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DEV

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CO

NFIG

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ION

5067

32A

TMS3

20C6

713

DSK

B

613

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

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of

HD

1H

D3

HD

5H

D7

HD

12H

D14

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S1n

HC

NTL

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HR

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3 53 6

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4 34 4

4546

4748

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6364

6566

6768

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2526

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3940

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4748

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5152

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6364

6566

6768

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7778

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U10

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B 14

C14

A15

C15

A16

B 16

C16

B 17

A 18

C17

B 18

C19

C20

D18

D20

E 20

H19

F18

E 19

F20

E18

G20

H20

G18

G19

J20

HD

15/G

P15

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14/G

P14

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13/G

P13

HD

12/G

P12

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11/G

P11

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10/G

P10

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9/G

P9H

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GP8

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7/G

P3H

D6/

AHC

LKR

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DIR

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ION

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L

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H

A

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H

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ISO

LATI

ON

DA

UG

HTE

RC

AR

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UFF

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GD

C_E

MIF

A_D

IR =

1 FO

R W

RITE

S

5067

32B

TMS3

20C6

713

DSK

B

713

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

TEA1

2

DC

_D30

DC

_D16

DC

_D26

DC

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DC

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DC

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T EA8

DC

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DC

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DC

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T D17

DC

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TEA3

T D11

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DC_

A2T E

A2

T EA2

0

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DC

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DC

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DC

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DC

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DC

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DC

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DC

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DC_

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DC

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TEA9

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DC

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DC_

A7

DC

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DC_

A6

TEA1

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TEA5

DC

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DC

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DC

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T EA7

T D9

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DC

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DC

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DC

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DC

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TD6

TD7

TD14

T D12

TD10 TD

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20

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TD28

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DC

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DC

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DC

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E#D

C_A

OE#

DC

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E#

DC

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#

DC

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#

DC

_CN

TL_O

E#

DC_

EMIF

A_DI

R

DC

_EM

IFA_

OE#

DG

ND

3.3V

DG

ND

3 .3V

DG

ND

3.3V

3 .3V

3 .3V

3 .3V 3 .

3V

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

3 .3V

DG

ND

3 .3V

3.3V

U16

SN74

LVTH

1624

5A

7 18314 2 47 4 6 44 4 3 41 4 0 38 3 7

2 3 5 6 8 9 11 1 236 35 33 3 2 30 29 27 2 6

13 14 16 1 7 19 20 22 2 3

48 1 25 24 4 10 15 21

28 34 39 45

V cc

Vcc

Vcc

V cc

1A1

1 A2

1A3

1 A4

1 A5

1A6

1A7

1A8

1B1

1 B2

1B3

1 B4

1 B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2 A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2 B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R40

31K

U6

SN74

LVTH

1624

5A

7 18314 2 47 4 6 44 4 3 41 4 0 38 3 7

2 3 5 6 8 9 11 1 236 35 33 3 2 30 29 27 2 6

13 14 16 1 7 19 20 22 2 3

48 1 25 24 4 10 15 21

28 34 39 45

V cc

Vcc

Vcc

V cc

1A1

1 A2

1A3

1 A4

1 A5

1A6

1A7

1A8

1B1

1 B2

1B3

1 B4

1 B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2 A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2 B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R15

33

C15

0.1

C17

0.1

C16

0.1

C14

0.1

U17

S N74

LVTH

1624

5A

7 1 83 142 47 4 6 44 43 41 4 0 38 3 7

2 3 5 6 8 9 11 1 236 3 5 33 32 30 29 2 7 2 6

13 1 4 16 17 19 20 2 2 2 3

4 8 1 25 2 4 4 10 1 5 2 1

2 8 34 3 9 4 5

V cc

Vcc

Vcc

V cc

1 A1

1A2

1A3

1A4

1A5

1 A6

1 A7

1A8

1 B1

1B2

1B3

1B4

1B5

1 B6

1 B7

1B8

2 A1

2A2

2A3

2A4

2 A5

2A6

2 A7

2A8

2 B1

2B2

2B3

2B4

2 B5

2B6

2 B7

2B8

1OE

1 DIR

2OE

2 DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R14

1K

C20

0 .1

R13

10K

C19

0 .1

C21

0 .1

C18

0 .1

U5

S N74

LVTH

1624

5A

7 1 83 14 2 4 7 46 44 43 4 1 40 3 8 37

2 3 5 6 8 9 1 1 123 6 35 33 32 30 2 9 2 7 2 6

1 3 14 16 17 19 2 0 2 2 2 3

4 8 1 2 5 24 4 1 0 1 5 2 1

28 3 4 3 9 4 5

Vcc

V cc

V cc

Vcc

1A1

1A2

1A3

1A4

1 A5

1 A6

1A7

1 A8

1B1

1B2

1B3

1B4

1 B5

1 B6

1B7

1 B8

2A1

2A2

2A3

2 A4

2A5

2 A6

2A7

2 A8

2B1

2B2

2B3

2 B4

2B5

2 B6

2B7

2 B8

1 OE

1DIR

2 OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

C96

0 .1

C94

0 .1

C11

5

0 .1

C11

6

0 .1

C11

7

0.1

C99

0.1

C98

0.1

C11

8

0.1


A-9

DA

UG

HTE

RCA

RD

I/F

Exte

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Mem

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Inte

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Per

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5067

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day,

Apr

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, 200

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Title

Size

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Rev

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of

DC

_D27

DC

_D11

DC

_D19

DC

_D9

DC_

A2

DC

_A18

DC

_A12

DC

_D5

DC

_D17

DC

_A14

DC

_A10

DC

_A17

DC

_D15

DC

_A19

DC

_D3

DC

_A21

DC

_D7

DC_

A6

DC

_A16

DC

_D13

DC

_A13

DC_

A3

DC

_D21

DC_

A9

DC

_D29

DC

_D23

DC_

A4D

C_A5

DC

_A15

DC

_D1

DC_

A7

DC

_A11

DC

_A20

DC

_D25

DC_

A8

DC

_D20

DC

_D4

DC

_D31

DC

_D18

DC

_D22

DC

_D14

DC

_D2

DC

_D30

DC

_D6

DC

_D24

DC

_D26

DC

_D28

DC

_D16

DC

_D10

DC

_D0

DC

_D12

DC

_D8

DC

_DR

0

DC

_CLK

S0

DC

_EIN

T7

DC

_CLK

X0

DC

_CLK

R1

DC

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1..2

]

DC

_CN

TL0

DC

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#

DC

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E#D

C_C

E2#

DC

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#

DC

_CLK

X1

DC

_TO

UT0

DC

_FSR

1

DC

_CN

TL1

DC

_TO

UT1

DC

_RS

T#

DC

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T4

DC

_AW

E#

DC

_DR

1

DC

_BE1

#

DC

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1

DC

_EIN

T5

DC

_EC

LKO

UT

DC

_FSR

0

DC

_TIN

P0

DC

_AR

DY

DC

_CLK

S1

DC

_DX0

DC

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0

DC

_CE3

#

DC

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T6

DC

_CLK

R0

DC

_D[3

1..0

]

DC

_TIN

P1

DC

_AR

E#

DC

_DX1

DC

_BE2

#

DC

_DET

DC

_STA

T1D

C_S

TAT0

DG

ND

DG

ND

DG

ND

DG

ND

- 12V

1 2V

3.3V

5V

3.3V

5V

3.3V

3.3V

5V5V

3.3V

3.3V

R16

4.7K

R2

0

R65

10K

J4

CO

NN

ECTO

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0 X

212

34

56

78

91 0

1 11 2

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1 51 6

1 71 8

1920

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2324

2 52 6

2728

2 93 0

3 13 2

3 33 4

3536

3 73 8

3940

4 14 2

4 34 4

4 54 6

4 74 8

4 95 0

5 15 2

5 35 4

5556

5 75 8

5960

6 16 2

6364

6 56 6

6768

6 97 0

7172

7 37 4

7576

7778

7980

12

34

56

78

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1112

1 31 4

1516

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2324

2 52 6

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2930

3132

3 33 4

3 53 6

3 73 8

3 94 0

4 14 2

4 34 4

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4748

4 95 0

5152

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5556

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5960

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6566

6768

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7374

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7778

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1920

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2324

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2728

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3 33 4

3536

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3940

4 14 2

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4 54 6

4 74 8

4 95 0

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5 35 4

5556

5 75 8

5960

6 16 2

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34

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3.3

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5067

32B

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913

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

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t Num

ber

Rev

Dat

e:Sh

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of

SEN

SE_D

SP_C

VDD

SVS_

RST

#

DSP

IO_3

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DSP

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D

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AGND

3.3V

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DG

ND

DSP

IO_3

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DSP

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D

DG

ND

DG

ND

5 V

U7

T PS5

4310

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1 2 3 4 5 6 7 8 9 1 01 11 21314151 61 7181 92021

AGND

V SEN

SEC

OM

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DB O

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P H2

PH3

P H4

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1 2 3 4 5 6 7 8 9 1 01 112131 4151 61 7181 9202 1

AGND

V SEN

SEC

OM

PP W

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DB O

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PH1

PH2

PH3

PH4

PH5

PGN

D1

PGN

D2

PGN

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V BIA

SSS

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AS Y

NC

RT

POW

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D

TP32

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P

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107

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3 .74

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1 00u

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R38 10

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T16

4 7uF

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7 1.5

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TP1

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1 80

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MU

RS1

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MU

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D14

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RS1

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D16

MU

RS1

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A-11

DSP

PO

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& D

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All

capa

cito

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is s

heet

are

dec

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capa

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. The

y sh

ould

be

plac

ed a

s cl

ose

as p

ossi

ble

to th

e D

SP.

5067

32A

TMS3

20C6

713

DSK

B

1013

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

DSP

IO_3

.3V

DSP

_CVD

D

DG

ND

DG

ND

DG

ND

DS P

IO_3

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DSP

IO_3

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DS P

_CVD

D

DSP

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D

DG

ND

DG

ND

DG

ND

DG

ND

C77

0 .1

C79

0 .1

C51

0.1

C26

0.1

C31

0.1

U1 0

G

TMS3

20C

6713

GD

P

A4 A 9 A10 B 2 B19

C3

C7

C18 D

5D

6D

11D

14D

15 F4 F17 K 1 K4 K 17 L4 L 17

L20

R4

R1 7 U

6U

10U

11U

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15 V 3 V18

W2

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CVD

DC

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DC

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CVD

DC

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CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CV D

DC

VDD

CV D

DC

VDD

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DC

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DC

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CV D

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VDD

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DC

VDD

CVD

DC

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DC

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CVD

DC

VDD

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DC

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C41

0.1

C52

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10K

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1

C11

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1

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H

TMS3

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6713

GD

P

A17 B 3 B8 B 13

C1 0 D

1D

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19 F 3 H18 J2

M18 R

1R

18 T3 U5

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7

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DVD

DD

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DVD

DD

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DVD

DD

VDD

DVD

DD

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DVD

DD

VDD

DVD

DD

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DV D

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DV D

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DV D

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DVD

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DVD

D

DVD

DD

VDD

C78

0.1

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40.

1

U1 0

I

TMS3

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6713

GD

P

A1 A 2 A11

A 14

A19

A 20 B1 B4 B 15

B 20

C6

C8

C9

D4

D8

D13

D1 7 E 2 E4 E 1

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1 7 H4

H17 J 4 J 9 J 1

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2 K 2 K9 K 10

K11

K 12

K 20 L 9 L10

L 11

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M4

M9

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M11

M12

M17 N

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P19

T 4 T17

U4

U8

U9

U13

U17

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W1

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W16

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Y1 Y 2 Y13

Y 19

Y20

VSS

V SS

V SS

VSS

VSS

V SS

V SS

V SS

VSS

V SS

V SS

VSS

VSS

VSS

VSS

V SS

V SS

VSS

V SS

VSS

VSS

VSS

V SS

VSS

V SS

VSS

V SS

VSS

V SS

VSS

V SS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

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VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

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VSS

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VSS

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C10

30.

1

C25

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C62

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C10

90.

1

C32

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C10

80.

1C

105

0.1

C30

0.1

C58

0.1

C46

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C50

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C90

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C34

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C35

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C10

10.

1

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T6 10C

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1+

CT8 10

C48

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C56

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110

C85

0.1

C10

60.

1

C11

20.

1

U10

J

TMS3

20C

6713

GD

P

A 5 B5 C12 D

7D

12 A12

B 11

RSV

RSV

RSV

RSV

RSV

RSV

RSV

C33

0.1

C54

0.1

C47

0.1

C81

0.1

C27

0.1

C23

0.1

C10

00.

1

C83

0.1

C59

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0.1



J TAG

MUL

TIPL

EXER

S

EMU

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DSP

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NGTH

.

LOC

ACTE

R-P

ACK

NEA

R D

SP

USB

IN U

SE

5067

32A

TMS3

20C6

713

DSK

B

1113

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

X DS_

TRST

#T_

TMS

XDS_

EMU

1

X DS_

TDO

X DS_

TMS

XDS_

EMU

0

XDS_

TVD

XDS_

TDI

T_EM

U1

X DS_

4.1V

T_EM

U0

HU

RR

ICAN

E_D

ETn

HU

R_E

MU

3H

UR

_EM

U2

HU

R_E

MU

5H

UR

_EM

U4

HU

R_E

MU

1H

UR

_EM

U0

MU

X_EM

U0

MU

X_EM

U1

HU

R_T

CK

HU

R_T

CKR

TN

T_TR

STn

T_TC

K

HU

RR

ICAN

E_D

ETn

XDS_

TCKR

ET

XDS_

TCK

T_TC

K_R

ET

T _TD

O

T _TD

I

DSP

_TD

O

DSP

_TD

I

DSP

_TM

S

T_E

MU

0

T_E

MU

1

DSP

_EM

U2

DS P

_EM

U3

DSP

_EM

U5

DSP

_EM

U4

T_TC

K_R

ET

DSP

_EM

U0

DSP

_EM

U1 D

SP_T

CK

DSP

_TR

ST#

T _T M

S

T_TC

K

T_TR

STn

X DS_

4.1V

T_TD

O

T _TD

I

DG

ND

3 .3V

DG

ND

DG

ND

DG

ND

3 .3V

DG

ND

5V

DG

ND

DG

ND3.

3V

DG

ND

3 .3V

DG

ND

DG

ND

DG

ND

3 .3V

3.3V

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

DG

ND

3.3V

RN

2C42

RN

2D42

U24

SN74

LVC

1G32

1 24

5 3

R96

33

R92

33

R93

1.6K

D5 LM

4040

DCI

M3-

4.1

21

RN

2B4 2

RN2

A42

C12

2.1

uF

R10

033

R89

150

U26 SN

74LV

C1G

321 2

4

5 3

R95

100

1%

C12

6

22pF

J8

HEA

DER

7x2

, Em

ulat

ion

1 3 5 7 9

2 4 8 101 1

1 213

14

R67

4 7K

R90

47K

C12

4.1

uF

U19

S N74

CBT

3257

PW

4

1 4

71 1

9 1 21 3 12 151 03 5 6

1 6 8

1 A

4B1

2 A3 B

13 A 4 A

4 B2

S1 B1

OE

3 B2

1 B2

2 B1

2 B2

V CC

GN

D

U25

SN74

CBT

3257

PW

4

14

711

9 1213 12 15103 5 6

1 6 8

1A

4B1

2A3B

13A 4A

4B2

S1 B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

J7 HEA

DER

4x1

5

A 1 A2 A 3 A4 A 5 A6 A7 A8 A9 A 10

A 11

A 12

A 13

A 14

A15

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

B14

C14B1

3C

13 B 12

C12B 1

1C

11B 10

C10B 9C

9 B 7C7B6C6B 5C5 B4C4B3 C3B 2C2 B 1B 15

C1

C15 B 8C

8

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DT Y

PE0

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DT Y

PE1

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

E MU

0E M

U1

EMU

2E M

U3

TCLK

EMU

4E M

U5

EMU

6E M

U7

EMU

8E M

U9

EMU

10

T DO

E MU

11EM

U12

EMU

13EM

U14

E MU

15

T DI

EMU

16E M

U17

T RST

nT M

S

E MU

18

ID0

I D1

I D2

I D3

T VD

TCKR

TN

D4

LTS

T-C

150G

KT

R9 4

30.1

K

R88

1K

C12

3

0 .1

U23

SN74

LVC

1G32

1 24

5 3

U22

SN74

AHC

1G14

3

4

5

2

U18 S N

74AH

C1G

14

3

4

5

2

RN

2H42

RN

2G42

RN

2F4 2

RN

2E4 2

R91

1K

C12

5

0 .1


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Hier

arch

aric

al B

lock

s

5067

32A

TMS3

20C6

713

DSK

B

1213

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

USB

/Em

ulat

ion

USB

/Em

ulat

ion

5V

USB

_DSP

_RST

#

T_TD

O

T_TC

KT_

TMS

T_TR

STn

T_E

MU

0T_

EM

U1

T_TD

I

3.3V

PON

RSn

GN

D

T_TC

K_R

ET

CLK

_12M

HZ

CLK

_24M

HZ

AIC

23 A

udio

AIC

23 A

udio

GN

D

DAT

A_BC

LKD

ATA_

SYN

CIN

DAT

A_DI

ND

ATA_

DO

UT

CTL

_DAT

AC

TL_C

LKC

TL_C

S

CO

DEC

_SYS

CLK

AIC

3.3V

DAT

A_SY

NC

OU

T

CLK

_12M

HZ

USB

_DSP

_RST

#

T_TD

IT_

TMS

T_TC

K

T_E

MU

0T_

EM

U1

T_TD

OSV

S_R

ST#

T_TR

STn

T_TC

K_R

ETC

TL_C

LKX0

CTL

_FSX

0

CTL

_DX0

BCLK

AIC

23SD

ATAO

UT

LRC

OU

T

AIC

23SD

ATAI

NLR

CIN

CO

DEC

_CLK

5V

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

U11

SN74

LVC

1G32

1 24

5 3

C67

.1uF

R32

33



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Con

trol P

ort

AU

DIO

5067

32A

TMS3

20C

6713

DSK

B

1313

Tues

day,

Apr

il 29

, 200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

LLIN

E_O

UT

RLI

NE_

OU

T

AIC

23LR

CIN

AIC

23CS

SPIM

OD

E

3.3V

A

3.3V

A

AIC

3.3V

AIC

3.3V

AIC

3.3V

AIC

3.3V

AIC

3.3V

+

C32

510

uF

C32

60.

1uF+

C31

910

uF

C32

20.

1uF

R32

52.

2K

R32

8N

O P

OP

R32

64.

7K

R33

74.

7K

R33

44.

7K

R33

64.

7K

R33

54.

7K

C34

1

0.1u

F

+C32

3220

uF

+ C32

4220

uF

L306

BLM

21P2

21SN

C34

0N

O P

OP

C34

4N

O P

OP

C34

5N

O P

OP

R34

30

C32

1

47pF

+

C31

5

1uF

L307

BLM

21P2

21SN

C33

9N

O P

OP

C33

847

0nF

J302

Hea

d Ph

one

Out

3 4 2 1

C34

2

0.1u

F

R33

247

KC

333

470n

F

C33

447

0nF

R33

347

KJ3

03

Line

In

3 4 2 1

R34

533

C33

20.

1uF

J301

Mic

roph

one

In

3 4 2 1

+C

343

10uF

C33

747

0nF

R31

20

C33

6N

O P

OP

L305

BLM

21P2

21SN

C32

9N

O P

OP

+

C33

110

uF

J304

Line

Out

3 4 2 1

R34

1 47K

R34

2 47K

R33

910

0

R33

80

L304

BLM

21P2

21SN

C33

0N

O P

OP

C33

5N

O P

OP

RN

314

10K

1 2 3 45678

RN

316

33

1 2 3 45678

R34

010

0

PW P

acka

geU

307 TL

V320

AIC2

3

22141115 25

34 5 212423

10 9 28

16 17 18 20 19

26 13 12

8

167

2 27

MO

DE

AVdd

HPG

ND

AGND

XTI/M

CLK

BCLK

DIN

LRCI

N

CS

SCLK

SDIN

RH

POU

TLH

PO

UT

DG

ND

VMID

MIC

_BIA

SM

IC_I

NLL

INE_

INR

LIN

E_IN

XTO

RLI

NE_

OU

TLL

INE_

OU

T

HPV

dd

BVdd

DO

UT

LRC

OU

T

CLK

OU

T

DVd

d

L308

BLM

21P2

21SN

L303

BLM

21P2

21SN

C31

8N

O P

OP

R34

42.

2

L301

HZ0

805E

601R

R32

70

C32

0N

O P

OP

L309

BLM

21P2

21SN

C31

7N

O P

OP

C31

6N

O P

OP

C32

7N

O P

OP

R33

10

+C

347

10uF

+C

346

10uFL3

02BL

M21

P221

SN

C32

8N

O P

OP

RN

315

10K

1 2 3 45678

CTL

_CLK

CTL

_CS

CTL

_DAT

A

DAT

A_DI

ND

ATA_

SYN

CIN

DAT

A_BC

LKD

ATA_

DO

UT

DAT

A_SY

NC

OU

T

CO

DEC

_SYS

CLK

AIC

3.3V

GN

D

B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about theTMS320C6713 DSK produced by Spectrum Digital.


B-2 TMS320C6713 DSK Module Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE

Printed in U.S.A., May 2003506735-0001 Rev. A

TMS320C6713 DSK Technical Reference

Documents

Transcript of TMS320C6713 DSK Technical Reference