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TMS320C6416 DSK

2003 DSP Development Systems

ReferenceTechnical

TMS320C6416 DSK Technical Reference

505945-0001 Rev. B November 2003

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2003 Spectrum Digital, Inc.

Contents

1 Introduction to the TMS320C6416 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C6416 DSK Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320C6416 DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.4 DC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.5 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.6 MISC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 Flash ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 LEDs and DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320C6416 DSK and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.6.1 J201, USB Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.2 J8, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.7 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.8 Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the TMS320C6416 DSKB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the TMS320C6416 DSK

About This Manual

This document describes the board level operations of the TMS320C6416 DSPStarter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6416 Digital Signal Processor.

The TMS320C6416 DSK is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320C6416 DSP to determineif the processor meets the designers application requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The TMS320C6416 DSK will sometimes be referred to as the DSK.

Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320C64xx DSP CPU Reference GuideTexas Instruments TMS320C64xx DSP Peripherals Reference Guide

Table 1: Manual History

Revision History

A Production Release

B Updates for 720 Mhz. Support

1-1

Chapter 1

Introduction to the TMS320C6416 DSK

Chapter One provides a description of the TMS320C6416 DSK alongwith the key features and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-6

Spectrum Digital, Inc

1-2 TMS320C6416 DSK Module Technical Reference

1.1 Key Features

The C6416 DSK is a low-cost standalone development platform that enables users toevaluate and develop applications for the TI C64xx DSP family. The DSK also servesas a hardware reference design for the TMS320C6416 DSP. Schematics, logicequations and application notes are available to ease hardware development andreduce time to market.

The DSK comes with a full compliment of on-board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments TMS320C6416 DSP operating at 600 or 720 MHz.

• An AIC23 stereo codec

• 16 Mbytes of synchronous DRAM

• 512 Kbytes of non-volatile Flash memory

• 4 user accessible LEDs and DIP switches

• Software board configuration through registers implemented in CPLD

• Configurable boot options and clock input selection

• Standard expansion connectors for daughter card use

• JTAG emulation through on-board JTAG emulator with USB host interface or external emulator

• Single voltage power supply (+5V)

Figure 1-1, Block Diagram C6416 DSK

Ext.JTAG

AIC23Codec

Host

Por

t Int

MUX

MUX

MIC

IN

LIN

E O

UT

HP

OU

T

LIN

E IN

Peripheral Exp

LED DIP

EMIFA

HPI

McBSPs

JTAG

0 1 2 30 1 2 3

CPLD

Memory Exp

VoltageReg

PWR

USB

EmbeddedJTAG

JP1 1.4V

JP2 3.3V

END

IAN

BOO

TM 1

BOO

TM 0

6416DSP SD

RAM

648

Flas

h

8

EMIFB

1 32

ConfigSW 3

32

JP45V

PLL_

SELE

CT

4


1-3

1.2 Functional Overview of the TMS320C6416 DSK

The DSP on the 6416 DSK interfaces to on-board peripherals through one of twobusses, the 64-bit wide EMIFA and the 8-bit wide EMIFB. The SDRAM, Flash andCPLD are each connected to one of the busses. EMIFA is also connected to thedaughtercard expansion connectors which is used for third party add-in boards.

An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP1 is used for the codec control interface and McBSP2 is used for data. AnalogI/O is done through four 3.5mm audio jacks that correspond to microphone input, lineinput, line output and headphone output. The codec can select the microphone or theline input as the active input. The analog output is driven to both the line out (fixedgain) and headphone (adjustable gain) connectors. McBSP1 and McBSP2 can be re-routed to the expansion connectors in software.

A programmable logic device called a CPLD is used to implement glue logic that tiesthe board components together. The CPLD also has a register based user interfacethat lets the user configure the board by reading and writing to the CPLD registers.

The DSK includes 4 LEDs and 4 position DIP switch as a simple way to provide theuser with interactive feedback. Both are accessed by reading and writing to the CPLDregisters.

An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the 1.4V DSP core voltage and 3.3V I/O supplies. Theboard is held in reset until these supplies are within operating specifications. Aseparate regulator powers the 3.3V lines on the expansion interface.

Code Composer communicates with the DSK through an embedded JTAG emulatorwith a USB host interface. The DSK can also be used with an external emulatorthrough the external JTAG connector.



1.3 Basic Operation

The DSK is designed to work with TI’s Code Composer Studio developmentenvironment and ships with a version specifically tailored to work with the board.Code Composer communicates with the board through the on-board JTAG emulator.To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation anddrivers.

After the install is complete, follow these steps to run Code Composer. The DSK mustbe fully connected to launch the DSK version of Code Composer.

1) Connect the included power supply to the DSK.

2) Connect the DSK to your PC with a standard USB cable (also included).

3) Launch Code Composer from its icon on your desktop.

Detailed information about the DSK including a tutorial, examples and referencematerial is available in the DSK’s help file. You can access the help file through CodeComposer’s help menu. It can also be launched directly by double-clicking on the filec6416dsk.hlp in Code Composer’s docs\hlp subdirectory.


1-5

1.4 Memory Map

The C64xx family of DSPs has a large byte addressable address space. Program codeand data can be placed anywhere in the unified address space. Addresses are always32-bits wide.

The memory map shows the address space of a generic 6416 processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.

Each EMIF (External Memory Interface) has 4 separate addressable regions calledchip enable spaces (CE0-CE3). The SDRAM occupies CE0 of EMIFA while the CPLDand Flash are mapped to CE0 and CE1 of EMIFB respectively. Daughtercards useCE2 and CE3 of EMIFA.

Figure 1-2, Memory Map, C6416 DSK

Internal Memory

Reserved Spaceor

Peripheral Regs

EMIFB CE0

EMIFB CE3

EMIFB CE2

EMIFB CE1

AddressGeneric 6416

Address Space

0x60000000

0x64000000

0x68000000

0x6C000000

SDRAM

CPLD

Flash

DaughterCard

6416 DSK

InternalMemory

Reservedor

Peripheral

EMIFA CE0

EMIFA CE3

EMIFA CE2

EMIFA CE1

0x80000000

0x90000000

0xA0000000

0xB0000000

0x00000000

0x00100000



1.5 Configuration Switch Settings

The DSK has 3 configuration switches that allows users to control the operational stateof the DSP when it is released from reset. The configuration switch block is labeledSW3 on the DSK board, next to the reset switch.

Configuration switch 1 controls the endianness of the DSP while switches 2 and 3configure the boot mode that will be used when the DSP starts executing. By default allswitches are off which corresponds to EMIFB boot (out of 8-bit Flash) in little endianmode. The figure below shows these settings.

1.6 Power Supply

The DSK operates from a single +5V external power supply connected to the mainpower input (J5). Internally, the +5V input is converted into +1.4V and +3.3V using adual voltage regulator. The +1.4V supply is used for the DSP core while the +3.3Vsupply is used for the DSP's I/O buffers and all other chips on the board. The powerconnector is a 2.5mm barrel-type plug.

There are three power test points on the DSK at JP1, JP2 and JP4. All 6416 I/Ocurrent passes through JP2 while all core current passes through JP1. All systemcurrent passes through JP4. Normally these jumpers are closed. To measure thecurrent passing through remove the jumpers and connect the pins with a currentmeasuring device such as a multimeter or current probe.

The DSK provides +3.3V, up to 1A for the daughter card. The +3.3V supply is derivedfrom the +5V power source via the main +3.3 volt regulator. It is also possible toprovide the daughter card with +12V and -12V when the external power connector (J6)is used.

Table 1: Configuration Switch Settings

Switch 4 Switch 3 Switch 2 Switch 1 Configuration Description

Off 720 Mhz operation (60 Mhz input clock)

On 600 Mhz operation (50 Mhz input clock)

Off Off EMIF boot from 8-bit Flash

Off On No Boot

On Off Reserved

On On HPI boot

Off Little endian

On Big endian

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe TMS320C6416 DSK.

Topic Page

2.1 CPLD (Programmable Logic) 2-22.1.1 CPLD Overview 2-22.1.2 CPLD Registers 2-32.1.3 USER_REG Register 2-32.1.4 DC_REG Register 2-42.1.5 Version Register 2-42.1.6 MISC Register 2-52.2 AIC23 Codec 2-62.3 Sychronous DRAM 2-72.4 Flash Memory 2-72.5 LEDs and DIP Switches 2-72.6 Daughter Card Interface 2-8



2.1 CPLD (Programmable Logic)

The C6416 DSK uses an Altera EPM3128TC100-10 Complex Programmable LogicDevice (CPLD) device to implement:

• 4 Memory-mapped control/status registers that allow software control of various board features.

• Address decode and memory access logic.

• Control of the daughter card interface and signals.

• Assorted "glue" logic that ties the board components together.

2.1.1 CPLD Overview

The CPLD logic is used to implement functionality specific to the DSK. Your ownhardware designs will likely implement a completely different set of functions or takeadvantage of the DSPs high level of integration for system design and avoid the use of external logic completely.

The CPLD implements simple random logic functions that eliminate the need foradditional discrete devices. In particular, the CPLD aggregates the various resetsignals coming from the reset button and power supervisors and generates a globalreset.

The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industrystandard VHDL (Hardware Design Language) and included with the DSK.


2-3

2.1.2 CPLD Registers

The 4 CPLD memory-mapped registers allows users to control CPLD functions insoftware. On the 6416 DSK the registers are primarily used to access the LEDs andDIP switches and control the daughter card interface. The registers are mapped intoEMIFB data space at address 0x60000000. They appear as 8-bit registers with asimple asynchronous memory interface. The following table gives a high leveloverview of the CPLD registers and their bit fields:

The table below shows the bit definitions for the 4 registers in CPLD.

2.1.3 USER_REG Register

USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on oroff to allow the user to interact with the DSK. The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.

Table 1: CPLD Register Definitions

Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 USER_REG USR_SW3R

USR_SW2R

USR_SW1R

USR_SW0R

USR_LED3R/W

0(Off)

USR_LED2R/W

0(Off)

USR_LED1R/W

0(Off)

USR_LED0R/W

0(Off)

1 DC_REG DC_DETR

0 DC_STAT1R

DC_STAT0R

DC_RSTR

0(No reset)

0 DC_CNTL1R/W

0(low)

DC_CNTL0R/W

0(low)

4 VERSION CPLD_VER[3.0]R

0 BOARD VERSION[2.0]R

6 MISC McBSP2_ENR

(MCBSP2enabled)

SCR_4R/W

0

SCR_3R/W

0

DSPPLL_SELECT

R1

DSPPLL_ENABLE

R1

FLASH_PAGER/W

0(A19=0)

McBSP2ON/OFFBoardR/W

0(Onboard)

McBSP1ON/OFFBoardR/W

0(Onboard)

Table 2: CPLD USER_REG Register

Bit Name R/W Description

7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)




3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)






2.1.4 DC_REG Register

DC_REG is used to monitor and control the daughter card interface. DC_DET detectsthe presence of a daughter card. DC_STAT and DC_CNTL provide simplecommunications with the daughter card through readable status lines and writablecontrol lines.

The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.

2.1.5 VERSION Register

The VERSION register contains two read only fields that indicate the BOARD andCPLD versions. This register will allow your software to differentiate betweenproduction releases of the DSK and account for any variances. This register is notexpected to change often, if at all.

Table 3: DC_REG Register


7 DC_DET R Daughter Card Detect (1= Board detected)

6 0 R Always 0

5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)

4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)

3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)

2 0 R Always zero

1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)

0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)

Table 4: Version Register Bit Definitions

Bit # Name R/W Description

7 CPLD_VER3 R Most Significant CPLD Version Bit

6 CPLD_VER2 R CPLD Version Bit

5 CPLD_VER1 R CPLD Version Bit

4 CPLD_VER0 R Least Significant CPLD Version Bit

3 0 R Always 0

2 DSK_VER2 R Most Significant DSK Board Version Bit

1 DSK_VER1 R DSK Board Version Bit

0 DSK_VER0 R Least Significant DSK Board Version Bit


2-5

2.1.6 MISC Register

The MISC register is used to provide software control for miscellaneous boardfunctions. On the 6416 DSK, the MISC register controls how auxiliary signals arebrought out to the daughter-card connectors.

McBSP1 and McBSP2 are usually used as the control and data ports of the on-boardAIC23 codec. The power-on state of these bits (both 0s) represents that configuration. Set MCBSP1SEL or MCBSP2SEL to route the McBSPs to the daughtercardconnectors rather than the codec.

The Flash and CPLD share CE1 which means that the highest address bit (A21) isused to differentiate between the two. In this configuration 512Kbytes of 8-bit Flash arevisible at the beginning of CE1 which matches the chip on the production board. If theFlash is replaced with a 1Mbyte chip, only 512Kbytes of Flash will still be visible butFLASH_PAGE can be used to select between the top and bottom halves. FLASH_PAGE replaces the address bit (A21) that is lost sharing CE1 with the CPLD.

An on-board PLL is used to generate the DSP’s input clock frequency. TheDSPPLL_SELECT and DSPPLL_ENABLE bits are read-only versions of the PLLconfiguration signals. DSPPLL_ENABLE will read 1 if the PLL is enabled.DSPPLL_SELECT (set by configuration switch #4) switches between a 50 Mhz and 60 Mhz input clock.

The 6416’s PCI interface and McBSP2 share some pins. The McBSP2_EN signal isused to disable McBSP2 when the PCI interface is active. McBSP2_EN is generatedon the board when an appropriate daughtercard that uses PCI is plugged in, it can beread through this CPLD bit.

The scratch bits are unused. They can be set to any value.

Table 5: MISC Register


7 McBSP2_EN R Value of McBSP2_EN from PCI header

6 SCRATCH_4 R/W Scratch bit 4

5 SCRATCH_3 R/W Scratch bit 3

4 DSPPLL_SELECT R PLL select (0 = 50/600 Mhz, 1 = 60/720 Mhz)

3 DSPPLL_ENABLE R PLL enable (0 = off, 1 = on)

2 FLASH_PAGE R/W Flash address bit 19

1 MCBSP2SEL R/W McBSP2 on/off board (0 = on-board, 1 = off-board)

0 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)



2.2 AIC23 Codec

The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for inputand output of audio signals. The codec samples analog signals on the microphone orline inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples backinto analog signals on the line and headphone outputs so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internalconfiguration registers and one to send and receive digital audio samples. McBSP1 isused as the unidirectional control channel. It should be programmed to send a 16-bitcontrol word to the AIC23 in SPI format. The top 7 bits of the control word shouldspecify the register to be modified and the lower 9 should contain the register value. The control channel is only used when configuring the codec, it is generally idle whenaudio data is being transmitted,

McBSP2 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The DSK examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side. Thepreferred serial format is DSP mode which is designed specifically to operate with theMcBSP ports on TI DSPs.

The codec has a 12MHz system clock. The 12MHz system clock corresponds to USBsample rate mode, named because many USB systems use a 12MHz clock and canuse the same clock for both the codec and USB controller. The internal sample rategenerate subdivides the 12MHz clock to generate common frequencies such as48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATEregister. The figure below shows the codec interface on the C6416 DSK.

Figure 2-1, TMS320C6416 DSK CODEC INTERFACE

MIC IN

LINE IN

LINE OUT

HP OUT

ADC

DAC

McBSP2

DSP Format

0 LEFTINVOL1 RIGHTINVOL2 LEFTHPVOL3 RIGHTHPVOL4 ANAPATH5 DIGPATH6 POWERDOWN7 DIGIF8 SAMPLERATE9 DIGACT15 RESET

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FSX1

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AIC23 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT


2-7

2.3 Synchronous DRAM

The DSK uses a pair of industry standard 64 megabit SDRAMs in CE0 of EMIFA. Thetwo devices are used in parallel to create a 64-bit wide interface. Total availablememory is 16 megabytes.

The DSK uses an EMIFA clock of 120 MHz. The integrated SDRAM controller isstarted by configuring the EMIF in software. Timings can be found in the SDRAMdatasheet and the DSK help file. When using the SDRAM, note that one row of thememory array must be refreshed at least every 15.6 microseconds to maintain theintegrity of its contents.

2.4 Flash Memory

The DSK uses a 512Kbyte external Flash as a boot option. It is connected to CE1 ofEMIFB with an 8-bit interface. Flash is a type of memory which does not lose itscontents when the power is turned off. When read it looks like a simple asynchronousread-only memory (ROM). Flash can be erased in large blocks commonly referred toas sectors or pages. Once a block has been erased each word can be programmedonce through a special command sequence. After than the entire block must be erasedagain to change the contents.

The Flash requires 70ns for both reads and writes. The general settings used with theDSK use 8 cycles for both read and write strobes (80ns) to leave a little extra margin.

2.5 LEDs and DIP Switches

The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) thatprovide the user a simple form of input/output. Both are accessed through the CPLDUSER_REG register.



2.6 Daughter Card Interface

The DSK provides three expansion connectors that can be used to accept plug-indaughter cards. The daughter card allows users to build on their DSK platform toextend its capabilities and provide customer and application specific I/O. Theexpansion connectors are for memory, peripherals, and the Host Port Interface (HPI)

The memory connector provides access to the DSP’s asynchronous EMIF signals tointerface with memories and memory mapped devices. It supports byte addressing on32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals likeMcBSPs, timers, and clocks. Both connectors provide power and ground to thedaughter card

The HPI is a high speed interface that can be used to allow multiple DSPs tocommunicate and cooperate on a given task. The HPI connector brings out the HPIspecific control signals as well as McBSP2.

Most of the expansion connector signals are buffered so that the daughter card cannotdirectly influence the operation of the DSK board. The use of TI low voltage, 5V tolerantbuffers, and CBT interface devices allows the use of either +5V or +3.3V devices to beused on the daughter card.

Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET andDC_DET exist and are accessible through the CPLD DC_REG register. The DSKalso multiplexes the McBSP1 and McBSP2 of on-board or external use. This functionis controlled through the CPLD MISC register.

3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the TMS320C6416 DSKand its connectors.

Topic Page

3.1 Board Layout 3-23.2 Connector Index 3-33.3 Expansion Connectors 3-33.3.1 J4, Memory Expansion Connector 3-43.3.2 J3, Peripheral Expansion Connector 3-53.3.3 J1, HPI Expansion Connector 3-63.4 Audio Connectors 3-73.4.1 J301, Microphone Connector 3-73.4.2 J303, Audio Line In Connector 3-73.4.3 J304, Audio Line Out Connector 3-83.4.4 J302, Headphone Connector 3-83.5 Power Connectors 3-93.5.1 J5, +5 Volt Connector 3-93.5.2 J6, Optional Power Connector 3-93.6 Miscellaneous Connectors 3-103.6.1 J201, USB Connector 3-103.6.2 J8, External JTAG Connector 3-103.6.3 JP3, PLD Programming Connector 3-113.7 System LEDs 3-113.8 Reset Switch 3-12



3.1 Board Layout

The C6416 DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which ispowered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6416 DSK.

Figure 3-1, TMS320C6416 DSK

J4

J5J6 JP3

J302

J8SW1 SW2J201 D7-10

J304J303J301 J3 J1 J2


3-3

3.2 Connector Index

The TMS320C6416 DSK has many connectors which provide the user accessto the various signals on the DSK.

Note: “*” Not populated

3.3 Expansion Connectors

The TMS320C6416 DSK supports three expansion connectors that follow the TexasInstruments interconnection guidelines. The expansion connector pinouts aredescribed in the following three sections.

The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profileconnectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectorsare designed for high speed interconnections because they have low propagationdelay, capacitance, and cross talk. The connectors present a small foot print on theDSK. Each connector includes multiple ground, +5V, and +3.3V power signals so thatthe daughter card can obtain power directly from the DSK. The peripheral expansionconnector additionally provides both +12V and -12V to the daughter card. Therecommended mating connector, whose part number is TFM-140-32-S-D-LC, is asurface mount connector that provides a 0.465” mated height.

Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin

Table 1: TMS320C6416 DSK Connectors

Connector # Pins Function

J4 80 Memory

J3 80 Peripheral

J1 80 HPI

J301 3 Microphone

J303 3 Line In

J304 3 Line Out

J303 3 Headphone

J5 2 +5 Volt

J6 * 4 Optional Power Connector

J8 14 External JTAG

J201 5 USB Port

JP3 10 CPLD Programming

SW3 8 DSP Configuration Jumper



3.3.1 J4, Memory Expansion Connector

Table 2: J4, Memory Expansion Connector

Pin Signal I/O Description Pin Signal I/O Description

1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin

3 AEA21 O EMIF address pin 21 4 AEA20 O EMIF address pin 20




11 GND Vss System ground 12 GND Vss System ground








27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2

29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0


33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30




41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
















73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable

75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready

77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2



3-5

3.3.2 J3, Peripheral Expansion Connector

Table 3: J3, Peripheral Expansion Connector


1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin





11 N/C - No connect 12 N/C - No connect




19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin

21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source

23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data


27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect

29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data


33 CLKX2 I/O McBSP2 transmit clock 34 CLKS2 I McBSP2 clock source

35 FSX2 I/O McBSP2 transmit frame sync 36 DX2 O McBSP2 transmit data


39 CLKR2 I/O McBSP2 receive clock 40 N/C - No connect

41 FSR2 I/O McBSP2 receive frame sync 42 DR2 I McBSP2 receive data


45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input

47 N/C - No connect 48 EXT_INT5 I External interrupt 5

49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input


53 EXT_INT4 I External interrupt 4 54 N/C - No connect



59 RESET O System reset 60 N/C - No connect


63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control

65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status

67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7

69 ACE3# O Chip enable 3 70 N/C - No connect



75 DC_DET# Vss System ground 76 GND Vss System ground

77 GND Vss System ground 78 ECL KOUT O EMIF Clock




3.3.3 J1, HPI Expansion Connector

Table 4: J1, HPI Expansion Connector


1 PCI_EN I PCI enable 2 BSP2_EN I MCBSP2_EN

3 GND Vss System ground 4 HPI_RS# I HPI reset

5 XSP_CS O PCI serial 6 BEA13 I PCI EEPROM auto-init


9 AD1 I/O PCI address/data 1 10 PCBE0# I/O PCI command/byte ena 0

11 AD3 I/O PCI address/data 3 12 AD0 I/O PCI address/data 0



17 GND System ground 18 AD6 I/O PCI address/data 6

19 AD8 I/O PCI address/data 8 20 GND Vss System ground




27 GND Vss System ground 28 AD15 I/O PCI address/data 15

29 PCBE1# I/O PCI command/byte ena 1 30 GND Vss System ground

31 GND Vss System ground 32 PPAR I/O PCI parity

33 PSERR# I/O PCI system error 34 GND Vss System ground

35 GND Vss System ground 36 PSTOP# I/O PCI stop

37 PPERR# I/O PCI parity error 38 GND Vss System ground

39 GND Vss System ground 40 PTRDY# I/O PCI target ready

41 PDEVSEL# I/O PCI device select 42 GND Vss System ground

43 GND Vss System ground 44 PFRAME# I/O PCI Frame

45 PIRDY# I/O PCI initiator ready 46 GND Vss System ground


49 PCBE2# I/O PCI command/byte ena 2 50 AD18 I/O PCI address/data 18




57 AD23 I/O PCI address/data 23 58 PIDSEL I PCI init device select

59 PCBE3# I/O PCI command/byte ena 3 60 AD24 I/O PCI address/data 24




67 AD29 I/O PCI address/data 29 68 PGNT# I PCI bus grant


71 GND Vss System ground 72 PRST# I PCI reset

73 PREQ# O PCI bus request 74 GND Vss System ground

75 GND Vss System ground 76 PINTA# O PCI interrupt A

77 PCLK I PCI Clock 78 GND Vss System ground

79 GND Vss System ground 80 N/C - No connect


3-7

3.4 Audio Connectors

The C6416 DSK has 4 audio connectors. They are described in the followingsections.

3.4.1 J301, Microphone Connector

The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it ismonaural. The signals on the plug are shown in the figure below.

3.4.2 J303, Audio Line In Connector

The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.

Microphone In

Ground

Figure 3-2, Microphone Stereo Jack

Microphone Bias

Left Line In

Ground

Figure 3-3, Audio Line In Stereo Jack

Right Line In



3.4.3 J304, Audio Line Out Connector

The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.

3.4.4 J303, Headphone Connector

Connector J4 is a headphone/speaker jack. It can drive standard headphones or a highimpedance speaker directly. The standard 3.5 mm jack is shown in the figure below

.

Left Line Out

Ground

Figure 3-4, Audio Line Out Stereo Jack

Right Line Out

Left Headphone

Ground

Figure 3-5, Headphone Jack

Right Headphone


3-9

3.5 Power Connectors

The C6416 DSK has 2 power connectors. They are described in the followingsections.

3.5.1 J5, +5 Volt Connector

Power (+5 volts) is brought onto the TMS320C6416 DSK via connector J5. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. TheA diagram of J5 is shown below.

3.5.2 J6, Optional Power Connector

Connector J6 is an optional power connector. It will operate with the standard personalcomputer power supply. To populate this connector use a Molex #15-24-4041. Thetable below shows the voltages on the respective pins.

Table 5: J6, Optional Power Connector

Pin # Voltage Level

1 +12 Volts

2 -12 Volts

3 Ground

4 +5 Volts

PC Board

J5+5V

Ground

Front ViewFigure 3-6, TMS320C6416 DSK Power Connector

WARNING !Do not plug into J5 and J6 at the same time.



3.6 Miscellaneous Connectors

The C6416 DSK has 3 additional connectors to aid the user in developing with thisproduct. They are described in the following sections.

3.6.1 J201, USB Connector

Connector J201 provides a Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the DSK. This allows for code development and debugwithout the use of an external emulator. The signals on this connector are shown in thebelow.

3.6.2 J8, External JTAG Connector

The TMS320C6416 DSK is supplied with a 14 pin header interface, J8. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.The pinout for the connector is shown figure 3-6 below.

Table 6: J201, USB Connector

Pin # USB Signal Name

1 USBVdd

2 D+

3 D-

4 USB Vss

5 Shield

6 Shield

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 3-7, JTAG INTERFACE


3-11

The signal names for each pin are shown in the table below.

3.6.3 JP3, PLD Programming Connector

This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for theprogramming of the CPLD. This connector is not intended to be used outside thefactory.

3.7 System LEDs

TheTMS320C6416 DSK has four system light emitting diodes (LEDs). TheseLEDs indicate various conditions on the DSK. These function of each LED is shown inthe table below.

Table 7: J8, JTAG Interface

Pin # Signal Name

1 TMS

2 TRST-

3 TDI

4 GND

5 PD

6 no pin

7 TDO

8 GND

9 TCK-RET

10 GND

11 TCK

12 GND

13 EMU0

14 EMU1

Table 8: System LEDs

Reference Designator Color Function On Signal

State

D4 Green USB Emulation in use. When External JTAG Emulator is used this LED is off.

1

D3 Green +5 Volt present 1

D6 Orange RESET Active 1

DS201 Green USB Active, Blinks during USB data transfer 1



3.8 Reset Switch

There are three resets on the TMS320C6416 DSK. The first reset is the power onreset. This circuit waits until power is within the specified range before releasing thepower on reset pin to the TMS320C6416.

External sources which control the reset are push button SW2, and the on boardembedded USB JTAG emulator.

A-1

Appendix A

Schematics

This appendix contains the schematics for the TMS320C6416 DSK.Board components with designators between 200 and 299 (e.g. DS201,R211) are part of Spectrum Digital’s embedded JTAG emulator and are notincluded in these schematics.


A-2 TMS320C6416 DSK Module Technical Reference

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R23

10K

R40

10K

RN

19D

10K

RN

19E

10K

RN

19F

10K

RN

19G

10K

SW

1

SW D

IP-4

/SM

1234

8765

R78

150

TP10

TP

R98

10K

R97

10K

TP16

TP TP19

TP TP20

TP TP15

T P



CLK

MO

DE[

1:0]

: Cor

e C

LKIN

mul

tiple

s 0

0 =

x1 0

1 =

x6 1

0 =

x12

(Def

ault)

11

= R

eser

ved

Pla

ce a

ll PL

L ex

tern

al c

ompo

nent

s as

clo

seto

the

DSP

. All

PLL

exte

rnal

com

pone

nts

mus

t be

on a

sin

gle

side

of t

he b

oard

.

Max

imiz

e th

e di

stan

ce b

etw

een

switc

hing

sig

nals

an

d th

e P

LL e

xter

nal c

ompo

nent

s.

OPT

ION

AL

Advis

ory 1

.03.01

OP

TIO

NAL

ON

REV

D P

WB

AN

DH

IGH

ER

PLA

CE

CO

MP

ON

EN

TS O

N B

AC

KSID

EO

F PW

B A

S C

LOSE

TO

U10

PIN

H25

AS P

OSS

IBLE

.

3-PI

N S

MT

JUM

PER

S A

CC

EP

T 60

3R

ES

ISTO

RS

.

33 O

HM

, A T

O B

WH

EN

US

ED

, B T

O C

WH

EN

NO

T U

SE

D.

S1

S0M

ULT

IPLI

ER

4X 5.33

X

5X 2.5X

2X 3.33

X

6X 3X 8X

00 M

0 01

M0

MM

M1

10

1M

11

REV

E P

WB

AN

D H

IGH

ER

MU

LTIP

LIER

4X 5.33

X

5X 2.5X

2X 3.33

X

6X 3X 8X

600

MH

z

720

MH

z

AB E

NA

BLE

DS

PPLL

_S0/

S1D

RIV

E FR

OM

CP

LD

BC

US

E J

P50

0/JP

501

TOS

ET

FRE

QU

EN

CY

20 M

Hz

480

MH

z

MU

ST

DR

IVE

1/0/

Z, Z

FO

RO

PEN

0-BC

, 1-A

B, O

PEN

-M

0-BC

, 1-A

B, O

PEN

-M

M

0

0

S1

0 1M

11

0

M

M

M

1

0

S0

1

10 M

5059

42E

TMS

320C

6416

DSK

B

314

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

DS

P_C

OR

E_C

LK

EIN

T4EI

NT5

EIN

T6EI

NT7

TIN

P0

TIN

P1

TOU

T0TO

UT1

AEC

LKIN

CLK

MO

DE

1C

LKM

OD

E0

DS

P_T

DO

(13)

DS

P_T

RS

T#(1

3)

DS

P_T

MS

(13)

DS

P_TD

I(1

3)

DS

P_T

CK

(13)

DS

P_E

MU

0(2

)D

SP

_EM

U1

(2)

DS

P_R

ST#

DC

_EIN

T4( 1

0)

DC

_EIN

T6(1

0)D

C_E

INT7

(10)

DC

_TIN

P0

(10)

DC

_TIN

P1

(10)

DC

_EIN

T5(1

0)

DC

_TO

UT0

(10)

DC

_TO

UT1

(10)

DS

P_E

MU

9(2

)D

SP

_EM

U8

(2)

DS

P_E

MU

4(2

)

DS

P_E

MU

6(2

)D

SP

_EM

U5

(2)

DS

P_E

MU

2(2

)D

SP

_EM

U3

(2)

DS

P_E

MU

7(2

)

DS

P_EM

U11

(2)

DS

P_EM

U10

(2)

XD

S_4.

1V

DSP

IO_3

.3V

CLK

MO

DE

0C

LKM

OD

E1

DSP

PLL

_S0

DSP

PLL

_S1

DS

PPLL

_EN

ABL

E

DG

ND

3.3V

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

3.3V

DG

ND 3.3V

DG

ND

TP27

TP29

C40

0

NU

R29

1KR

30N

U

R27

1KR

28N

U

C40

1

NU

C92

0.1

TP28

TP5

E1

EX

CC

ET1

03U

EM

I FIL

TER

13

2

IO

GND

+C

T10

10

JP40

1

JPS

MT

1

2

3A

B

C

JP40

0

JPS

MT

1

2

3A B C

C12

1

0.1

C11

30.

01

R77

360

C40

2

.01U

FJP

402

JPS

MT

1

2

3A

B

C

JP50

2

JPS

MT

1

2

3A

B

C

C22

NO

-PO

P

Y1 20

MH

z

U40

0

ICS

512

1 2 3 45678

X1/C

LK

VDD

GN

D

RE

FC

LKS0

S1X2

C50

0

6pF

NPO

C50

1

6pF

NP

O

JP50

0

JPS

MT

1

2

3A B C

JP50

1

JPS

MT

1

2

3A

B

C

Y50

0

20M

Hz

U50

0

ICS5

12

1 2 3 45678

X1/C

LK

VDD

GN

D

RE

FC

LKS0

S1X2

C11

40.

1

R17

NO

-PO

P

L5 Ferri

te C

hip

R50

33

U21

SN

74C

BTD

3384

PW

1 133 4 7 8 11

2 5 6 9 10

14 17 18 21 22

24 1215 16 19 20 23

1OE

2OE

1A1

1A2

1A3

1A4

1A5

1B1

1B2

1B3

1B4

1B5

2A1

2A2

2A3

2A4

2A5

Vcc

GN

D

2B1

2B2

2B3

2B4

2B5

R51

NU

TP6

TP8

TP7

U10

E

TMS

320C

6416

GLZ

AF1

5A

C15

AE1

6A

D16

AC

16A

E17

AD

17A

F17

AC

17A

E18

AE1

9A

D18

AC

18

D6

B5

A4AF6

AE6

AD6

AC6

H4

H2

G1J6

AC7

B4

AF5

AE5

AD5

AF4

C6 A5 C5

AF18

AB16

AF16

AB15

H25 A1

1

EM

U0

EM

U1

EM

U2

EM

U3

EM

U4

EM

U5

EM

U6

EM

U7

EM

U8

EM

U9

TDO

EM

U10

EM

U11

TOU

T0TO

UT1

TOU

T2

GP

00G

P01

_CLK

OU

T4G

P02

_CLK

OU

T6G

P03

CLK

IN

CLK

MO

DE

0C

LKM

OD

E1

PLLV

RE

SE

T

NM

IE X

TIN

T4_G

P04

EXTI

NT5

_GP0

5EX

TIN

T6_G

P06

EXTI

NT7

_GP0

7

TIN

P0

TIN

P1

TIN

P2

TDI

TMS

TCLK

TRS

T

AEC

LKIN

BEC

LKIN


A-5

EM

IFA

& S

DR

AM

NE

AR D

SPN

EAR

DS

P

NEA

R S

DR

AM

NEA

R S

DR

AM

5059

42B

TMS

320C

6416

DSK

B

414

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

T AE

D34

TAE

D51

TAE

D48

TAE

D45

TAE

D42

TAE

D54

TAE

D46

TAE

D57

TAE

D56

TAE

D37

TAE

D43

TAED61

TAE

D55

TAED32

TAE

D44

TAE

D61

TAE

D33

TAE

D53

TAED58

TAE

D36

TAE

D49

TAE

D39

TAED55

TAED47

TAE

D62

TAE

D50

TAE

D32

TAE

D58

TAE

D38

TAE

D40

TAE

D47

TAED62

TAE

D60

TAE

D52

TAE

D63

TAED60

TAED53TA

ED

41

TAED50TAED51

TAE

D59

TAE

D35

TAED38

TAB

E3#

TAB

E2#

TAB

E7#

TAB

E6#

TAB

E0#

TAB

E5#

TAB

E4#

TAB

E1#

TAB

E4#

TAB

E5#

TAB

E7#

TAB

E6#

TAC

E2#

TAC

E0#

TAC

E3# TA

SDC

AS#

TAE

CLK

OU

T1TA

SDC

KE

TAED9TAED10

TAED31

TAED4

TAEA

12

TAE

D23

TAE

D22

TAE

A7

TAED17

TAED14

TAED0

TAE

A14

TAE

A8

TAEA

16

TAEA

6

TAEA

13

TAE

A4TA

ED

26

TAE

D21

TAE

D20

TAE

D11

TAE

D9

TAE

D7

TAED15

TAE

A12

TAE

A12

TAE

D4

TAED23TAED22

TAB

E2#

TAEA

4

TAE

D31

TAE

D28

TAE

D27

TAEA

7

TAED1

TAED7

TAEA

5

TAE

D29

TAE

D18

TAE

D3

TAE

A6

TAED16

TAED27TAED26

TAE

A3

TAEA

9

TAE

D13

TAE

D5

TAED12

TAB

E3#

TAB

E1#

TAE

D24

TAE

D1

TAE

A11

TAED28

TAE

D19

TAE

D2

TAE

A9

TAED18

TAED13

TAE

A13

T AE

D15

TAE

D8

TAED8

TAEA

5

TAED11

TAE

A16

TAE

A11

TAE

D17

TAE

D25

TAE

D10

TAED29

TAEA

9

TAE

A14

TAED24

TAED2

TAED25

TAEA

14TA

EA15

TAEA

8

TAEA

11

TAE

D30

TAE

D16

TAE

A15

TAE

A10

TAED21

TAED6

TAE

A8

TAE

A3

TAEA

7

TAE

A13

TAB

E0#

TAE

D6

TAED20

TAEA

6

TAED5

TAED30

TAE

A5

TAED19TA

EA10

TAE

D12

TAED3

TAEA

4

TAE

A10

TAE

A16

TAE

A15

TAEA

3TA

ED

14

TAE

D0

TAS

DR

AS#

TAS

DC

AS#

TAS

DW

E#

TAC

E0#

TAS

DW

E#

TASD

RAS

#TA

CE0

#

TASD

CAS

#

TAE

CLK

OU

T1TA

EC

LKO

UT1

TASD

CKE

TAS

DC

KE

TAE

A21

TAE

A17

T AE

A20

TAE

A22

T AE

A19

TAE

A18

TAA

RD

Y

AEA8

A EA2

0

ABE

1#

AED43

AED36

AEA1

4

AEA1

7

ABE

6#

AED39

AED47

AAR

DY

AEA1

3

ASD

WE#

AED58

AED46

AEA1

2

AEA1

5

ACE2

#

AED40

AEA3

AEA1

1

AEA1

8

ABE

5#

ABE

0#

ABE

2#

AED52

AED44

AEA5

AED59

AED34

ASD

CK

E

AED51

AED32

AEA9

AEA2

1

AE

CLK

OU

T2

ABE

4#

AED45

AED53

AED41

AEA4

AEA7

ACE0

#

AED35

ASD

CAS

#

AED48

AEA6

A EA1

9

AE

CLK

OU

T1

ABE

3#

AED42

AEA1

6

ABE

7#

AED38

AEA1

0

ACE3

#

AED33

AEA2

2

ASD

RAS

#

AED49

AED37

TASD

RA

S#TA

SDW

E#

TAED57

TAED42TAED41

TAED36

AED63AED62AED61AED60

AED57AED56AED55AED54

AED50

AED29

AED7

AED1AED0

AED14

AED11

AED4

AED18

AED16

AED13

AED2

AED30

AED21

AED9

AED6

AED17

AED20

AED15

AED27AED26

AED24

AED8

AED25

AED12

AED28

AED23

AED3

AED31

AED22

AED19

AED10

AED5

TAED33TAED34TAED35

TAED37

TAED39TAED40

TAED43TAED44TAED45TAED46

TAED48TAED49

TAED52

TAED54

TAED56

TAED59

TAED63

TAEA

17TA

EA1

7

TAE

A[22

..3]

(9)

TAA

RD

Y(9

)

TASD

RAS

#(2

,9)

TAS

DW

E#

(2,9

)

TASD

CAS

#(2

,9)

TAE

CLK

OU

T2(9

)

TAC

E2#

(2,9

)

TAB

E2#

(9)

T AB

E3#

( 9)

TAC

E3#

(2,9

)

TAB

E1#

(9)

TAB

E0#

(9)

TAED

[63.

.0]

(9)

3.3V

3.3V

DG

ND

DG

ND

DG

ND

3.3V

U10

A

TMS

320C

6416

GLZ

AD26AC26AC25AB25AB24AB26AA24AA25AA23AA26Y24Y25Y23Y26W23W24AD19AC19AF20AC20AE20AD20AF21AC21AE21AD21AF22AD22AE22AE23AF23AF24

T23

T24

R25

R26

M25

M26

L23

L24

L26

K23

K24

K25

M22

P22

N22

R22

J25

J24

K26

L25

J26

J23

A24A23B23B22C22A22C21B21D21A21C20B20D20A20D19C19H24H23G26G23G25G24F26F23F25F24E26E24E25D25D26C26

T22

V24

V25

V26

U23

U24

U25

U26

T 25

T26

R23

R24

P23

P24

P26

N23

N24

N26

M23

M24 L22

V23

AED32AED33AED34AED35AED36AED37AED38AED39AED40AED41AED42AED43AED44AED45AED46AED47AED48AED49AED50AED51AED52AED53AED54AED55AED56AED57AED58AED59AED60AED61AED62AED63

ABE

7A

BE6

ABE

5A

BE4

ABE

3A

BE2

ABE

1A

BE0

ACE3

A CE2

ACE1

ACE0

AP

DT

ABU

SREQ

0AH

OLD

AAS

OE3

A_A

RE/

SDC

AS/S

AD

S/S

RE

A_AO

E/SD

RAS

/SO

EA

_AW

E/S

DW

E/S

WE

ASD

CKE

AEC

LKO

UT1

AEC

LKO

UT2

AED0AED1AED2AED3AED4AED5AED6AED7AED8AED9AED10AED11AED12AED13AED14AED15AED16AED17AED18AED19AED20AED21AED22AED23AED24AED25AED26AED27AED28AED29AED30AED31

AEA2

2AE

A21

AEA2

0AE

A19

AEA1

8AE

A17

AEA1

6AE

A15

AEA1

4A E

A13

AEA1

2AE

A11

AEA1

0AE

A9AE

A8AE

A7AE

A6AE

A5AE

A4AE

A3

AAR

DY

AH

OLD

RN11F 33

RN14B 33

RN

8H33

R41

10K

RN

12C

33

RN

8G33

RN10D 33

RN13D 33

R44

33

RN14F 33

RN

12B

33

RN11B 33

R46

33R

4333

RN

8F33

RN

12A

33

RN13H 33

RN14A 33

RN11G 33

RN

8E33

TP18

RN

9H33

RN13C 33

RN

7B33

RN

7A33

RN14E 33

RN10E 33

RN

7H33

RN

7G33

RN

7F33

RN

7E33

RN

7D33

RN

7C3 3

RN11C 33

TP17

RN

8D33

C97

0.1

RN

9G33

C75

0.1

C73

0.1

RN6F 33

RN6H 33

RN4B 33

RN5F 33RN5E 33RN5D 33

RN5B 33

RN10A 33

RN13G 33

RN3C 33

RN3A 33

RN3G 33

RN5C 33

RN4D 33

RN6A 33

RN3D 33

RN6C 33

C95

0.1

RN

8C3 3

RN11H 33RN6G 33

RN4A 33RN5H 33

RN6E 33

RN3E 33

RN6D 33

RN4G 33

RN4C 33

RN4F 33

RN3F 33

RN4H 33

RN4E 33

RN5G 33

RN6B 33

RN3H 33

RN3B 33

C44

0.1

RN5A 33

RN

9F33

C74

0.1

U9

MT4

8LC

2M32

B2T

G-6

2 4 5 7 8 1 0 11 13 74 76 77 79 80 82 83 85 3 1 34 36 37 39 40 42 45 47 48 50 51 53 54 5633

24 66 6 5 64 63 62 61 60 27 26 2523 22 68 672071 16 19 18 1759 2 8 86 72 58 44 84 78 52 46 38 32 12 6

43 29 15 1 81 75 55 49 41 35 9 3

21 70 6973 57 30 14

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

DQ

16

DQ

18D

Q19

DQ

20D

Q21

DQ

22D

Q23

DQ

24D

Q25

DQ

26D

Q27

DQ

28D

Q29

DQ

30D

Q31

DQ

17

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

BA1

BA0

CLK

CK

E

CS

DQ

M1

DQ

M0

RAS

CAS W

E

DQ

M3

DQ

M2

VSS

VSS

VSS

VSS

VSS

QVS

SQ

VSS

QVS

SQ

VSS

QVS

SQ

VSS

QVS

SQ

VDD

VDD

VDD

VDD

VDD

QVD

DQ

VDD

QVD

DQ

VDD

QVD

DQ

VDD

QVD

DQ

NC

NC

NC

NC

NC

NC

NC

C45

0.1

U13

MT4

8LC

2M32

B2T

G-6

2 4 5 7 8 1 0 11 13 74 76 77 79 80 82 83 85 3 1 34 36 37 39 40 42 45 47 48 50 51 53 54 5633

24 66 6 5 64 63 62 61 60 27 26 2523 22 68 672071 16 19 18 1759 2 8 86 72 58 44 84 78 52 46 38 32 12 6

43 29 15 1 81 75 55 49 41 35 9 3

21 70 6973 57 30 14

DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

DQ

16

DQ

18D

Q19

DQ

20D

Q21

DQ

22D

Q23

DQ

24D

Q25

DQ

26D

Q27

DQ

28D

Q29

DQ

30D

Q31

DQ

17

A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1

BA0

CLK

CKE

CS

DQ

M1

DQ

M0

RAS

CAS

WE

DQ

M3

DQ

M2

VSS

VSS

VSS

VSS

VSS

QV

SSQ

VSS

QV

SSQ

VSS

QV

SSQ

VSS

QV

SSQ

VDD

VDD

VDD

VDD

VDD

QVD

DQ

VDD

QVD

DQ

VDD

QVD

DQ

VDD

QVD

DQ

NC

NC

NC

NC

NC

NC

NC

C42

0.1

RN

8B33

RN10F 33

RN13B 33

RN11D 33

RN14D 33

RN

9E33

R42

33

RN

8A33

TP11

R26

33

RN

9D33

RN13F 33

RN14H 33

RN10B 33

C41

0.1

C43

0.1

RN

9C33

RN13A 33

TP14

RN14C 33

RN10G 33

+C

T5 10

TP13

RN11E 33

R45

33

RN

9B33

R25

33

R48

33

+C

T13

10

R47

33

RN13E 33

RN10C 33

RN11A 33

RN14G 33

RN

9A33

TP12

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33

RN

12D

33

RN10H 33



EM

IFB

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H

LIL_

END

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BO

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LKIN

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1AE

CLK

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0BE

CLK

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EL1

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UTO

PIA

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R D

SP

NE

AR D

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END

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BO

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ED

IPU

IPU

IPD

5059

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320C

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Title

Size

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ber

Rev

Dat

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heet

of

BEA6

BEA1

7

BEA7

BEA1

1

BEA1

9

BEA8

BEA3

BEA1

0BE

A9

BEA2

0

BEA1

2

BEA2

BEA1

4BE

A13

BEA1

5

BEA1

8

BEA1

6

BEA5

BEA4

BEA1

BE

CLK

OU

T2

TBA

OE#

BE

CLK

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BAR

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TBE

CLK

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E#

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E#

BC

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TBC

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TBE

CLK

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T2

TBED0

TBED5

TBE

D3

TBED2

TBE

D5

TBED1

TBED4

TBE

D1

TBED6

TBED3

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3TB

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15TB

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TBE

A11

TBE

A8

TBEA

8

TBEA

13TB

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6

TBEA

8

TBEA

12

TBEA

14

TBE

A14

TBEA

7

TBE

A18

TBE

A4

TBE

A13

TBE

A15

TBEA

15

TBE

A9

T BE

A16

TBEA

20

TBEA

10

TBEA

16

TBEA

2

TBEA

17

TBE

A14

TBE

A20

TBEA

5

TBEA

11

TBE

A12

TBE

A16

TBEA

9

TBE

A10

TBEA

19

TBE

A2

TBE

A11

TBEA

6

TBE

A3

BC

E0#

TBC

E0#

TBA

RE

#

TBE

A19

TBEA

18

TBC

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A13

BED1

BED6

BED3

BED0

BED7

BED4

BED2

BED5

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A1

TBE

A20

TBE

A19

TBE

A18

TBEA

[3..1

](2

)

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PP

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3 .3V

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ND

DG

ND

DG

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3.3V

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ND

DG

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3V

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ND

SW

3

SW

DIP

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M

1 2 3 4

8 7 6 5

TP26

R58

33

R87

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C93

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51K

R74

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33

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RN

17C

33

R85

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R70

1K

RN

17B

33

R50

31K

R86

1K

TP22

RN

17A

33R

N16

H33

RN

16G

33R

N16

F33

RN

16E

33R

N16

D33

RN

16C

33R

N16

B33

RN

16A

33R

N15

H33

RN

15G

33R

N15

F33

U15

AM29

LV40

0B

2 1 48345678 9

10 13 14

16181920212223242537 4627

26 28 11 1247

1529 31 33 35 38 40 42 44 30 32 34 36 39 41 43 4517

A14

A15

A16

A13

A12

A11

A10

A9A8 A19

NC

1N

C2

NC

3

A18

A7A6A5A4A3A2A1A0VC

C

VSS

VSS

CE

OE

WE

RE

SE

T

BY

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RY

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DQ

0D

Q1

DQ

2D

Q3

DQ

4D

Q5

DQ

6D

Q7

DQ

8D

Q9

DQ

10D

Q11

DQ

12D

Q13

DQ

14D

Q15

/A-1

A17

RN

15E

33R

N15

D33

R75

1K

RN

15C

33R

N15

B33

RN

15A

33

R71

NU

RN18H 33RN18G 33

R61

33

TP21

RN18F 33

R69

NU

RN18E 33

R59

33

RN18D 33RN18C 33RN18B 33RN18A 33

U10

B

TMS

320C

6416

GLZ

E16

D18

C18

B18 A18

D17

C17

B17 A17

D16

C16

B16 A16

D15

C15

B15 A15

D14

C14 A14

E11

B19

B10D10A9C10B9D9B8C9A7C8B7D8A6C7B6D7

E12

E14

E13

E15

A10

B11

C11

D12

D11

A13

C12

B12

A12

D13

C13

BEA

20B

EA19

BEA

18B

EA17

BEA

16B

EA15

BEA

14B

EA13

BEA

12B

EA11

BEA

10BE

A9BE

A8BE

A7BE

A6BE

A5BE

A4BE

A3BE

A2BE

A1

BAR

DY

BH

OLD

BED0BED1BED2BED3BED4BED5BED6BED7BED8BED9BED10BED11BED12BED13BED14BED15

BP

DT

BB

US

RE

Q0

BH

OLD

AB

SO

E3

B_AR

E/S

DC

AS/

SAD

S/S

RE

B_A

OE/

SD

RA

S/S

OE

B_A

WE

/SD

WE

/SW

E

BE

CLK

OU

T1B

EC

LKO

UT2

BCE

3B

CE

2B

CE

1B

CE

0

BBE

1B

BE0

R60

33

R62

33

R63

33

R64

33

R57

10K

TP30

TP23


A-7

MC

BS

P

5059

42A

TMS

320C

6416

DSK

B

614

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

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t Num

ber

Rev

Dat

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heet

of

CLK

X0

DX0

CLK

S0

DR

0

CLK

R0

DR

2D

X2

FSX2

CLK

S2

CLK

R2

CLK

X2

FSR

2

DC

ISO

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V

FSR

0FS

X0

MC

BSP

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N

DC

_DR

0(1

0)D

C_C

LKX

0(1

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C_C

LKR

0(1

0)D

C_C

LKS

0(1

0)

DC

_DX0

(10)

DC

_FS

R0

(10)

DC

_FS

X0(1

0)

DC

_CLK

S2

(10)

DC

_CLK

R2

(10)

DC

_CLK

X2

(10)

DC

_DR

2(1

0)

DC

_FSR

2(1

0)

DC

_FS

X2(1

0)

DC

_DX2

(10)

AIC

23SD

ATAO

UT

AIC

23SD

ATAI

N

BCLK

LRC

IN

LRC

OU

T

CP

LD_M

CB

SP2

_MU

X

X DS_

4.1V

3.3V

DG

ND

DG

ND

DG

ND

DG

ND

5V

DG

ND

DG

ND

DG

ND

R12

360

U10

D

TMS

320C

6416

GLZ

F4 D1

E1

D2

E2

C1

E3

AE4

AB1

AC2

AB3

AA2

AC1

AB2

AF3

CLK

S0

CLK

R0

CLK

X0

DR

0D

X0

FSR

0FS

X0

CLK

S2_G

P08

CLK

R2

CLK

X2_

XSP

CLK

DR

2_XS

PD

ID

X2_

XSP

DO

FSR

2FS

X2M

CB

SP2_

EN

C12

0

0.1

R1

1.6K

D1 LM

4040

DC

IM3-

4.1

21

C13 0.

1

R55

1K

U4

SN

74C

BT3

257P

W4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

U20

SN

74C

BTD

3384

PW

1 133 4 7 8 11

2 5 6 9 10

14 17 18 21 22

24 1215 16 19 20 23

1OE

2OE

1A1

1A2

1A3

1A4

1A5

1B1

1B2

1B3

1B4

1B5

2A1

2A2

2A3

2A4

2A5

Vcc

GN

D

2B1

2B2

2B3

2B4

2B5

U3

SN

74C

BT3

257P

W4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

R76

360



UTO

PIA

& H

OS

T P

OR

T I/F

UTO

PIA

Inte

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HP

I DAU

GH

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CA

RD

CA

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VIA

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SIG

NAL

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BIN

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LOC

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TOP

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ER/D

SP

PAD

8/P

AD10

WER

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APP

ED O

N R

EV A

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WB

.

REM

OVE

HAR

DW

IRE

OF

TBEA

11 O

N R

EV

EP

WB

5059

42E

TMS

320C

6416

DSK

B

714

Frid

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t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

UR

DA

TA4

UR

DA

TA0

UR

SOC

UX

DAT

A2

UR

DA

TA5

UR

DA

TA3

UX

DAT

A0

UXC

LKU

RC

LAV

UX

DAT

A6

UX

ADD

R1

UR

ADD

R0

UR

CLK

UX

DAT

A5

UR

DA

TA1

UXC

LAV

UXS

OC

UR

ADD

R3

UR

DA

TA2

UX

DAT

A4

UR

DA

TA6

UR

ADD

R1

UX

ADD

R0

UR

DA

TA7

UXE

NB

#

UX

DAT

A1

UX

DAT

A3

UR

ADD

R2

UR

EN

B#

UX

DAT

A7

UR

SO

C

UR

DAT

A0

UR

DAT

A6

UR

DAT

A2

UR

DAT

A4

UR

DA

TA1

UR

DA

TA5

UR

DA

TA7

UR

DA

TA3

UR

CLA

V

UX

DAT

A2U

XD

ATA0

UX

DAT

A4U

XD

ATA6

UR

ADD

R3

UR

ADD

R1

UR

ADD

R2

UR

ADD

R0

UR

ADD

R4

UXC

LAV

UXS

OC

UXC

LK

UX

ADD

R0

UX

ADD

R2

UX

ADD

R4

UXA

DD

R1

UXA

DD

R3

PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7PAD8PAD9PAD10PAD11PAD12PAD13PAD14PAD15PAD16PAD17PAD18PAD19PAD20PAD21PAD22PAD23PAD24PAD25PAD26PAD27PAD28PAD29PAD30PAD31

PDEV

SELn

PS

TOP

nP

TRD

Yn

PCB

E2n

PSE

RR

nPC

BE

1nPP

ER

Rn

PPAR

PCI_

EN

PIR

DY

nPF

RAM

En

PR

STn

P CLK

PIN

TAn

PG

NTn

PREQ

nPC

BE

3nPI

DS

EL

XSP

_CS

PCB

E0n

UR

CLK

UR

ENB

#

UXE

NB

#

CLK

X1

DX1

FSX1

CLK

X1

DX1

UXA

DD

R4

UXA

DD

R3

UR

ADD

R4

UX

ADD

R2

FSX1

PCI_

EN

XSP_

CS

PAD

1PA

D3

PAD

5PA

D7

PAD

8

PAD

12P

AD14

PC

BE

1n

PS

ER

Rn

PD

EVS

ELn

PIR

DYn

PC

BE

2n

PAD

19

PAD

23P

CB

E3n

PAD

25

PAD

29P

AD31

PR

EQ

n

PC

LK

PAD

10

PAD

21

PAD

27

PAD

17

PP

ER

Rn

PC

BE0n

PAD

0P

AD2

PAD

4P

AD6

PAD

9P

AD11

PAD

13P

AD15

PPA

R

PS

TOP

n

PTR

DY

n

PFR

AMEn

PAD

16P

AD18

PAD

20P

AD22

PID

SEL

PAD

24P

AD26

PAD

28P

AD30

PG

NTn

PR

STn

PIN

TAn

UXD

ATA5

UXD

ATA3

UXD

ATA1

UXD

ATA7

HP

I_R

ES

ET#

CTL

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1

CTL

_DX

1

CTL

_CLK

X1

CPL

D_M

CB

SP1_

MU

X

MC

BSP

2_E

N

TBEA

13

TBE

A11

DG

ND

DG

ND

3.3V

DG

ND

5V

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

J2

SFM

-140

-L2-

S-D

-LC

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

R19

10K

U1

SN

74C

BT3

257P

W

4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2 S

1B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

R18

360

J1 SFM

140L

2SD

LC

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

JP50

3

SOLD

ER

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MP

ER

12

AB

U10

F

TMS

320C

6416

GLZ

AE9

AF11

AC9

AB13

AB11

AD7

AE7

AF7

AF9

AE8

AD8

AD9

AD10

AD11

AC14

AE15

AC13

AE10

AF10

AC10

AC8

AB12

AD13

AD14

AE12

AC12

AC11

AF13

AE11

AF12

AD12

AF14

AD15

AB14

UXA

DD

R0

UXA

DD

R1_

DR

1U

XAD

DR

2_FS

R1

UXA

DD

R3_

FSX1

UXA

DD

R4_

DX1

UXD

ATA0

UXD

ATA1

UXD

ATA2

UXD

ATA3

UXD

ATA4

UXD

ATA5

UXD

ATA6

UXD

ATA7

UX

CLK

UXC

LAV

UXE

NB

UXS

OC

UR

ADD

R0

UR

ADD

R1

UR

ADD

R2_

CLK

R1

UR

ADD

R3_

CLK

S1U

RA

DD

R4_

CLK

X1

UR

DA

TA0

UR

DA

TA1

UR

DA

TA2

UR

DA

TA3

UR

DA

TA4

UR

DA

TA5

UR

DA

TA6

UR

DA

TA7

UR

CLK

UR

CLA

VU

RE

NB

UR

SO

C

D2 LM

4040

DC

IM3-

4.1

21

R3

1.6K

C28 0 .

1

U10

C

TMS

320C

6416

GLZ

AA4

T3R2

T2T1P1R3

T4R1

J2K3J1K4K2L3K1L4L1M4M2N4M1N5N1P5U4U1U3U2V4V1V3V2W2W4Y1Y3Y2Y4AA1AA3

W3

AD1

M3L2F1J3G4F2G3

R4

P4

PCI_

EN

PPAR

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PP

ER

R_H

CS

PC

BE

1_H

DS

2P

SE

RR

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S1

PC

BE

2_H

R/W

PTR

DY

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WIL

PS

TOP

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NTL

0P

DE

VSE

L_H

CN

TL1

AD31_HD31AD30_HD30AD29_HD29AD28_HD28AD27_HD27AD26_HD26AD25_HD25AD24_HD24AD23_HD23AD22_HD22AD21_HD21AD20_HD20AD19_HD19AD18_HD18AD17_HD17AD16_HD16AD15_HD15AD14_HD14AD13_HD13AD12_HD12AD11_HD11AD10_HD10

AD9_HD9AD8_HD8AD7_HD7AD6_HD6AD5_HD5AD4_HD4AD3_HD3AD2_HD2AD1_HD1AD0_HD0

PC

BE0

XSP_

CS

PID

SEL

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9P

CB

E3_G

P10

PR

EQ

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1P

GN

T_G

P12

PIN

TA_G

P13

PC

LK_G

P14

PR

ST_

GP

15

PFR

AME

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TPI

RD

Y_H

RD

Y


A-9

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DIR

OPE

RA

TIO

NL

L

A

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A

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BH

X

IS

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N

DA

UG

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RC

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D B

UFF

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DC

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5059

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ber

Rev

Dat

e:S

heet

of

T AE

A13

DC

_D30

DC

_D16

DC

_D26

DC

_D14

DC

_D15

DC

_D4

TAE

A9

DC

_D10

DC

_D21

DC

_D25

TAE

D17

DC

_A19

TAE

A4

TAE

D11

TAE

D1

DC

_A2

TAE

A3

TAE

A21

TAE

A12

TAE

D21

DC

_A16

DC

_D19

DC

_D23

DC

_D3

DC

_A11

DC

_A20

T AE

A14

DC

_D24

DC

_D22

DC

_D8

DC

_A8

DC

_A9

TAE

A22

DC

_D11

DC

_D17

TAE

A10

TAE

D18

TAE

D13

DC

_D6

DC

_D1

DC

_A7

DC

_D20

DC

_A6

TAE

A20

TAE

A6

DC

_D5

DC

_D0

DC

_A15

TAE

A8

TAE

D9

TAE

D15

T AE

A15

DC

_D12

DC

_D31

TAE

A11

DC

_D7

DC

_D28

TAE

A7

DC

_D9

TAE

D24

DC

_D2

DC

_A4

TAE

A17

TAE

D16

DC

_A14

DC

_A21

DC

_A3

TAE

A19

TAE

D0

DC

_D18

DC

_D27

TAE

A18

DC

_A18

DC

_A5

DC

_A10

DC

_A17

TAE

A5

TAE

A16

TAE

D8

DC

_D13

TAE

D31

DC

_D29

TAE

D2

TAE

D3

TAE

D4

T AE

D5

TAE

D6

TAE

D7

TAE

D14

TAE

D12

TAE

D10 TA

ED

19TA

ED

20

TAE

D22

TAE

D23

TAE

D30

TAE

D29

TAE

D28

TAE

D27

TAE

D26

TAE

D25

DC

_A12

DC

_A13

DC

_A[2

1..2

](1

0)

TAE

A[22

..3]

(3) TA

ED[6

3..0

](3

)

DC

_D[3

1..0

](1

0)

TASD

WE

#(2

,3)TA

SDC

AS#

(2,3

) TAE

CLK

OU

T2(3

)

TAB

E0#

(3)TA

BE

2#(3

) TAC

E3#

(2,3

)

TASD

RAS

#(2

,3)

DC

_AR

DY

(10)

TAC

E2#

(2,3

)TAB

E3#

(3) TA

BE

1#(3

)D

C_B

E2#

(10)

TAAR

DY

(3)

DC

_EC

LKO

UT

(10)

DC

_BE

3#(1

0)

DC

_BE

0#(1

0)D

C_C

E3#

(10)

DC

_AW

E#

(10)

DC

_AO

E#(1

0)D

C_A

RE#

(10)

DC

_BE

1#(1

0)

DC

_CE

2#(1

0)

DC

_CN

TL_O

E#

DC

_EM

IFA_

DIR

(2)

DC

_EM

IFA

_OE

#(2

)

DG

ND

3.3V

DG

ND

3.3V

DG

ND

3.3V

3.3V

3.3V

3.3V 3.

3V

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

3.3V

DG

ND

3.3V

3.3V

U16

SN

74LV

TH16

245A

7 183142 47 46 44 43 41 40 38 37

2 3 5 6 8 9 11 1236 35 33 32 30 29 27 26

13 14 16 17 19 20 22 23

48 1 25 24 4 10 15 21

28 34 39 45

Vcc

Vcc

Vcc

Vcc

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R40

31K

U6

SN

74LV

TH16

245A

7 183142 47 46 44 43 41 40 38 37

2 3 5 6 8 9 11 1236 35 33 32 30 29 27 26

13 14 16 17 19 20 22 23

48 1 25 24 4 10 15 21

28 34 39 45

Vcc

Vcc

Vcc

Vcc

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R15

22

C15

0.1

C17

0.1

C16

0.1

C14

0.1

U17

SN

74LV

TH16

245A

7 183142 47 46 44 43 41 40 38 37

2 3 5 6 8 9 11 1236 35 33 32 3 0 29 27 26

13 14 16 17 1 9 20 22 23

48 1 25 24 4 1 0 15 21

28 3 4 39 45

Vcc

Vcc

Vcc

Vcc

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2 A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

R14

1K

C20

0.1

R13

10K

C19

0.1

C21

0.1

C18

0.1

U5

SN

74LV

TH16

245A

7 183142 47 46 44 43 41 40 38 37

2 3 5 6 8 9 11 1236 35 33 3 2 30 29 27 26

13 14 16 1 7 19 20 22 23

48 1 25 24 4 10 15 21

2 8 34 39 45

Vcc

V cc

V cc

Vcc

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1A8

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1OE

1DIR

2OE

2DIR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

C96

0.1

C94

0.1

C11

5

0.1

C11

6

0.1

C11

7

0.1

C99

0.1

C98

0.1

C11

8

0.1



DA

UG

HTE

RC

AR

D I/

F

Exte

rnal

Mem

ory

Inte

rface

Ext

erna

l Per

iphe

ral I

nter

face

5059

42C

TMS

320C

6416

DSK

B

914

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

DC

_D27

DC

_D11

DC

_D19

DC

_D9

DC

_A2

DC

_A18

DC

_A12

DC

_D5

DC

_D17

DC

_A14

DC

_A10

DC

_A17

DC

_D15

DC

_A19

DC

_D3

DC

_A21

DC

_D7

DC

_A6

DC

_A16

DC

_D13

DC

_A13

DC

_A3

DC

_D21

DC

_A9

DC

_D29

DC

_D23

DC

_A4

DC

_A5

DC

_A15

DC

_D1

DC

_A7

DC

_A11

DC

_A20

DC

_D25

DC

_A8

DC

_D20

DC

_D4

DC

_D31

DC

_D18

DC

_D22

DC

_D14

DC

_D2

DC

_D30

DC

_D6

DC

_D24

DC

_D26

DC

_D28

DC

_D16

DC

_D10

DC

_D0

DC

_D12

DC

_D8

DC

_DR

0(5

)DC

_CLK

S0

(5)

DC

_EIN

T7(2

)

DC

_CLK

X0(5

)

DC

_CLK

R2

(5)

DC

_A[2

1..2

](9

)

DC

_CN

TL0

(2)

DC

_BE

3#(9

)

DC

_AO

E#(9

)D

C_C

E2#

(9)

DC

_BE0

#(9

)

DC

_CLK

X2(5

)

DC

_TO

UT0

(2)

DC

_FS

R2

(5)

DC

_CN

TL1

(2)

DC

_TO

UT1

(2)

DC

_RS

T#(2

)

DC

_EIN

T4(2

)

DC

_AW

E#

(9)

DC

_DR

2(5

)

DC

_BE

1#(9

)

DC

_FS

X2(5

)

DC

_EIN

T5(2

)

DC

_EC

LKO

UT

(9)

DC

_FS

R0

(5)

DC

_TIN

P0

(2)

DC

_AR

DY

(9)

DC

_CLK

S2

(5)

DC

_DX0

(5)

DC

_FS

X0(5

)

DC

_CE

3#(9

)

DC

_EIN

T6(2

)

DC

_CLK

R0

(5)

DC

_D[3

1..0

](9

)

DC

_TIN

P1

(2)

DC

_AR

E#

(9)

DC

_DX2

(5)

DC

_BE2

#(9

)

DC

_DE

T(2

)

DC

_STA

T1(2

)D

C_S

TAT0

(2)

DG

ND

DG

ND

DG

ND

DG

ND

- 12V

1 2V

3 .3V

5V

3 .3V

5V

3 .3V

3 .3V

5V5V

3.3V

3.3V

R16

4.7K

R2

0

R65

10K

J4

CO

NN

EC

TOR

40

X 21

23

45

67

89

1011

1213

1415

1617

1819

2021

2223

2425

262 7

2 829

3031

3233

3435

3637

3839

4041

4243

4445

4647

4849

5051

5253

5455

5657

5859

6061

6263

6465

6667

6869

7071

7273

7475

7677

7879

80

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2 93 0

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

J3

CO

NN

ECTO

R 4

0 X

212

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2 72 8

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2 93 0

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980


A-11

3.3

sq in

AG

ND

, min

ther

mal

pad

Con

nect

at p

in 1

Set

s Vo

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3.3V

@1.

5Am

p M

ax

3.3

sq in

AG

ND

, min

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pad

1.4V

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p M

ax

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at p

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WARN

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DO N

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0.15

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5059

42D

TMS

320C

6416

TEB

B

1014

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

SE

NSE

_DS

P_C

VD

D

SVS

_RS

T#(2

)

DS

PIO

_3.3

V

DS

P_C

VD

D

AG

ND

3.3V

AG

ND

3.3V

5V

-12V

12V

DG

ND

DG

ND

DSP

IO_3

.3V

DS

P_C

VDD

DG

ND

DG

ND

5V

U7

TPS

5431

0PW

P

1 2 3 4 5 6 7 8 9 101112131415161718192021

AGN

DVS

ENSE

CO

MP

PW

RG

DB

OO

T

PH1

PH2

PH3

PH4

PH5

PG

ND

1P

GN

D2

PG

ND

3

VIN

1VI

N2

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3

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SSS

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AS

YN

CR

TPO

WE

RPA

D

C11

1000

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T9

10uF

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SR

C64

0.1u

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C63

0.1u

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U2

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5431

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P

1 2 3 4 5 6 7 8 9 101112131415161718192021

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ENSE

CO

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RG

DB

OO

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PH1

PH2

PH3

PH4

PH5

PG

ND

1P

GN

D2

PG

ND

3

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1VI

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VIN

3

VBIA

SSS

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AS

YN

CR

TPO

WE

RPA

D

TP32

Test

Poi

nt

1

C4

0.01

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750S

PT

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T3

10uF

LE

SR

C7

0.1u

F

C9

0.1u

F

L12.

7 uH

C3

0.04

7uF

C2

560p

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1.65

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%

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pFR

810

7 1%

R7 10

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3

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7

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M71

2

CE

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1%

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FC

3733

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R20

107

1%

R21

10K

1%

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3.74

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100u

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R38 10

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R31

71.5

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%

C6

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R9

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R66

0

C66

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JP2

NO

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P

12

JP1

NO

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12

R99

0

R4

0

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12

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GR

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C8

0.03

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T1

100

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T15

100

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M1

125_

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M3

125_

PHM

212

5_PH

M4

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R34

7N

UR

346

NU

TP2

TP

TP31

TP

TP1

TP

L4

BLM

41P

750S

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J6

NU

1234

+12

-12

GN

D+5

R52

180

D13

MU

RS

120T

3

D15

MU

RS

120T

3

D14

MU

RS

120T

3

D16

MU

RS

120T

3



DS

P P

OW

ER

& D

EC

OU

PLI

NG

All

capa

cito

rs o

n th

is s

heet

are

dec

oupl

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capa

cito

rs fo

r the

DS

P. T

hey

shou

ld b

e pl

aced

as

clos

e as

pos

sibl

e to

the

DS

P.

5059

42B

TMS

320C

6416

DSK

B

1114

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

DS

PIO

_3.3

V

DSP

_CVD

D

DG

ND

DG

ND

DG

ND

DG

ND

DSP

IO_3

.3V

DS

PIO

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V

DSP

IO_3

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DS

P_C

VDD

DSP

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D

DSP

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D

DS

P_C

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DS

PIO

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V

DSP

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C76

0.1

U10

H

TMS

320C

6416

GLZ

A2 A25

B1

B14

B26 E7

E8

E10

E17

E19

E20 F9 F12

F15

F18

G5

G22 H5

H22 J21

K5

K22 M6

M21 N2

P25

R21

U5

U22

V6 V21

W5

W22

Y5

Y22

AA9

AA12

AA15

AA18

AB7

AB8

AB10

AB17

AB19

AB20

A E1

AE13

AE26

AF2

AF25

L 5 M5

T5R5

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DVD

D

DVD

D

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

DD

VDD

DVD

D

DV

DD

DV

DD

DVD

D

DVD

D

U10

I

TMS

320C

6416

GLZ

A8 A19

B3

B13

B24 C

2C

4C

23C

25 D3

D5

D22

D24 E

4E

6E

9E

18E

21E

23 F5 F8 F10

F 11

F13

F14

F16

F17

F19

F22

G9

G12

G15

G18 H

1H

6H

21H

26 J5 J7 J20

J22

K21 L6 L2

1M

7M

20 N6

N21

N25 P

2

P6 P21

R7

R20

T6 T21

U6

U21

V5 V7 V20

V22

W1

W6

W21

W26

Y9 Y12

Y15

Y18

AA5

AA8

A A10

AA11

AA13

AA14

AA16

AA17

AA19

AA22

AB4

AB6

AB9

A B18

AB21

AB23

AC3

AC5

AC22

AC24

AD2

AD4

AD23

AD25

AE3

AE14

AE24

AF8

AF19

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

C52

0.1

C11

00.

1

C10

20.

1

C88

0.1

C78

0.1

C24

0.1

C10

40.

1

U10

G

TMS

320C

6416

GLZ

A1 A26

B2 B25

C3

C24 D4

D23 E5 E22 F6 F7 F20

F21

G6

G7

G8

G10

G11

G13

G16

G17

G19

G20

G21

H20 K7 K20 L7 L20

N7

P20

T7 T20

U7

U20

W7

W20

Y6

Y7

Y8

Y10

Y11

Y14

Y16

Y17

Y19

Y20

Y21

AA6

AA7

AA20

AA21

AB5

A B22

AC4

AC23

AD3

AD24

AE2

AE25

AF1

AF26

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CVD

DC

VDD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

C10

30.

1C

620.

1

C25

0.1

C32

0.1

C10

90.

1

C10

80.

1

C11

10.

1

C10

50.

1C

300.

1C

790.

1C

460.

1

C58

0.1

C50

0.1

C77

0.1

C34

0.1

C60

0.1

C90

0.1

C10

70.

1C

910.

1C

490.

1C

890.

1C

870.

1C

570.

1

C31

0.1

C61

0.1

C84

0.1

C10

10.

1

+C

T6 10

C35

0.1

C55

0.1

C80

0.1

+C

T8 10

C56

0.1

C86

0.1

C48

0.1

+C

T14

10+

CT1

110

C10

60.

1

C85

0.1

+C

T7 10

C53

0.1

U10

J

TMS

320C

6416

GLZ

F3 A3 G2

G14 H3

H7 J4 K6

N3

N20

P3

P7

R6

W25

Y13

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

RSV

C11

20.

1

C33

0.1

C54

0.1

+C

T12

10

C81

0.1

C26

0.1

C47

0.1

C27

0.1

C23

0.1

C10

00.

1

C82

0.1

C59

0.1

C83

0.1

C29

0.1

C51

0.1


A-13

J TAG

MUL

TIPL

EXER

S

EM

ULA

TIO

N

DSP

JTAG

HEA

DER

RO

UTE

TR

ACES

AS

ON

E G

RO

UP.

MAT

CH

SIG

NAL

LEN

GTH

.

LOC

ACTE

R-P

ACK

NEA

R D

SP

US

B IN

US

E

5059

42B

TMS

320C

6416

DSK

B

1214

Frid

ay, A

ugus

t 15,

200

3

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

XD

S_T

RS

T#T_

TMS

XD

S_E

MU

1

XD

S_T

DO

XD

S_T

MS

XD

S_E

MU

0

XD

S_T

VD

XD

S_TD

I

T_E

MU

1

XDS

_4.1

V

T_E

MU

0

HU

RR

ICAN

E_D

ETn

HU

R_E

MU

9H

UR

_EM

U8

HU

R_E

MU

3H

UR

_EM

U2

HU

R_E

MU

5H

UR

_EM

U4

HU

R_E

MU

7H

UR

_EM

U6

HU

R_E

MU

1H

UR

_EM

U0

MU

X_E

MU

0

MU

X_EM

U1

HU

R_E

MU

10H

UR

_EM

U11

HU

R_T

CK

HU

R_T

CK

RTN

T_TR

STn

T_TC

K

HU

RR

ICA

NE

_DE

Tn

XD

S_T

CK

RE

T

XD

S_T

CK

T_TC

K_R

ET

T_TD

O

T_TD

I

DS

P_T

DO

(2)

DS

P_TD

I(2

)

DS

P_T

MS

(2)

T_E

MU

0

T_E

MU

1

DS

P_E

MU

9(2

)D

SP

_EM

U8

(2)

DS

P_E

MU

2(2

)

DS

P_E

MU

7(2

)

DS

P_E

MU

3( 2

)

DS

P_E

MU

5(2

)D

SP

_EM

U4

(2)

DS

P_E

MU

6(2

)

T_TC

K_R

ET

DS

P_E

MU

0(2

)

DS

P_E

MU

1(2

)

DS

P_E

MU

10(2

)D

SP

_EM

U11

(2)

DS

P_T

CK

(2)

DS

P_T

RS

T#(2

)

T_TM

S

T_TC

K

T_TR

STn

XD

S_4.

1V

T_TD

O

T_TD

I

DG

ND

3.3V

DG

ND

DG

ND

DG

ND

3.3V

DG

ND

5V

DG

ND

DG

ND3.

3V

DG

ND

3.3V

DG

ND

DG

ND

DG

ND

3.3V

3.3V

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

DG

ND

3.3V

RN

1D42

RN

1E42

RN

2D42

RN

2C42

R92

33

R96

33

U24

SN

74LV

C1G

32

1 24

5 3

R93

1.6K

D5 LM

4040

DC

IM3-

4.1

21

RN

2A42

RN

2B42

C12

2

.1uF

R89

150

R95

100

1%

U26 SN

74LV

C1G

321 2

4

5 3

C12

6

22pF

J8

HE

ADER

7x2

, Em

ulat

ion

1 3 5 7 9

2 4 8 1011

1213

14

R90

47K

R67

47K

C12

4.1

uF

U19

SN

74C

BT3

257P

W4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

J7 HEA

DE

R 4

x15

A1 A2 A3 A4 A5 A6 A7 A 8 A9 A10

A11

A12

A13

A14

A15

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

B14

C14

B13

C13

B12

C12

B11

C11

B10

C10B

9C

9

B7

C7

B6

C6

B5

C5

B4

C4

B3

C3

B2

C2

B1

B15C

1C

15 B8

C8

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DT Y

PE

0G

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DTY

PE

1G

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

EMU

0EM

U1

EMU

2EM

U3

TCLK

EMU

4EM

U5

EMU

6EM

U7

EMU

8EM

U9

EMU

10

TDO

EMU

11EM

U12

EMU

13EM

U14

EMU

15

TDI

EMU

16EM

U17

TRS

TnTM

S

EMU

18

ID0

ID1

ID2

ID3

TVD

TCK

RTN

U25

SN

74C

BT3

257P

W4

14

711

9 1213 12 15103 5 6

16 8

1A

4B1

2A3B

13A 4A

4B2

S1B1

OE

3B2

1B2

2B1

2B2

VCC

GN

D

D4

LTS

T-C

150G

KT

R88

1K

R94

30.1

K

C12

3

0.1

U23

SN

74LV

C1G

32

1 24

5 3

U22

SN74

AH

C1G

14

3

4

5

2

U18 SN

74AH

C1G

14

3

4

5

2

RN

2E42

RN

2F42

RN

2G42

RN

1C42

RN

1A42

RN

1B42

RN

2H42

RN

1F42

RN

1G42

R91

1K

C12

5

0.1



54

32

1

D C B AH

iera

rcha

rica

l Blo

cks

5059

42A

TMS

320C

6416

DSK

B

1314

Frid

ayAu

gust

1520

03

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

USB

/Em

ulat

ion

USB

/Em

ulat

ion

5V

US

B_D

SP

_RS

T#

T_TD

O

T_TC

KT_

TMS

T_TR

STn

T_E

MU

0T_

EM

U1

T_TD

I

3.3V

PO

NR

Sn

GN

D

T_TC

K_R

ET

CLK

_12M

HZ

CLK

_24M

HZ

AIC

23 A

udio

AIC

23 A

udio

GN

D

DAT

A_B

CLK

DA

TA_S

YN

CIN

DAT

A_D

IND

ATA

_DO

UT

CTL

_DAT

AC

TL_C

LKC

TL_C

S

CO

DE

C_S

YSC

LK

AIC

3.3V

DA

TA_S

YN

CO

UT

CLK

_12M

HZ

US

B_D

SP

_RS

T#

T_TD

IT _

T MS

T_TC

K

T_E

MU

0T_

EM

U1

T_TD

O

SVS

_RS

T#

T _TR

ST n

T_TC

K_R

ET

CTL

_CLK

X1

CTL

_FS

X1

CTL

_DX1

BC

LK

AIC

23SD

ATA

OU

TLR

CO

UT

AIC

23SD

ATAI

NL R

CIN

CO

DE

C_C

LK

5V

DG

ND

3.3V

3.3V

DG

ND

DG

ND

3.3V

DG

ND

U11

SN74

LVC

1G32

1 24

5 3

C67

.1uF

R32

33


A-15

54

32

1

D C B A

Con

trol P

ort

AU

DIO 5059

42A

TMS

320C

6416

DSK

B

1414

Frid

ayAu

gust

1520

03

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:S

heet

of

LLIN

E_O

UT

RLI

NE

_OU

T

AIC

23LR

CIN

AIC

23C

S

SPIM

OD

E

3.3V

A

3.3V

A

AIC

3.3V

AIC

3.3V

AIC

3.3V

AIC

3.3V

AIC

3.3V

+

C31

910

uF

C32

60.

1uF

+

C32

510

uF

R32

64.

7K

R32

8N

O P

OP

R32

52.

2K

C32

20.

1uF

R33

54.

7K

R33

64.

7K

R33

44.

7K

R33

74.

7K

L306

BLM

21P

221S

N

+ C32

422

0uF

+C32

3220

uF

C34

1

0.1u

F

R34

30

C34

5N

O P

OP

C34

4N

O P

OP

C34

0N

O P

OP

C33

9N

O P

OP

L307

BLM

21P

221S

N

+

C31

5

1uF

C32

1

47pF

R33

247

K

C34

2

0.1u

F

J302

Hea

d P

hone

Out

3 4 2 1

C33

847

0nF

J303

Line

In

3 4 2 1

R33

347

K

C33

447

0nF

C33

347

0nF

+C

343

10uF

J301

Mic

roph

one

In

3 4 2 1

C33

20.

1uF

R34

533

L305

BLM

21P

221S

N C33

6N

O P

OP

R31

20

C33

747

0nF

R34

147

K

J304

Line

Out

3 4 2 1

+

C33

110

uFC

329

NO

PO

PL3

04B

LM21

P22

1SN

R33

80

R33

910

0

R34

247

K

RN

316

33

1 2 3 45678

RN

314

10K

1 2 3 45678

C33

5N

O P

OP

C33

0N

O P

OP

L303

BLM

21P

221S

N

L308

BLM

21P2

21SN

PW P

acka

geU

307 TL

V32

0AIC

23

22141115 25

34 5 212423

10 9 28

1 6 17 18 20 19

26 13 12

8

167

2 27

MO

DE

AVdd

HP

GN

DA

GN

D

XTI

/MC

LK

BC

LK

DIN

LRC

IN

CS

SC

LKS

DIN

RH

PO

UT

LHP

OU

T

DG

ND

VMID

MIC

_BIA

SM

IC_I

NLL

INE_

INR

LIN

E_IN

XTO

RLI

NE

_OU

TLL

INE

_OU

T

HPV

dd

BVdd

DO

UT

LRC

OU

T

CLK

OU

T

DVd

d

R34

010

0

R32

70

L301

HZ0

805E

601R

R34

42.

2

C31

8N

O P

OP

C31

6N

O P

OP

C31

7N

O P

OP

L309

BLM

21P

221S

N

C32

0N

O P

OP

+C

346

10uF

+C

347

10uF

R33

10

C32

7N

O P

OP

RN

315

10K

1 2 3 45678

C32

8N

O P

OP

L302

BLM

21P

221S

N

CTL

_CLK

CTL

_CS

CTL

_DA

TA

DAT

A_D

IND

ATA

_SY

NC

IND

ATA

_BC

LKD

ATA

_DO

UT

DA

TA_S

YN

CO

UT

CO

DE

C_S

YS

CLK

AIC

3.3V

GN

D

B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about theTMS320C6416 DSK produced by Spectrum Digital.


B-2 TMS320C6416 DSK Module Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE

Printed in U.S.A., November 2003505945-0001 Rev. B

dsk c6416b - Spectrum Digitalc6000.spectrumdigital.com/dsk6416/V2/docs/dsk6416_TechRef.pdf ·...

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