Abstract

A novel approach to testing CMOS digital circuits is pre-sented that is based on an analysis of voltage transients atmultiple test points and IDD switching transients on thesupply rails. We present results from hardware experi-ments which show distinguishable characteristics betweenthe transient waveforms of defective and non-defectivedevices. These variations are shown to exist in both thetime domain and frequency domain for CMOS open drainand bridging defects, located both on and off of a sensitizedpath.

1.0 IntroductionTransient Signal Analysis (TSA) is a parametric

approach to testing digital integrated circuits. TSA is basedon a measurement of the contribution to the transientresponse of a device by physical characteristics such assubstrate, power supply or parasitic coupling which arepresent in any circuit. Defect detection is accomplished inTSA by analyzing the variations produced by defects in thevoltage and current transients of defective devices. Thecurrent transients can be measured at the power supply I/Opins of a device without significant high frequency attenua-tion because of the absence of driver circuitry in the pads.However, these signals alone cannot be used to differenti-ate between the variations produced by defects and thoseproduced by fluctuations in process parameters. TSA isable to distinguish between these two types of variations byadditionally measuring voltage transients at a set of testpoints. The variations in multiple test point signals arecross-correlated to determine if the variation is regional orglobal. The absence of correlation in one or more of the testpoint signals indicates the presence of a catastrophic defect.On the other hand, the variations produced by fluctuationsin process parameters tend to be global and correlated in alltest point measurements.

In this paper, we present the results from four hard-ware experiments conducted on devices with bridging andopen drain defects. We demonstrate the regional and globalsignal variations that occur in the test devices by measuringthe voltage transients at a set of test points located on probepads on the surface of the die. The term Signature Wave-form or SW is used to describe the waveform that captures

these signal variations. In addition to presenting the set oftime domain Signature Waveforms for each of these exper-iments, we also present a set of frequency domain Signa-ture Waveforms. The frequency domain SWs of thedefective devices show variations in specific frequencycomponents that the time domain SWs are not able to por-tray. Consequently, defect detection sensitivity is enhancedin TSA if the frequency domain SWs are used in conjunc-tion with the time domain SWs.

The remainder of this paper is organized as follows. InSection 2 we present related research on device testing.Section 3 describes the Signature Waveform creation pro-cedures and the principles on which TSA is based. Section4 presents the results of hardware experiments conductedon devices with intentionally inserted bridging and opendrain defects. Section 5 gives a summary and conclusions.

2.0 Background and MotivationParametric device testing strategies [1][2] are based on

the analysis of a circuit’s parametric properties, for exam-ple, propagation delay, magnitude of quiescent supply cur-rent or transient response. Parametric methods have beenshown to be more effective than conventional logic basedmethods in detecting common types of CMOS defects[3][4]. Many types of parametric tests have been proposed[5] but recent research interest has focused primarily onthree types; IDDQ [6], IDD [7], and delay fault testing [8][9].

IDDQ is based on the measurement of an IC’s supplycurrent when all nodes have stabilized to a quiescent value[10]. IDDQ has been shown to be an effective diagnostictechnique for CMOS bridging defects, but is not applicableto all types of CMOS defects [11]. Although defect observ-ability is significantly improved by the addition of IDDQ to

logic tests, IDDQ is handicapped by the necessarily slowtest vector application rates, the limited resolution achiev-able for large ICs and the restricted class of CMOS circuitsto which it is applicable. Recently, concerns have beenraised over the applicability of IDDQ to deep sub-microntechnologies[12].

Several dynamic supply current IDD-based approacheshave since been proposed to overcome the limitationscaused by the static nature of the IDDQ test

Time and Frequency Domain Transient Signal Analysis for Defect Detection in CMOS Digital ICs

James F. Plusquellic, Donald M. Chiarulli and Steven P. LevitanTechnical Report, Department of the Computer Science

University of Pittsburgh1997

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[7][13][14][15][16]. In general, these IDD-based methodsare not hampered by the slow test application rates and arenot as sensitive to design styles as IDDQ, however, circuitsize and topology are still factors that affect the defect reso-lution of these schemes. Also, these methods do not pro-vide a means of accounting for changes due to normalprocess fluctuations and are therefore subject to aliasingproblems.

Alternatively, delay fault testing takes advantage of thefact that many CMOS defects cause a change in the propa-gation delay of signals along sensitized paths [4]. Since thetest is dynamic and regional, delay fault testing does notsuffer from slow test vector application rates, as is true ofIDDQ, and is not as sensitive to circuit size, like IDD. One ofthe difficulties with delay fault testing is that test vectorgeneration is complicated due to static and dynamic haz-ards [17]. Also, since the number of possible paths in a cir-cuit is much larger than the number of paths that aretypically tested, the effectiveness of a delay fault test isdependent on the propagation delay of the tested paths andthe delay defect size, for path delay fault testing, and theaccuracy of the test equipment, for gate delay fault test-ing[18]. Lastly, Pierzynska and Pilarski [19] have shownthat a non-robust test can detect a delay fault undetectable

by any robust test. Franco and McCluskey [20] and others[21][22][23] have proposed extensions to delay fault test-ing that address some of these difficulties.

Recently, Ma, et al. [24] and others [3][4][25][26]evaluated a large number of test methodologies and deter-mined that a combination of several test strategies may benecessary in order to find all defective devices. In particu-lar, Ma, et al. discovered that IDDQ cannot detect all kindsof defects and must be used with some kind of dynamicvoltage test. Our technique, Transient Signal Analysis(TSA), with its advantages in defect detection and processinsensitivity, is proposed as an addition to this test suite.

In previous papers [27][28], we have demonstratedthrough simulation experiments that global variations ofmajor device performance parameters, i.e. threshold volt-age and gate oxide thickness, result in measurable changesof the circuit’s transient response at all test points. In con-trast, the presence of a device defect will change both thevalue and topology of the parasitic components in theregion of the defect. For example, a single open circuit forthe connection to the drain terminal of a CMOS transistorwill remove a percentage of the normal parasitic capaci-tance present on the output node of the associated logicgate. Similarly, a bridging short between two or more gate

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output lines will add new parasitic resistive and capacitiveelements at each of the shorted nodes. We have shownthrough other simulation experiments that the changesintroduced by both of these classes of defects result in mea-surable variations in the transient response and that thesevariations are distinct at two or more test points.

3.0 TSA Procedures and PrinciplesTSA is based on the analysis of transient signal varia-

tions. In order to capture the variations produced by defectsand process parameter fluctuations in the test point signals,we create Signature Waveforms using the procedure shownin Figure 1. Shown in the upper portion of the left plot ofFigure 1 are the transient waveforms generated by twodevices at a test point located along a sensitized test path.Similarly, shown along the bottom are two transient wave-forms produced by the same two devices at a non-sensi-tized test point. Signature Waveforms (SWs) are createdfrom these pairs of transient waveforms by subtracting theTest device waveform from the Standard device waveform.The difference waveforms, shown in the right plot of Fig-ure 1, are then shaded along a zero baseline to add empha-sis to the variations. The frequency domain SWs arecreated by performing a discrete fourier transform (DFT)on the raw time domain waveforms as shown in Figure 2.Magnitude and phase SWs are created from the DFT’s out-put by subtracting the test device magnitude and phase val-ues from the corresponding values of the standard device.

Signature Waveforms capture the transient signal vari-ations produced by defects and process parameter fluctua-tions. TSA is able to distinguish between these two types ofvariation by analyzing the Signature Waveforms at multipletest points simultaneously. This is true because fluctuationsof process parameters tend to affect the physical propertiesof a device as a whole producing variations that are corre-lated across the Signature Waveforms of a device. On theother hand, the presence of a defect will have a larger influ-ence on the transients at test points closer to the defect.Therefore, defect detection is accomplished in TSA by ana-

lyzing the transients at all test points simultaneously so thatglobal process variations can be distinguished from theregional defect variations.

For example, the plots in Figure 3 show the SignatureWaveforms (SWs) produced at seven test points each fromthree test devices. The test points for these experimentswere located externally at the I/O pins of the devices. Theleft-most and middle plot show the SWs generated by twoknown defect-free devices while the right-most plot showsthe SWs generated by a known defective device. The testpoints are labeled TP 1 through TP 7 from top to bottomwhere TPs 1 through 6 are non-sensitized test points andTP 7 is sensitized. The defect-free test device whose SWsare shown in the left-most plot and the standard devicewere fabricated under almost identical conditions. Thevariation in TP 7 is negligible and the magnitude of thevariation in TPs 1 through 6 is less than 35 millivolts whichis very close to our noise threshold value.

Variations due to measurement noise are also presentin the SWs shown in the middle and right plots. However,other mechanisms are responsible for producing the uniquevariations in these SWs. In the middle plot, variationscaused by a small change in the fabrication process param-eters are observable in the SWs at all test points. Notably,TP 7 shows variation around 20 and 62 nanoseconds corre-sponding to a change in propagation delay along the pathdriving this test point while the magnitude of the variationin TPs 1 through 6 is less than 50 millivolts. More impor-tantly, however, is the correlation that exists across theSWs of defect-free devices. Since the variations caused bychanges in process parameters are global, it is possible tocharacterize the variations produced at any given test pointusing the variations produced on another test point. In con-trast, shown in the right-most plot are the SWs produced bya known defective device where the defect has been placedalong the path driving TP 7. The variation in TP 7 at 25 and65 nanoseconds results from the change in propagationdelay caused by the presence of the defect. This large sig-nal variation in the SW from TP 7 couples through the

Figure 3. Examples of SWs with global process variation and regional defect variation.

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power supply lines of the I/O pads into the SWs of TPs 1through 6. However, the variation created by the couplingof this signal is not uniform across each of the test pointSWs, notably the SWs of TPs 5 and 6 are distinct from theSWs of TPs 1 through 4 at 25 and 65 nanoseconds. Evenwithout observing the variation on TP 7, the absence of thecorrelation in the SWs across TPs 1 through 6 can be usedalone to identify this device as defective.

4.0 ExperimentsIn this section we present the results of several hard-

ware experiments designed to demonstrate that it is possi-ble to characterize ICs using time and frequency domainSignature Waveforms. The experiments were conducted onthree different versions of the ISCAS85 c432 benchmarkcircuit [29], a version with intentionally inserted bridgingdefects, a version with intentionally inserted open draindefects and a defect-free version. Four devices of each ver-sion were fabricated at MOSIS using ORBIT’s 2.0µmSCNA process. The defect-free devices were verified usingboth functional and Stuck-At test sets.

A digitizing oscilloscope with a bandwidth of 1 GHzwas used to collect a 2048 point waveform from each of thetest points. The averaging function of the oscilloscope wasused to reduce ambient noise levels. The waveforms weresubsequently passed through a low-pass filter to reduce RFnoise (above 250MHz). The experiments were run at 11MHz, about half the maximum clock rate of the devices.

The test points used in these experiments are labeledPRE-PAD and POST-PAD in Figure 4. Only a selected setof results are shown from the POST-PAD test point experi-ments and the reader is directed to reference [30] for anextended discussion. The PRE-PAD test points are 22micron square Metal 2 pads placed on the output nodes ofthe gates driving the seven primarily outputs of the c432.Since these test points are not driven by the I/O pad drivers,variation caused by coupling through the power supplylines of the pads has been minimized. In addition, the highfrequency components of the signals generated through thecore logic coupling mechanisms has been preserved. The

measurements were taken at a probe station using a Pico-Probe, model 12C, with a 100 FF and 1 MΩ load.

In each experiment four non-defective and four defec-tive devices were tested. The TSA testing process involvesapplying a test vector sequence to the primary inputs (PIs)of an IC and sampling the waveforms generated at the testpoints. In order to extract only the variation that occursbetween the test devices and the standard device, SignatureWaveforms were created in both the time and frequencydomain. The same defect-free standard device was used tocreate all SWs shown in this paper.

4.1 Bridging ExperimentsFirst we report on two bridging defect experiments.

Since the focus of these experiments is on signal coupling,we show only the SWs generated at the non-sensitized testpoints. Both experiments demonstrate the regional signalvariations created by the presence of the defect.

4.1.1 Bridging Experiment 1Figure 5 shows a portion of the schematic diagram of

the c432. Only those sensitized paths affected by the defectare shown. The input stimulus for this experiment togglesPI 66. PI 56 is held high and the other PIs (not shown) areheld low. The red dotted line in the figure represents thebridging defect which was created in the layout by insert-ing a first-level to second-level metal contact between theoutput lines of a 4-input NAND gate and an inverter asshown in Figure 6. This simulates an SiO2 defect. The onlyPO that changes logic state is 370. However, in the defect-free circuit, a static hazard causes a pulse to propagate toPOs 421 and 430 along paths shown in magenta in the fig-ure. Note that the bridging defect is not on any sensitizedpath and no contention exists between the two bridgednodes in steady-state. However, since the output of theinverter driven by PI 56 is low, the bridge eliminates thepulse produced by the hazard in the defective circuit.

Figure 6 shows the spatial relationships of all sensi-tized paths in a portion of the c432’s layout. Gates with nooutputs are shaded gray and indicate the termination of sig-nal propagation. For clarity, non-dominant inputs to thegates are not shown. Paths shown with thick blue lines cor-respond to the paths shown in blue in Figure 5. The thinblue lines are sensitized paths which terminate at internalgates and are not shown in Figure 5. A similar relationshipexists for the magenta lines in both figures. The bridgingdefect is shown in the figure as a shaded red circle. Thelightly shaded gates shown along the bottom of the figureremain at DC values in this experiment. Some of the driv-ing gates for PO 223 are shown to illustrate the potentialfor signal coupling between the DC outputs and the sensi-tized paths. Similar types of coupling exist for 329, 432 and431.

Each of the plots in Figure 7 shows a set of time

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domain or frequency domain SWs from a single test point.

The time domain SWs are always shown in the left-mostplot while the magnitude and phase are shown in the mid-dle and right-most plot respectively. Any given row acrossthe three plots represents the time and frequency domainSWs produced by a single device at the test point identifiedin the header. The top-most waveform of each plot is theoutput trace from the standard IC used in the differenceoperation to create the SWs shown below it. The next threewaveforms labeled DF#x (colored dark-green) are the SWs

from each of the three Defect-Free ICs. The next four SWs,labeled either BR#x for BRidging defects or OD#x forOpen Drain defects (colored red) are the SWs from thefour defective ICs.

As indicated in the schematic diagram of Figure 5,POs 223 and 329 are held high under this test sequence.The variations in the phase components of the BR#x SWsshown in right-most plots of Figures 7 and 8 can be used todistinguish between the defect-free and defective devices.For example, phase shifts occur in the phase SWs of

Figure 7. Time and Frequency Domain Signature Waveforms from PO 223 of Bridging Experiment #1.

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devices BR#1 and BR#4 at 100 MHz and between 10 and100 MHz for devices BR#2 and BR#3. No significant vari-ation occurs in the phase SWs of the defect-free devicesbelow 250 MHz. The magnitude SWs of the defectivedevices shown in the middle plots of these figures alsoshow distinguishable variation in the region between 50and 100 MHz. But the variation in the magnitude SWs ofDF#1 and DF#2 around 125MHz create an anomaly in thecharacterization of the defect-free devices. However, thisanomaly can be attributed to fluctuations of process param-eters if the magnitude SWs of POs 223 and 329 as well asPOs 431 and 432 (Figures 9 and 10) are consideredtogether. This is true because the variation is global in thatit occurs at the same frequency and with the same relativemagnitude in all four test point SWs. In summary, theseresults indicate that the defect delays and distorts specificfrequency components of off-path signals. This phenomenais difficult to see in the time domain SWs shown in the left-most plots of Figures 7 and 8 because other frequency com-ponents of the transient signals combine to mask these vari-ations.

The SWs generated by POs 370, 421 and 430 are notshown. PO 370 is the only sensitized path in this experi-ment. The variations in the SWs of this PO are dominatedby the variations caused by process parameter fluctuationand consequently, the regional variation produced by thedefect is difficult to observe. This result and the results

shown for the non-sensitized POs 223 and 329 suggest thatthe regional variation caused by a defect is most easilymeasured on steady-state test points. Moreover, the degreeto which a given test device is different from the standarddevice in terms of fabrication parameters is more accu-rately determined by measuring the variation that occurs inthe SWs generated on sensitized test points. This is truebecause changes in process parameters cause variationsthat are primarily characterized as changes in propagationdelay and this delay accumulates at each gate along thesensitized path.

POs 431 and 432 are held low under the test sequenceused in this experiment. Again we note specific phaseshifts and distortions of magnitude in the phase and magni-tude SWs of the defective devices shown in Figures 9 and10. However, the phase components that are shifted are dif-ferent than those observed in the SWs of POs 223 and 329.In this case, the frequency components around 20 MHzhave been delayed by the defect. We believe that thischange in phase variation is attributable to the difference inthe capacitance loading to substrate of the VDD and GNDsupply networks.

4.1.2 Bridging Experiment 2

Figure 11 shows a portion of the c432 schematic withthe sensitized paths for the second bridging experiment. PI69 is toggled while PI 82 is held high. All other PIs are held

Figure 9. Time and Frequency Domain Signature Waveforms from PO 431 of Bridging Experiment #1.

Figure 10. Time and Frequency Domain Signature Waveforms from PO 432 of Bridging Experiment #1.

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low. PO 432 is the only output that changes state in thisexperiment. Unlike the previous bridging experiment, thedefect is on the sensitized path driving PO 432. Again, nocontention exists between the two bridged nodes in steady-state and the circuit operates logically correctly under thistest sequence. Figure 12 shows the spatial relationships ofthe sensitized paths for the second bridging experiment.The bridging defect is shown in the figure as a red dottedline but is physically represented as an extra piece of sec-ond-level metal between the outputs of two 4-input NANDgates.

In order to determine if there exists a dependencybetween the observed regional variation and the frequencyof the applied stimulus, we reduced the frequency of theinput stimulus to 1 MHz for this experiment. This allowedus to examine the transients generated as a single edge waspropagated through the circuit under quiescent initial con-ditions similar to the conditions of an impulse experiment.We also extended the depth of data sample to capture anentire microsecond of data. The portion of the frequencyrange between DC and 100MHz is shown in the figures.

As shown in Figure 4, the gates driving the seven POsare located along the bottom and are connected throughcommon power and ground supply rails. Assuming that thesupply rails provide the predominate mechanism for cou-pling of transient signals between nodes, we would expecta relationship to exist between the SWs generated at thetest points and the topological position of the gates on thesupply rail. For example, since the gate driving 223 islocated furthest to the left with respect to the gate driven bythe path with the defect (432), we would expect the varia-tion in the defective device SWs to be smaller than the vari-ation produced on 430 or 431 which are much closer in thelayout, measured as the distance on the supply rail, to thec432. In fact we would expect the correlation in this varia-tion to increase in the test points from left to right in test

points 223, 329, 421, 370 and 430. Only the results from370, 421, 431 and 432 are shown. It is apparent in the timedomain SWs of Figures 13, 14 and 15 that using a slowerinput stimulus enhances the variations that occur betweenthe defective and non-defective devices. However, the fre-quency domain once again provides a clearer characteriza-tion of the two types of devices and the topologicaldependancy discussed above is more evident. For example,the magnitude and phase SWs of the defective devices inFigures 13 and 14 show distinctive characteristics in therange between 1 and 50 MHz. The corresponding set ofSWs in Figure 15 show distinctive characteristics over alarger range, in this case, between 1 and 70 MHz in themagnitude SWs and over the entire range in the phaseSWs. Since the gate driving 431 is adjacent in the layout tothe gate driving 432 (see Figure 12), the regional variationcaused by the defect has a stronger influence on the tran-sients at this test point than at test points 370 and 421. Fig-ure 16 clearly shows the large signal variation introducedby the presence of the feedback bridgin short.

4.2 Open Drain Experiments

The results of two open drain experiments are pre-sented in this section. Like the bridging experiments, wehave selected the test vector sequences so that no logicerror is generated at any of the POs. The first experiment issimilar to the first bridging experiment in that the signalsfrom static hazards are exploited for defect detection. Thetest sequence selected for the second experiment isdesigned to test the change in loading capacitance causedby the defect and in this sense represents a harder defectdetection experiment. The results of the experiment alsoserve to illustrate how process variations can affect defectdetection when the change in the transient response is min-imal.

Figure 17 shows the sensitized paths through the

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defective gates for the open drain experiments. The left

side of Figure 17 shows an open drain defect in the transis-

tor-level schematic diagram of a 4-input NAND gate. Athree micron wide piece of first-level metal has been

Figure 14. Time and Frequency Domain Signature Waveforms from PO 421 of Bridging Experiment #2.

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PO 421Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 421

Figure 13. Time and Frequency Domain Signature Waveforms from PO 370 of Bridging Experiment #2.

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PO 370Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 370

Figure 15. Time and Frequency Domain Signature Waveforms from PO 431 of Bridging Experiment #2.

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PO 431Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 431

9

removed between the p-transistor drain pairs. Both of theopen drain experiments test this type of defect in two dif-ferent 4-input NAND gates in the circuit. The input stimulifor the experiments is shown in the middle of the figure.The test sequence for the first experiment generates a num-ber of pulses at the POs which are created by a static haz-ard. The difference in the signal arrival times on the inputsto the NAND gate labeled G in Figure 17 cause the outputof the gate to pulse low in the non-defective circuit. Sincegate G drives input B of the 4-input NAND gate, the statichazard signals are not generated in the defective circuit. Forthe second experiment, the sensitized path is driventhrough functional input C of the NAND gate. The loading

capacitance on the output node of the NAND gate consistsof 118FF drain, 40FF routing and 59FF driven-gate capaci-tance. The open circuit removes two drains for approxi-

mately 42 FF or 19% of the total.

4.2.1 Open Drain Experiment 1As shown in Figure 17, the open prevents the propaga-

tion of static hazard signals along 3 separate paths in thedefective devices. Since the gates driving the metal 2 testpoints are all connected through a common power andground connection (see Figure 4), a larger amount of varia-tion occurs in the off-path SWs of this experiment than inthe previous bridging experiments. Moreover, the results ofthese experiments as well as the results from an experiment

Figure 16. Time and Frequency Domain Signature Waveforms from PO 432 of Bridging Experiment #2.

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PO 432Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 432

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Static 1/0/1 hazard

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PO 430

PO 432

111

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Vdd

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4 input NAND gate 0

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PO 329

PO 370PI 690/1/0

ABCD

0/1/0

Open Drain Experiment 2

Open Drain

PO 223...PO 329...

PO 370...PO 431... 0

PO 223...PO 421...

PO 431...

PO 430... 0

PO 432...

Static hazard signals

PI 37

PI 43PIs not shown are held low

PIs not shown are held low

Logic not shown

Open Drain Experiment 1

Figure 17. Portions of the c432 showing the sensitized paths from the open drain defects.

G

10

in which these signals were measured externally at the I/Opins provide a good illustration of the high frequency filter-ing properties of the I/O pad drivers. Consequently, theresults of both experiments are shown in the figures thatfollow. The SWs generated internally on the metal 2 padswill be referred to as the PRE-PAD results while those gen-erated externally will be referred to as POST-PAD results.Within any given figure, the PRE-PAD SW are shown inthe upper portion and the POST-PAD SWs are shown in thebottom portion. As in the previous experiments, both thetime and frequency domain results are shown for any givenoutput in three plots laid out horizontally across the page.

As shown in Figure 17, the path driving PO 223 is sen-sitized and the paths driving 329 and 370 propagate hazardsignals in both sets of devices. The results of this experi-ment (and the next) will also illustrate the variations thatoccur along these paths due to changes in propagation

delay induced by fluctuations in process parameters.

Figures 18, 19 and 20 show the PRE-PAD and POST-PAD SWs generated on 223, 329 and 370, respectively.The high frequency attenuation characteristics of the I/Opads can be observed in any of these figures by comparingthe OD#1 through OD#4 SWs generated PRE- and POST-PAD. It is important to note that the variation that occurs inthe OD#1, OD#2 and OD#4 POST-PAD SWs is due to achange in propagation delay of the paths driving these testpoints. Since this variation occurs in multiple test points(223, 329 and 370), it can be identified as that resultingfrom a change in process parameters and is not due to thepresence of a defect. We will evaluate this relationshipquantitatively for the results of the second open drainexperiment. Although obscured by the change in propaga-tion delay, the PRE-PAD SWs of the defective devices, ineither the time or frequency domain, show significant

Figure 18. Time and Frequency Domain Signature Waveforms from PO 223 of Open Drain Experiment #1.

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PO 223Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 223

Figure 19. Time and Frequency Domain Signature Waveforms from PO 329 of Open Drain Experiment #1.

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PO 329Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 329

11

amounts of variation and can be used to classify the devicesas defective and non-defective. As noted in the bridgingexperiments, the defect has caused delay in the frequencycomponents over the range of 150 to 200 MHz in the PRE-PAD phase SWs of the defective devices.

Figures 19 shows the time and frequency domain SWsfor the only non-sensitized test point, 431. Since this testpoint remains at steady-state 0, the variation due to thechange in process parameters is reduced in scale. Conse-quently, the PRE-PAD SWs in either the time or frequencydomain are more consistent and the variation caused by theabsence of the static hazard signals is more easily measuredin the SWs of the defective devices.

4.2.2 Open Drain Experiment 2This last experiment best illustrates the advantage in

using multiple transitioning test points to identify variationcaused by changes in process parameters. As shown in Fig-ure 17, the sensitized path is driven through function input

C of the 4-input NAND gate. Under these conditions, thedefective devices do not generate or propagate any largesignal variations due to the defect. The experiment wasdesigned to measure the change in propagation delaycaused by the defect on test points 329 and 370 since thepresence of the open removes a portion of the loadingcapacitance present on the output of the defective NANDgate. However, the predominance of variation caused thechanges in process parameters masks the variation causedby the defect in both the PRE- and POST-PAD SWs.

Only the POST-PAD time domain SWs generated attest points driven by the sensitized paths are shown in Fig-ure 21. In order to determine that the variation observed inthese SWs is due to a global change in process parameters,we have computed the set of sample correlation coeffi-cients relating the areas under the front and back edges sep-arately and placed the results into Table 1. Any given blockin the table represents the correlation coefficient computed

Figure 21. Time and Frequency Domain Signature Waveforms from PO 431 of Open Drain Experiment #1.

Figure 20. Time and Frequency Domain Signature Waveforms from PO 370 of Open Drain Experiment #1.

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PO 431Time Domain Frequency Domain - Magnitude Frequency Domain - PhasePO 431

12

between the areas calculated under the edges identified bythe row and column header. The results show that a highdegree of correlation exists between any two sets of edges.This suggests that the change in propagation delay mea-sured as area under the appropriate portion of the SWsresults from a global change in process parameters.

5.0 Summary and ConclusionsThe hardware experiments conducted on the c432 have

shown that it is possible to use the transient signals of adigital device to determine the presence of fabricationdefects. Variations in the transient response of any twodevices can be extracted by computing a polarized differ-ence waveform called a Signature Waveform. We haveshown that defects cause measurable variations to occur inSignature Waveforms generated at test points topologicallyclose to the defect site but not sensitized from the defectsite. By measuring the variations that occur at multiple testpoints simultaneously, we have also demonstrated that wecan distinguish between variations that occur due to thepresence of a defect and those that occur due to a change infabrication process parameters.

Coupling capacitances and power supply couplingbetween devices provide the mechanisms by which it ispossible to measure transient signal variations on non-sen-sitized test points. We have shown in both bridging experi-ments and the first open drain experiment that thevariations caused by defects are most easily measured inthe phase components of the discrete fourier transform of

the time domain transient signals. The first bridging exper-iment further illustrates that the defect causes a delay tooccur in different frequency components of the power andground supply rail transient waveforms.

The results of the second bridging experiment showthat the differences in the Signature Waveforms of defec-tive and non-defective devices are more pronounced whenthe frequency of the input stimulus is reduced. The resultsof this experiment also show the relationship that existsbetween the position of the test point with respect to thedefect site and the amount of variation that occurs in theSignature Waveforms. We have shown that test pointscloser to the defect site produce Signatures Waveforms thatare more distinctive then those produced on test points fur-ther removed when compared with the SWs generated by anon-defective device at these same test points.

By comparing the PRE-PAD and POST-PAD results ofthe first open drain experiment, we have demonstrated theattenuation that occurs to the high frequency componentsof the transient signals generated internally by the corelogic. We have also shown that changes in propagationdelay are not filtered by the I/O pad drivers. This suggeststhat defects that cause changes in propagation delay can bemeasured externally at the I/O pins given that multiple sen-sitized paths are monitored simultaneously so that defectdetections can be distinguished from false positives result-ing from changes in process parameters. Moreover, thisexperiment also demonstrates that regional variations that

Figure 22. SWs generated on all sensitized paths from Open Drain Experiment #2.

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13

occur internally are best measured on non-sensitized testpoints where the effects of process variation are de-empha-sized. This observation further suggests that the non-sensi-tized test points should be placed directly on the supplyrails in order to enhance the sensitivity of the measurementand reduce the number of test points required.

This work also demonstrates that process variation canstill make open drain defects difficult to detect under cer-tain test sequences, as we illustrated with the second opendrain experiment. However, the quantitative evaluation ofthe results of this experiment illustrates that it may be pos-sible to calibrate for variation caused by changes in processparameters since this variation is highly correlated at eachof the test point signals. This relationship permits the use ofa method based on the cross correlation of Signature Wave-forms to help identify which variations are caused by pro-cess variation and which are due to defects. Moreover,these results suggest that the most accurate account of pro-cess parameter fluctuations is obtained by measuring thedelays along the longest sensitized paths.

We are currently investigating a means of quantifyingthe degree of coupling through each of the main parasiticcoupling mechanisms, namely, power supply, internodal,well and substrate when defects are introduced into neigh-boring circuit components. This information and other sim-ulation experiments will help us determine the number andposition of the test points or the amount of observabilityrequired and subsequently, the number and type of test vec-tors necessary to achieve a given fault coverage and qualitylevel improvement factor. More hardware experiments arealso planned to determine the detectability of gate oxideshort defects and other types of opens and bridges.

References[1] Mark W. Levi. CMOS is Most Testable. In IEEE Test

Conference, pages 217-220, 1981.[2] F. Joel Ferguson, Martin Taylor and Tracy Larrabee.

Testing for Parametric Faults in Static CMOS Cir-cuits. In International Test Conference, pages 436-443, 1990.

[3] Charles F. Hawkins, Jerry M. Soden, Alan W. Righterand Joel Ferguson. Defect Classes - An Overdue Par-adigm for CMOS IC Testing. In International TestConference, pages 413-425, 1994.

[4] Jerry M. Soden and Charles F. Hawkins. Electricalproperties and detection methods for CMOS IC de-fects. In Proceeding of the European Test Conference,pages 159–167, 1989.

[5] A. P. Dorey, B. K. Jones, A. M. D. Richardson, andY. Z. Xu. Rapid Reliability Assessment of VLSICs.Plenum Press, 1990.

[6] Thomas M. Storey and Wojciech Maly. CMOS bridg-ing fault detection. In International Test Conference,pages 1123–1132, 1991.

[7] James F. Frenzel and Peter N. Marinos. Power supplycurrent signature (PSCS) analysis: A new approach tosystem testing. In International Test Conference, pag-es 125–135, 1987.

[8] E. P. Hsieh, R. A. Rasmussen, L. J. Vidunas, andW. T. Davis. Delay test generation. In Proceeding ofthe 14th Design Automation Conference, pages 486–491, 1977.

[9] Chin Jen Lin. On delay fault testing in logic circuits.IEEE Transactions on Computer-Aided Design,CAD-6(5):694–703, September 1987.

[10] Steven D. McEuen. IDDQ benefits. In VLSI Test Sym-posium, pages 285–290, 1991.

[11] Adit D. Singh, Haroon Rasheed, and Walter W. We-ber. IDDQ testing of CMOS opens: An experimentalstudy. In International Test Conference, pages 479–489, 1995.

[12] E. McCluskey(Moderator), K. Baker(Organizer),

Table 1: Estimated Sample Correlation Coefficients for Open Drain Exp #2.

F1 F2 F3 F4 F5 F6 B1 B2 B3 B4 B5 B6

F1 +1.00

F2 +1.00 +1.00

F3 +1.00 +0.99 +1.00

F4 +0.97 +0.96 +0.97 +1.00

F5 +0.96 +0.94 +0.96 +1.00 +1.00

F6 +0.96 +0.94 +0.96 +1.00 +1.00 +1.00

B1 -0.99 -0.98 -0.99 -0.97 -0.95 -0.95 +1.00

B2 -1.00 -1.00 -0.99 -0.98 -0.96 -0.96 +0.99 +1.00

B3 -0.99 -0.99 -0.99 -0.97 -0.96 -0.96 +1.00 +1.00 +1.00

B4 -0.97 -0.95 -0.97 -0.99 -0.98 -0.98 +0.98 +0.98 +0.99 +1.00

B5 -0.96 -0.95 -0.97 -0.99 -0.98 -0.98 +0.98 +0.97 +0.98 +1.00 +1.00

B6 -0.96 -0.95 -0.97 -0.99 -0.98 -0.98 +0.98 +0.97 +0.98 +1.00 +1.00 +1.00

14

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