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• Thin films in ULSI: Dielectrics, Conductors, and Semiconductors

Thin Films in ULSI

• Thin Film Deposition TechniquesChemical Vapor Deposition (CVD)

: utilize chemical gas and reaction for deposition

- Atmospheric pressure CVD (APCVD) - Low pressure CVD (LPCVD)- Plasma enhanced CVD (PECVD)- Metal organic CVD (MOCVD)- Atomic Layer Deposition (ALD)

Physical Vapor Deposition (PVD): utilize physical vapors

- DC/RF Sputtering- Molecular beam epitaxy (MBE)- Evaporation (e-beam or thermal)

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• Film deposition occurs – Nucleation– Coalescence– Continuous growth

Thin Film Growth

• Growth modes – 3-D island growth

• When atoms in clusters more strongly bond• Coalescence: two islands combine into one

to reduce energy• Metal, semiconductor on oxide

– 2-D layer-by-layer growth• When atoms are more strongly bound to

substrate• Single crystal epitaxy

– Stranski-Krastanov growth• Initially 2-D and then 3-D• Metal-metal, metal-semiconductor

Nucleation Coalescence Continuous growth

Ag film growth on (111) NaCl substrate

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Step Coverage (Conformality)

Conformal step coverage (ideal) CVD, Sputter

Actual Directional deposition(e-beam evaporator)

a) side step coverage = s / t

b) bottom step coverage = b / t

c) aspect ratio = h/d

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Epitaxial growth

• Epitaxy: single crystal layer on a single crystal substrate. MOCVD, MBE

Homoepitaxy: thin film and substrate have the same crystal structureSi on Si substrates

Heteroepitaxy: Lattice mismatch btw substrate and thin filmGaN on Saphire, SiGe on Si…

t<tc t>tc

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Vacuum System

Turbo (High)

Load Lock

Cryopump (High)Freezing water vapor and gases using refrigeration principle.

Rotary

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Evaporation (PVD)

Thermal Evaporation E-beam Evaporation

- Heat the boat (or sometimes filament) until source materials melts and evaporate the source material

- This is not the main deposition technique now for semiconductor industry due to bad step coverage,

-Electron beam is used to heat and evaporate the source materials

- A high-intensity electrons beam (energy up to 15keV) is focused on a source target containing the source material to be evaporated

W filament

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Sputtering (PVD)

- Sputtering of target is achieved by the bombardment of energetic ions, typically Ar+ plasma- Atoms at the target surface are dislodged and deposited on the wafer substrate - Dc plasma source can be used to deposit electrically conductive materials (e.g metal), in which the target acts as the cathode - RF power source is required for sputtering of not only the metal but also other dielectrics materials such as SiO2 or aluminum oxide to supply energy to the argon atoms. Low pressure, HDP, and higher dep rate.

input

RF power supply

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CVD Overview

• Thin film materials that can be deposited by CVD - Poly-Si, amorphous silicon- SiO2, Si3N4- Metals & Barriers: W, Ti, TiN, TaN, Cu

• Advantage over PVD: better step coverage

• CVD reactions 1) thermal decomposition:

- CH4(g) C(s) + 2H2(g)- SiH4(g) Si(s) + 2H2(g)- CH3SiCl3(g) SiC(s) + 3HCl(g)- WF6(g) W(s) + 3F2(g)

2) Oxidation and hydrolysis- SiH4(g) + O2 (g) SiO2(s) + 2H2(g)- 2AlCl3(g) +3H2OAl2O3(s) + 6HCl(g)

3) Compound formation- 3SiH4(g) + 4NH3(g) Si3N4(s) + 12HI2(g)

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CVD process

Reactants to deposition region

Transport into boundary layer Boundary layer

Adsorption Surface reactions

Desorption of byproducts

Pumping out

Wafer

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CVD Theory (Grove model)

Diffusion flux within Boundary layer

1 ( )G g sF h C C

Chemical reaction at surface

2 s sF k C

In a steady state condition(F1=F2),

When ks<<hG (low temp),

When ks>>hG (high temp),

growth rate R

gs G

G s

Ck hFRN h k N

s gR k C Surface-reaction-limited regime

G gR h C Mass-transfer-rate limited regime

(hG :mass-transfer coefficient)

(ks :surface reaction coefficient)

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Thermal CVD

• Operating pressure - APCVD: Atmospheric (750-760 Torr)- LPCVD: Low (0.1-5 Torr)

• APCVD- Planar wafer arrangement due to gas flow

- Limited wafer capacity, large amounts ofgas needed, mostly replaced by LPCVD

• LPCVD- Closely stacked wafer arrangement- Excellent uniformity and lots of wafers can be processed in a single run.

- Polysilicon gate for CMOS is grown by LPCVD at 600 ° C

SiH4(g) Si + 2H2(g)

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PECVD

• Plasma (non-thermal energy) is used to activate processes at lower temperatures

• Low temp and fast deposition rate is major advantage

• Wafer capacity is limited

N2O activation by RF plasma can lower CVD deposition rate (200-400 C) compared to other thermal CVD (O2 gas with temp over 400 C)

SiH4(g) + 2N2O (g) SiO2(s) +2N2(g) + 2H2(g)

DARC thin filmSiH4(g) + N2O (g) + He (g) SiON(s)

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CVD Thin Film in VLSI

• CVD Silicon nitrides for VLSI– Etch stop layer for damascene– CMP stop layer for STI– Dielectric layer for DRAM capacitor– Sidewall spacer – Final passivating layers

2 2 3 3 4 23SiCl H 4NH Si N 6HCl 6H

4 3 x y 2SiH NH SiN H H

LPCVD: 700-800 °C

PE-CVD: 200-400 °C

• CVD metal- Recently, CVD metal becomes more important due to good fill and conformality - W for plug fill, TiN, TaN diffusion barrier, Ti adhesion layer, Metal gates- W : low resistivity with good electromigration

- Ti: TiCl4 + 2H2 Ti + 4HCl at 650 °C - TiN: TiCl4+ NH3 at 700 °C

WF6(g) W(s) + 3F2(g)

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• Vapor phase epitaxy (Crystalline Si growth from vapor phase) is most common form of Si epitaxy.

• To have good growth rate control and minimize sensitivity to temperature variation, mass transfer region of 1200 ° C and silicon tetrachloride are widely used.

Si Epitaxy

Si

SiGe

Temperature vs Si epitaxial growth

SiCl4(g) + 2H2(g) Si (solid) + 4 HCl (g) : Epitaxy

SiCl4(g) + Si (solid) 2SiCl2(g) : Etching if SiCl4 is too high

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A thermal CVD process using metal-organic precursors as source materials• A popular technique for III-V epitaxy• Devices

- LD (laser diode), LED (light emitting diodes), photodetector, - HBT(heterojunction bipolar transistor), HEMT(high electron mobility transistor)

For GaAs,Ga(CH3)3(g)+AsH3(g) = GaAs (s) + 3CH4(g)

MOCVD

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• ALD deposits thin films in atomic scale precision • ALD chemistry is similar to CVD, but reaction

breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction.

• ALD film growth is self-limited and based on surface reactions

• ALD is used for depositing high-K dielectrics for reduces leakage current, faster switching speed, cooling transistors temperature

ALD temperature window

Atomic Layer Deposition (ALD)

• High-K dielectrics

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ALD Reaction

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Metallization

- Polysilicon and diffused Si (n+) can be connected together using the metal level. - Metal must be low sheet resistance to minimize voltage drops along the interconnect lines and to

minimize propagation delay caused by resistance and capacitance of the line.

Inexpensive, adhere wellRapid diffuser, deep level recomb. center

Advanced IC, rapid diffuser than Au

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Al metallization

450 ° C

• Al and Si has the eutectic temperature of 577 ° C, low melting temp. Due to low Tm, Al annealing has to be done after all high temp process.

• For good contact formation, Al is annealed at 450 ° C below the eutectic temperature. Al still diffuses into silicon, forming the Al spike.

Si solubility is from 0.25 to 1.5% btw 400 ° C and eutectic.

Solution is to co-deposite Al target with 1% Si.

Metallization and subsequent annealing does not absorb Si from the substrate.

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Electromigration

• Electromigratio (EM): The movement of metal atoms due to momentum transfer from the electrons carrying the high current which causes voids

EM of Al interconnection with 0.5% Cu(4% Cu alloy is better)

• Best Al target 98% Al, 4% Cu, 1% Si to minimize both EM and spiking.

MTF (mean time to failure) )/exp()( 2 kTEJ a

(J is current density ans Ea is activation energy for EM)

10 times more MTF

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Silicide Contact

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Silicide Contact

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Dual Damascene Cu Structures

TaN/Cu seed (PVD) (Electroplating)CMP

• Need for Cu over conventional Al- low resistivity RC delay reduction (<1 um)

- Less electromigration (EM)- Al etch to circuit dimension below 0.1 um is difficult.

• Merits of Dual Damascen Small Via contact Low resistivity Planarization

TaN for diffusion barrier btw Cu and insulator

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Tunable Workfunction metal gate (FUSI)

FinFETs and other Multi-Gate Transistors, Springer

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• Strain :

Strain Engineering

• Stress :

• Type of Stress

Uniaxial tensile stress Uniaxial compressive stress Biaxial tensile stress

E: Young’s modulus

Strain engineering plays an important rules from 90nm node modern MOSFET.

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Strain vs Mobility Enhancement

conduction band splitting ( ) decrease the conductivity mass (m*) decrease intervalley phonon scattering

Unstrained Si

All equivalent

Two fold valleys

Four fold valleys

(Lower energy)

(Higher energy)

• Constant-energy ellipses

Split

• Constant-energy ellipses

64

2

strainEUnstrained Si Strained Si

Four fold valleys

(Higher energy)

Two fold valleys (Lower energy)

)()( 426 energyHigherenergyLower

Strained Si

• Strain changing atomic structures breaking symmetry

iphT 111

mdk

Ed 2

2

2

Supplementary(Annu. Rev. Mater. Res. 39, 203, 2009)

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SiGe

SiSi

SiGe

Tensile stress Relaxed stress (X) :

Si on SiGe

Tensile stress to Strained Si region (or channel region)

aSi <aSiGe

Bulk Si Substrate

SiGe

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• Stress by S/D

aSi aSi

SiGe S/DSi • Operating mechanism of SiGe S/D

aSiC < aSi < aSiGe

Strain Technology

• Challenges of SiC S/D

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Strain Technology

• Dual Strain Liner

Gate

• Operating mechanism of stress liner

• NMOS Tensile stress mobility enhancement

PMOS Compressive stress mobility enhancement

(Contact etch stop nitride layer)

• In 22 nm node CMOS devices, it is expected that NMOS and PMOS have same driving current because strain effect is significant for PMOS devices compared to NMOS.