Thermal Test of an Improved Platform for Silicon Nanowire-Based Thermoelectric Micro-generators

C. CALAZA,1,3 L. FONSECA,1,4 M. SALLERAS,1 I. DONMEZ,1

A. TARANCON,2 A. MORATA,2 J. D. SANTOS,2 and G. GADEA2

1.—IMB-CNM (CSIC), Campus UAB, 08193 Bellaterra, Barcelona, Spain. 2.—IREC, C/Jardins deles Dones de Negre 1, pl 2a, 08930 Barcelona, Spain. 3.—e-mail: carlos.calaza@imb-cnm.csic.es.4.—e-mail: luis.fonseca@csic.es

This work reports on an improved design intended to enhance the thermalisolation between the hot and cold parts of a silicon-based thermoelectricmicrogenerator. Micromachining techniques and silicon on insulator sub-strates are used to obtain a suspended silicon platform surrounded by a bulksilicon rim, in which arrays of bottom-up silicon nanowires are integratedlater on to join both parts with a thermoelectric active material. In previousdesigns the platform was linked to the rim by means of bulk silicon bridges,used as mechanical support and holder for the electrical connections. Suchsupports severely reduce platform thermal isolation and penalise the func-tional area due to the need of longer supports. A new technological route isplanned to obtain low thermal conductance supports, making use of a par-ticular geometrical design and a wet bulk micromachining process to selec-tively remove silicon shaping a thin dielectric membrane. Thermalconductance measurements have been performed to analyse the influence ofthe different design parameters of the suspended platform (support type,bridge/membrane length, separation between platform and silicon rim,) onoverall thermal isolation. A thermal conductance reduction from 1.82 mW/Kto 1.03 mW/K, has been obtained on tested devices by changing the supporttype, even though its length has been halved.

Key words: Microgenerator, thermoelectricity, harvesting

INTRODUCTION

Most of world’s power use is generated by meansof heat engines using fossil fuel combustion, butalmost two-thirds of the energy that is fed into thesesystems radiates away, becoming a waste heatsource.1 Thermoelectric modules, which have thecapability of converting heat into electricity, havebeen proposed as a promising solution to turn thiswaste heat into useful power. Although recent re-search has been intensely exploring new materialsand technical routes to boost the efficiency of suchdevices, thermoelectric energy conversion still rep-resents a major scientific challenge towards aneffective waste heat recovery. Several high-perfor-

mance thermoelectric materials, such as Bi-Tebased alloys, skutterudite compounds, Ag-Pb-Sb-Tequaternary systems and half-Heusler compounds2–6

have been lately reported as efficient thermoelectricmaterials, but they are known to be scarce andexpensive, toxic in some cases, as well as difficult tointegrate in microelectronics. Alternative develop-ments focus on the smart structuring of mainstreammicroelectronic materials as a route to achieve sili-con-based thermoelectric generators. Individualsilicon nanowires (Si NWs) have shown an en-hanced thermoelectric performance over that of thebulk silicon (ZT � 0.01).7,8 However, even thoughimproved ZT values have been reported, the dis-cussion around whether this nanomaterial will en-able the production of competitive thermoelectricdevices is still open. Our aim is to work towardsan all-Si thermal generator by designing thermally

(Received June 12, 2015; accepted October 22, 2015;published online November 24, 2015)

Journal of ELECTRONIC MATERIALS, Vol. 45, No. 3, 2016

DOI: 10.1007/s11664-015-4168-8� 2015 The Author(s). This article is published with open access at Springerlink.com

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efficient silicon microplatforms suitable for thesubsequent monolithic integration of bottom-up SiNWs as thermoelectric active material.

DESIGN AND FABRICATION

The planar configuration proposed for the silicon-based thermoelectric microgenerator uses a siliconon insulator (SOI) substrate and silicon microma-chining techniques to define a thermally isolatedsuspended Si platform surrounded by a bulk Si rim.Both parts are subsequently linked by means of SiNW arrays that are grown on a CVD reactor using abottom-up vapour–liquid–solid (VLS) process.9 Inour previous work, the suspended platform waslinked to the bulk Si rim by means of bulk Sibridges, in addition to the Si NW arrays, acting asmechanical support and as a holder for the electricalconnections.9–11 However, this kind of support se-verely reduces the platform thermal isolation due tothe high thermal conductivity of the bulk Si, limit-ing the device ability to get a large temperaturegradient from a waste heat source. Hence, longbridge supports are needed to develop large thermalgradients and significant device area is wastedgiving rise to poor power densities. In this work, anew technological route has been set-up to increasethe platform thermal isolation by replacing suchsilicon bridges by thin dielectric membranes, with amuch lower thermal conductivity, which are used tosupport the metallic electrical connections. A par-ticular geometrical design is proposed to etch the Siunder the membrane area using a short wet bulkmicromachining process, which is enough to shapethese suspended low thermal conductance thinmembranes and, at the same time, improve thesurface quality of the h111i vertical walls where theSi NWs will be grown. A sketch of both designs isshown in Fig. 1.

They consist of a suspended silicon platform (S1)that will be later connected to a bulk silicon rim (S2)with Si NWs arrays. In former designs, the electri-cal connections were placed on top of bulk siliconbridges while in the new design proposed as an

alternative they are laying on a thin dielectricmembrane. The Si NWs will be grown perpendicularto the h111i walls that have been used to define thedifferent Si parts on the SOI device layer. Thetemperature difference attainable across such de-vices when operated in harvesting mode (placed ontop of a heat source) will essentially depend on thelength of the thermoelectric material connecting thehigh- and low-temperature areas, which is techno-logically limited by the tapering effect during NWsgrowth.12–15 Trenches for the successive linkage ofmultiple Si NW arrays have been developed in orderto overcome this problem, providing larger effectiveSi NW lengths. A detailed schematic of the intendedfinal structure is shown in Fig. 2. The fabrication isperformed on SOI wafers, with thicknesses of the Sidevice layer, buried oxide layer and handle Si waferof 15 lm, 0.5 lm, and 500 lm, respectively. Due tothe peculiarity of Si NWs growth, which takes placepredominantly along the h111i direction, a (110)surface orientation is selected for the SOI devicelayer surface, so that h111i planes can be exposed onvertically etched trenches. In contrast, the orienta-tion of the SOI silicon handle wafer does not playany role and a standard (100) orientation is used.

The fabrication process starts with the depositionof a 300 nm thick LPCVD Si3N4 layer, to be used asmechanical support for the metals. After patterningthis nitride layer using photolithography and a dryetch process, the metallization used to simultane-ously obtain the electrical connections with the sili-con device layer and a built-in heater element(electrically isolated from the silicon by the nitridefilm) was performed using a 30 nm thick tita-nium/tungsten (Ti/W) (10/90%) adhesion layer and a200 nm thick W layer deposited by sputtering. Asecond photolithography and a wet etch were used topattern the metal. Once the different metal struc-tures are patterned the surface is protected with a1 lm thick SiO2 layer deposited by PECVD. The laststep on the SOI device layer is to define the siliconstructures, i.e. the isolated platform and the tren-ches that will enclose the Si NWs. This is done with aphotolithographic step and a dry etch process thatsequentially removes the SiO2 and the silicon devicelayer, until the buried oxide layer is reached. Next, ashort (150 s) KOH etch step was performed on thewafer top side to release the nitride bridge. Thisnew step is critical, as it must remove the exposed Si

Fig. 1. Illustration of the microgenerator designs, classic (a) andproposed alternative (b). The isolated silicon mass (S1) is linked tobulk Si (S2) by means of a Si bridge (a) or alternatively by a thindielectric membrane (b) with lower thermal conductance. For bothdesigns, the area of the suspended platform is 1 mm 9 1 mm.Bridge and membrane lengths are 200 lm and 100 lm, respectively.

Fig. 2. Detailed device illustration showing the integration of the SiNWs on the SOI based structure. The featured area is a magnifi-cation of the [support membrane-platform-rim] region on Fig. 1(right). The length of the Si NWs is 10 lm.

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device layer only under the nitride/metal/oxidebridge, while preserving the other device functionalparts. In view of that, the membrane structure andthe etch holes have been designed with a specificangle to allow a fast Si under-etch, while permanentSi parts are preserved as vertical walls have beenaligned with h111i planes, which present a muchslower etch rate when exposed to KOH. The SEMimage of the bridge in Fig. 3 clearly shows that onlysmall Si islands, which are isolated from each other,remain under the bridge after this short KOH step.This wet etch process plays and additional role, as ithelps to restore the surface quality of the h111i ver-tical walls where Si NWs will be grown, removing thescalloping effect of the previous RIE etch (Boschprocess). Devices are completed by processing thebackside, using a 1 lm thick patterned aluminumlayer that acts as a hard mask for a DRIE processthat etches the handle wafer and the buried oxidelayer. This process sequence is intended to build thedifferent parts of the thermoelectric generator,maintaining all metals and silicon surfaces coveredby SiO2, except the Si vertical walls that expose theh111i planes for the silicon nanowire growth.

RESULTS AND DISCUSSION

A set of different devices has been produced usingthe described fabrication route. In addition, deviceswith the former bulk Si bridge supports have beenproduced (Fig. 4) to be used as reference to evaluatethe improvement attained in the thermal isolationof the suspended platforms. Devices with two dif-ferent bridge lengths (100 lm and 200 lm) and withdifferent number of trenches (1–4) have been fab-ricated using the new membrane-like supports.

Figure 5 shows a detail of the multiple trenchesused to increase the effective NW length. Each

trench is 10 lm wide and midway silicon bars (3 lmwide) are used to define consecutive trenches. Con-figurations for test purposes have been createdincluding a built-in heater (isolated from Si by theSi3N4 layer) to characterize the thermal isolation byforcing a controlled thermal gradient by Jouleheating.

The thermal isolation achieved with the differentdesigns has been assessed by measuring the totalthermal conductance between the bulk silicon andthe isolated platform, which accounts for the ther-mal conductivity of the different heat paths thatconnect both elements, i.e. the support (Si bridge ordielectric membrane), the Si bars that define the SiNW trenches and the surrounding air. Thermalconductance has been obtained using the integratedheater to dissipate a known power on the isolatedplatform and to simultaneously measure the devel-oped temperature gradient. For this purpose, thetemperature coefficient of the resistance (TCR) waspreviously measured for the heater material(1950 ± 25 ppm/�C) to calibrate the heater as athermometer.

First of all, the performance of the new supportswas compared with that of former bulk Si bridges. Aclassic design using two 200 lm long bridges hasbeen compared with a new design using a shorter100 lm long dielectric membrane, with a singletrench (T1) for both devices. Figure 6 shows thetemperature reached in the isolated platform as afunction of the power dissipated in the heater ele-ment. Despite the reduced length, the membraneoutperforms the bridge supports in terms of thermalisolation. Thermal conductance is almost halved,from 1.82 mW/K to 1.03 mW/K, pointing out thatbridge conductance was the main contribution tototal thermal conductance in old designs, turninginto a limiting factor for thermoelectric perfor-mance.

Next, the influence of the distance between theisolated platform and the bulk silicon rim in theactive area (the effective NW length) has beenanalyzed using a set of four devices featuring a100 lm long dielectric membrane support and thefour different trench designs (T1–T4). Figure 7shows the temperature reached in the isolatedplatform as a function of the power dissipated in theheater element. As anticipated, the number oftrenches has a significant effect on thermal isolationsince thermal conductance is reduced from1.03 mW/K for T1 to 0.68 mW/K for T4, the morenumerous the trenches, the better the thermal iso-lation. The observed trend and values point out thatthe conductance of these bars is the main contri-bution to total thermal conductance in the newmembrance designs. However, the thermal conduc-tance of these trenches once filled with NWs in realthermoelectric generators will depend also on theparameters used for NW growth, which determineNW size and density. A complete optimization willbe necessary to find a NW distribution and a num-

Fig. 3. SEM image of the supporting membrane after the KOH etch.Metal connections are sandwiched in a thin dielectric membrane,which is released by the silicon under-etch. Only small isolated Siislands remain.

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Fig. 4. SEM images showing the microfabricated platforms, with bulk Si (a) or thin dielectric (b) supports. Both are single trench devices andinclude a heater element for characterization purposes.

Fig. 5. SEM images of the silicon structures used to increase the effective nanowire length, from 10 lm (T1) to 40 lm (T4), with successivetrenches to be filled with Si NWs. The images are a magnification of the bottom-right region of the platform-rim area featured in Fig. 4.

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ber of trenches enhancing the thermoelectric per-formance, which shows an opposite dependency onthermal and electrical conductions.

Finally, the influence on thermal conductance ofthe length of the membrane support has been ana-lyzed using a set of two devices with 100 lm and200 lm long dielectric membranes (B1, B2), and thefour trenches design (T4). Figure 8 shows the tem-perature reached in the isolated platform as afunction of the power dissipated in the heater ele-ment. The small change observed in total thermalconductance, from 0.68 mW/K for B1 to 0.65 mW/K

for B2, after having halved the contribution comingfrom the membrane support, confirms that maincontribution to thermal conductance in new designsis linked to the silicon bars used to define thetrenches to be filled with Si NWs, as anticipated inthe previous measurement.

In the light of abovementioned improvement inthermal conductance, the new platform designs areexpected to generate higher power densities thancurrent devices using bulk Si bridges, which gen-erated a maximum power density of 9 lW/cm2 forDT = 27�C.9

Fig. 6. Temperature increase in the platform as a function of dissipated power for two devices with a single trench, one with 200 lm long bulk Sisupports (black) and other with a 100 lm long Si3N4 membrane (red) (Color figure online).

Fig. 7. Temperature increase in the platform as a function of dissipated power for devices with a 100 lm long Si3N4 membrane and differentnumbers of consecutive trenches (T1–T4) (black, red, blue, green) (Color figure online).

Thermal Test of an Improved Platform for Silicon Nanowire Based Thermoelectric Micro-generators 1693

CONCLUSIONS AND FUTURE WORK

A new technological route has been proposed tointegrate low thermal conductance supports with thesilicon micromachined suspended platforms used tobuild all-Si thermoelectric microgenerators. A set ofdevices based on this process have been successfullyfabricated and thermal measurements have revealedthat a significant thermal conductance reduction isattained with this membrane-like supports, eventhough shorter lengths are used. This result paves aroute to further improve the power density attainedwith the all-Si microgenerators based on Si NWs. Thecompatibility of the supports with the Si NWs growthprocess has to be confirmed, and the thermal con-ductance of the supports has to be contrasted withthat of the NWs arrays in order to establish theoptimum length for this new type of support (i.e., theattainable support area reduction).

ACKNOWLEDGEMENTS

This work has been supported by the EU FP7-NMP-2013-SMALL-7, SiNERGY (Silicon FriendlyMaterials and Device Solutions for MicroenergyApplications), under contract n. 604169, the Span-ish Ministry of Economy and Competitiveness(TEC-2010-20844) and the ‘‘Generalitat de Catalu-nya’’ (Advanced Materials for Energy Network(XaRMAE), 2009-SGR-440). C. Calaza and A. Tar-ancon would like to thank the financial support ofthe Ramon y Cajal postdoctoral program of theSpanish Ministry of Economy and Competitiveness.

OPEN ACCESS

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Fig. 8. Temperature increase in the platform as a function of dissipated power for two devices with 100 lm (B1, black) and 200 lm (B2, red) longSi3N4 membrane and four consecutive trenches (Color figure online).

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