THE ZERO-POLE TRANSFORMATION NOISE REDUCTION …hp310vp3671/Dissertation_Nasrin_Jaffari...Boris...

THE ZERO-POLE TRANSFORMATIONNOISE REDUCTION TECHNIQUE FOR ULTRA

LOW-NOISE CHARGE AMPLIFIERS

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULLFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Nasrin Jaffari

December 2011

This dissertation is online at: http://purl.stanford.edu/hp310vp3671

© 2011 by Nasrin Jaffari. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

ii

http://purl.stanford.edu/hp310vp3671

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Bruce Wooley, Primary Adviser


Boris Murmann, Co-Adviser


Katelijn Vleugels

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

iii

Abstract

This research focuses on the design of ultra low-noise charge amplifiers for use in

sensor and photo-detector systems. Charge amplifiers are used in the front-end design

of systems that have an input signal in the form of charge or a current pulse.

Applications for such systems include photography, radar imaging, medical imaging,

X-ray fluorescence applications and particle-physics experiments.

A charge amplifier is used to convert the incoming charge or current to a

voltage for further processing. The noise level of a charge amplifier determines the

minimum signal that can be measured by the system, as well as its resolution. There

are many applications that would benefit from imaging systems with lower noise

levels than those available today.

The objective of this research is to define the optimal flow for the design of a

low-noise charge amplifier. The work introduces a zero-pole transformation

technique that lowers the noise level of charge amplifiers without introducing much

complexity or requiring substantial extra area. This method may be implemented in

any sensor or imaging system that has an input in the form of a packet of charge or a

current pulse.

A zero-pole transformation charge amplifier has been designed in 0.18µm

CMOS technology and fabricated by National Semiconductor. The theory of the zero-

pole transformation technique is validated by the experimental design, the measured

v

results agreeing well with the expected noise reduction based on the theories

developed for the proposed method. The experimental zero-pole transformation

charge amplifier shows a reduction in 40% in its input-referred noise compared to a

basic charge amplifier. The minimum input-referred noise level achieved in the

proposed charge amplifier is 102ENC (equivalent noise charge).

vi

Acknowledgments

First and foremost I would like to thank my principal adviser, Professor Bruce A.

Wooley, for giving me the opportunity to perform research under his guidance and

take advantage of the many resources available at Stanford University. Professor

Wooley has granted me enormous freedom in forming my research objective which I

believe is an invaluable aspect of his advising style. I also appreciate his assistance in

improving the clarity and precision of my communication skills.

I would also like to extend special thanks to Dr. Katelijn Vleugels for her

support in forming and developing my research ideas. Katelijn has provided me with

extensive technical guidance which has made the conduct of this research possible.

I gratefully acknowledge the members of my orals committee: Professor

Murmann and Professor Gill I would like to thank the Molecular Biology Consortium

for providing financial support during much of my stay at Stanford University.

Additionally, I would like to express special gratitude to National Semiconductor for

the fabrication of the circuits I have developed as part of my research. The assistance

of the other student members of Professor Wooley's research group has been

invaluable in the design and testing of my prototype chip.

Finally, I would like to thank my husband for his support of my studies, which

has made the conclusion of this research possible. I would also like to acknowledge

my parents which have always encouraged me to pursue my studies.

vii

Table of Contents

Abstract...........................................................................................................................vAcknowledgments........................................................................................................viiList of Figures..............................................................................................................xiv

Chapter 1 Introduction 1

1.1 Motivation.........................................................................................................1

1.2 Organization...................................................................................…...............5

Chapter 2 Noise in Electronic Circuits 7

2.1 Fundamental Noise Sources..............................................................................7

2.1.1 Thermal Noise........................................................................................8

2.1.2 Flicker Noise..........................................................................................9

2.1.3 Shot Noise............................................................................................10

2.2 Noise in MOSFET Devices.............................................................................10

2.2.1 Thermal Noise in MOSFET Devices...................................................10

2.2.2 Flicker Noise in MOSFET Devices.....................................................12

2.2.3 Shot Noise in MOSFET Devices.........................................................13

2.3 Effect of Feedback on Noise...........................................................................14

2.4 Summary.........................................................................................................15

Chapter 3 The Charge Amplifier 17

3.1 Principle of Operation.....................................................................................17

ix

3.2 Reset Mechanisms...........................................................................................20

3.2.1 Pulsed Reset.........................................................................................20

3.2.2 Continuous Reset..................................................................................22

3.3 Performance Metrics.......................................................................................25

3.4 Noise...............................................................................................................28

3.5 Applications....................................................................................................30

3.5.1 X-ray Imaging......................................................................................31

3.5.1.1 Crystallography.......................................................................31

3.5.1.2 X-ray Fluorescence Analysis (XRF).....................................32

3.5.1.3 X-ray Astronomy...................................................................32

3.5.2 Particle Physics....................................................................................33

3.5.3 Optical Systems....................................................................................33

3.5.4 Medical Electronics..............................................................................35

3.5.5 Micro-Electro-Mechanical Systems (MEMS).....................................35

3.6 Summary.........................................................................................................36

Chapter 4 Low-Noise Charge Amplifier Design 39

4.1 Amplification Stages.......................................................................................40

4.2 Single-Stage Amplifier Topology....................................................................41

4.2.1 Common-Source Amplifier..................................................................42

4.2.2 Cascode Amplifier................................................................................42

4.2.3 Folded Cascode Amplifier....................................................................45

4.3 Input MOSFET................................................................................................45

4.4 Transistor Sizing.............................................................................................45

4.5 Correlated Double Sampling...........................................................................49

4.6 Pulse Shapers..................................................................................................50

4.7 Signal Averaging.............................................................................................51

4.8 Summary.........................................................................................................52

Chapter 5 Zero-Pole Transformation Noise Reduction 53

5.1 Boosting and De-boosting...............................................................................54

5.2 The Zero-Pole Transformation Theory of Operation......................................56

x

5.3 Architecture of a Zero-Pole Transformed Charge Amplifier..........................57

5.4 Noise Analysis of the Zero-Pole Transformed Charge Amplifier...................59

5.5 The Secondary Pole.........................................................................................62

5.6 Resistor Implementation.................................................................................63

5.7 Zero-Pole Mismatch........................................................................................70

5.8 Tradeoffs .........................................................................................................71

5.8.1 Reduced Input Range..........................................................................72

5.8.2 Speed...................................................................................................73

5.8.3 Area.....................................................................................................74

5.9 Summary.........................................................................................................74

Chapter 6 Charge Injection in the Zero-Pole Transformed ChargeAmplifier 75

6.1 Charge Injection Issues...................................................................................75

6.2 Sources of Charge Injection............................................................................76

6.3 Techniques for Reducing Charge Injection.....................................................78

6.3.1 Transistor Switch Size...........................................................................78

6.3.2 Switch Turn-Off Speed........................................................................78

6.3.3 Gate Voltage Swing of MOS Switch....................................................80

6.3.4 Dummy Transistors..............................................................................80

6.4 Summary.........................................................................................................82

Chapter 7 The Experimental Zero-Pole Transformed Charge Amplifier 83

7.1 System Architecture........................................................................................83

7.1.1 The Zero-Pole Transformed Charge Amplifier....................................84

7.1.2 Second Amplifier..................................................................................88

7.1.3 Buffer....................................................................................................89

7.1.4 Input Generation...................................................................................91

7.1.5 Clocks and Digital Calibration.............................................................92

7.1.6 Bias Circuitry........................................................................................96

7.1.7 Chip Micrograph..................................................................................96

7.2 Test Setup........................................................................................................96

xi

7.3 Measured Performance.................................................................................102

7.4 Summary.......................................................................................................107

Chapter 8 Conclusion 109

8.1 Summary.......................................................................................................109

8.2 Suggestions for Future Research...................................................................110

Bibliography 113

xii

List of Tables

Table 7.1: Various calibration levels for Rz and Rp............................................87

Table 7.2: Open-loop amplifier transistor sizes.................................................88

Table 7.3: Buffer block transistor sizes..............................................................90

Table 7.4: Transistor sizes of Reset generator circuit........................................94

xiii

List of Figures

Figure 1.1: 3DX chip photo..................................................................................4

Figure 1.2: 3DX chip top level diagram...............................................................4

Figure 2.1: (a) Noisy amplifier block, (b) Feedback-connect noisy amplifier....15

Figure 3.1: Schematic diagram of a basic charge amplifier................................18

Figure 3.2: Pulsed reset method in charge amplifiers.........................................21

Figure 3.3: Continuous reset method through a feedback resistor......................23

Figure 3.4: Noise analysis of the charge amplifier.............................................29

Figure 4.1: Two-stage amplifier configurations.................................................41

Figure 4.2: Frequency compensation of the two-stage amplifier …..................41

Figure 4.3: Common-source amplifier configurations with (a) resistor load, (b) transistor load............................................................................43

Figure 4.4: Cascode amplifier with cascode load..............................................44

Figure 4.5: Folded cascode amplifier.................................................................46

Figure 4.6: Simple amplifier for noise analysis.................................................46

Figure 4.7: Concept of correlated double sampling...........................................50

Figure 4.8: CR-RC shaper..................................................................................52

Figure 5.1: (a) Basic system, (b) System with boosting and de-boosting.........55

Figure 5.2: Zero-Pole transformed charge amplifier.........................................58

Figure 5.3: Noise analysis of the basic charge amplifier..................................60

xv

Figure 5.4: Noise analysis of the zero-pole transformed charge amplifier.......60

Figure 5.5: Resistance of MOSFETs vs. gate to source voltage.....................65

Figure 5.6: MOS-bipolar resistor....................................................................65

Figure 5.7: Resistance of MOS-bipolar resistor vs. Vds...................................67

Figure 5.8: Series-reverse-connected MOS-bipolar pair.................................68

Figure 5.9: Reverse-connected MOS-bipolar pair vs. single MOS-bipolar....68

Figure 5.10: N number of MOS-bipolar pairs connected in series...................69

Figure 5.11: Resistance of MOS-bipolar pairs connected in series..................69

Figure 5.12: Saturation of the intermediary node Vz.........................................73

Figure 5.13: Parasitics of MOS-bipolar resistors..............................................73

Figure 6.1: Basic structure of a MOS switch with input and load nodes........77

Figure 6.2: Charge injection for various transistor sizes.................................79

Figure 6.3: Charge injection for various turn-off times..................................79

Figure 6.4: Charge injection for various gate low voltage values...................81

Figure 6.5: Use of dummy switches for compensation of injected charge.....81

Figure 7.1: Architecture of the experimental system......................................84

Figure 7.2: Zero-Pole transformed charge amplifier.......................................85

Figure 7.3: Circuit diagram of resistors Rz and Rp...........................................86

Figure 7.4: Experimental folded cascode amplifier........................................87

Figure 7.5: Second amplifier of the experimental chip...................................89

Figure 7.5: Circuit diagram of the Buffer block..............................................90

Figure 7.7: The input generation block of the experimental chip...................92

Figure 7.8: Timing of on-chip clocks..............................................................93

Figure 7.9: Generation of Reset from CLK.....................................................94

Figure 7.10: Generation of Reset2 and VCLK......................................................95

Figure 7.11: Bias current generation.................................................................97

Figure 7.12: Bias voltage generation................................................................97

Figure 7.13: Chip micrograph...........................................................................98

Figure 7.14: Experimental test setup.................................................................99

xvi

Figure 7.15: Printed circuit board.....................................................................99

Figure 7.16: Block diagram of test setup.........................................................101

Figure 7.17: Output of the traditional charge amplifier (a) Qinject = 0fC (b) Qinject = 1fC...................? 1fC................... 1fC..........................................................................103

Figure 7.18: Output of zero-pole transformed charge amplifier (a) Qinject = 0fC, (b) Qinject = 1fC...................? 1fC................... 1fC..........................................................................104

Figure 7.19: Charge amplifier noise measurement........................................106

Figure 7.20: Charge amplifier simulation noise vs. measurement noise........106

Figure 7.21: Extended noise reduction results................................................107

xvii

Chapter 1

Introduction

The science of imaging is applied in various fields such as photography, radar

imaging, medical imaging, X-ray fluorescence applications and particle-physics

experiments. Digital imaging systems are typically composed of a sensor electrically

connected to a readout circuit. The sensor converts the input of the imaging system,

which could be in the form of visible light, X-rays or high-energy particles, into an

electrical signal. Subsequently, the electrical signal is transferred to the readout circuit

for digitization. The main performance metrics of imaging systems are sampling rate,

signal-to-noise ratio and efficiency.

1.1 Motivation

One of the most important performance metrics of a sensor system is its signal-to-

noise ratio. The signal-to-noise ratio of a system is a measure of the extent to which a

signal is corrupted by noise. Thus, it indicates how small a signal can be measured.

In an imaging system, both the sensor and the readout circuit contribute to the overall

noise present in the system.

1

2 Chapter 1: Introduction

Protein crystallography and the fluorescence analysis of materials are two

applications that employ X-ray imaging systems. X-ray fluorescence (XRF) analysis

is used to determine the composition of materials. In XRF applications, a low-energy

X-ray is emitted from a material after the material is bombarded with a high-energy

X-ray. The energy level of the emitted X-ray is a unique characteristic of the

material that can be used for material identification, and is measured using X-ray

detectors.

In protein crystallography a beam of X-rays is directed towards a protein

crystal, after which the beam is diffracted into many directions. By studying the

direction and intensity of the diffracted X-rays, the three dimensional structure of the

crystal can be determined. The locations and energy levels of the diffracted X-rays are

measured using X-ray detectors.

The wavelength of X-rays used in crystallography is on the order of 0.1nm,

which corresponds to an energy level of approximately 12keV. An X-ray with a

wavelength of 0.1nm is used for crystallography applications, because its wavelength

is on the same order of magnitude of molecular dimensions. Low-noise X-ray

detectors thus play a crucial role in the accurate determination of crystal structures.

X-ray detectors that are capable of detecting X-rays with energies much lower than

12keV are also used in many other scientific fields. For example, typical XRF

applications employ X-rays with energies as low 1.5keV. More recently, XRF

applications are being developed utilizing X-rays with energies as low as 60eV.

However, these applications are currently not realizable due to limitations imposed by

the high noise level of present-day X-ray detectors. Crystallography would benefit

from an X-ray detector with a lower noise level by increasing its accuracy. In

addition, low-noise X-ray detectors will allow the use of low energy X-rays in XRF

applications.

A typical X-ray detector consists of a sensor connected to a readout circuit.

Silicon pn-junction diodes or PIN diodes are commonly used as the sensor of X-ray

detectors. More recently, sensors have been developed that are composed of

1.1. Motivation 3

semiconductor materials other than silicon. These non-silicon sensors typically have

lower leakage currents and/or create more electron-hole pairs per unit of energy. The

incidence of an X-ray onto the sensor creates electron-hole pairs in the sensor that are

collected and transmitted to the readout circuit. Subsequently, the readout circuit

converts the analog current into a digitized output.

The signal in the readout circuit is typically passed through conditioning

circuitry before being digitized with an on-chip analog-to-digital converter (ADC).

The noise level of the sensor depends on the material from which it is formed and its

operating temperature. Similarly, the noise level of the readout circuit depends on its

operating temperature as well as other factors such as the circuits topology, the

fabrication technology, and the method of noise reduction used.

The motivation for this work came from working on the 3DX X-ray detector,

which was designed by the Molecular Biology Consortium for applications in protein

crystallography [1]. The detector uses 3DX technology to fabricate sensors, which

allows a sensor to be active on its edges to within 1µm of the surface. In the 3DX

detector, the sensors are directly bonded onto the ASIC in order to minimize parasitic

capacitance.

A photo of the 3DX chip is shown in Figure 1.1. The chip was designed in

0.25-µm technology and operates with a supply voltage of 2.5V. The detector has an

array of 8 x 64 pixels and each pixel measures 150µm x 150µm. A top level diagram

of the 3DX chip is shown in Figure 1.2. Each pixel has a charge amplifier, voltage

amplifier and memory capacitor. The output of each pixel is sent to an ADC for

digitization.

One of the purposes of working on the 3DX chip was to improve its noise

performance. The chip had an input-referred noise level of 400ENC. Typically, in

detector systems, including the 3DX detector, the charge amplifier is the main source

of noise. As described later in Chapter 4, by following simple sizing guidelines the

noise of a charge amplifier can be significantly reduced. Applying these guidelines to

the 3DX chip reduced its input-referred noise to 200ENC.


Figure 1.1: 3DX chip photo

Figure 1.2: 3DX chip top level diagram

1.2. Organization 5

The objective of this research is to define a flow for the design of charge

amplifiers that minimizes noise. The detailed design of a low-noise charge amplifier

is explored. Additionally, various noise-reduction techniques such as correlated

double sampling and shaping of the signal using a shaping filter are reviewed. Finally,

a novel zero-pole transformation noise reduction technique for charge amplifiers is

introduced.

A low-noise charge amplifier along with its relevant bias circuitry has been

designed in 0.18µm CMOS technology and fabricated by National Semiconductor.

Correlated double sampling is included in the design of this charge amplifier.

Additionally, a zero-pole transformation technique is embedded into the amplifier to

significantly reduce the noise introduced by the amplifier. Various digital calibration

options are included on the chip to allow for a thorough study of the zero-pole

transformation technique.

1.2 Organization

This dissertation is organized into eight chapters. The first chapter explains the

motivation for the research presented in this dissertation. The second chapter provides

a review of various sources of noise and their physical origins. Additionally,

analytical expressions for the various types of noise present in electronic devices are

presented, which provide the basis for noise analysis in the future chapters. Also, the

effect of feedback on noise is briefly discussed.

Chapter 3 describes the design of a typical charge amplifier for detector

systems. The operation of the amplifier along with its reset mechanisms are described,

and its noise performance is reviewed. The chapter concludes with a brief listing of a

number of applications which employ charge amplifiers. The specific requirements of

each application in regards to the charge amplifier design are set forth.

Chapter 4 provides an in-depth discussion of the design flow for a low-noise


charge amplifier. Design features such as number of amplification stages and single

vs. differential signaling are considered. Additionally, various amplifier topologies are

compared, and the most suitable of all topologies for low-noise performance is

determined. Subsequently, the optimal size and type of devices used in the

selected low-noise amplifier are determined. Finally, a brief overview of common

techniques used for noise reduction in charge amplifiers, including their tradeoffs, is

presented.

Chapter 5 begins with a theoretical discussion of the proposed zero-pole

transformation method. The chapter continues with a description of the

implementation of the amplifier with the zero-pole transformation method followed by

the noise analysis of a charge amplifier with zero-pole transformation. Subsequently,

the effect of parasitics on the performance of the amplifier is described. The chapter

concludes with a discussion on the trade-offs involved with the zero-pole

transformation technique.

Chapter 6 considers the issue of charge injection in a zero-pole transformation

amplifier. The chapter also includes a list of techniques that may be used to reduce

charge injection.

Chapter 7 describes an experimental prototype of the zero-pole transformation

amplifier that has been designed and implemented in 0.18µm CMOS technology. The

prototype amplifier also includes the correlated double sampling technique. Measured

performance results from the experimental chip are also presented.

Finally, chapter 8 conveys concluding remarks and suggestions for future

research.

Chapter 2

Noise in Electronic Circuits

The noise level in the output of a circuit determines the minimum signal detectable by

the circuit, as well as its dynamic range. Therefore, there is immense interest in

studying the sources of noise present in electronic systems and methods by which

noise can be reduced or eliminated. This chapter explores the various physical sources

of noise in electronic devices. Initially, the most prominent types of noise present in

low to moderate frequency electronic devices are described. Subsequently, analytical

expressions for noise sources present in MOSFET devices are presented. The chapter

concludes with a discussion on the effect of feedback on the noise performance of a

system.

2.1 Fundamental Noise Sources

Electrical noise refers to unwanted fluctuations that obscure or interfere with a desired

signal. Noise consists of frequency components which are random in both amplitude

and phase. Consequently, the exact value of noise can not be determined at any

specific point in time. Therefore the integrity and accuracy of a signal is reduced by

7

8 Chapter 2: Noise in Electronic Circuits

the presence of noise.

In many cases, multiple noise sources are present in a device or circuit. In that

case, the total noise is calculated as a sum of noise powers, or equivalently noise

voltages squared, such as

v nT2 =vn1

2 +vn22 +2C vn1 vn2 (2.1)

where v n12 and v n2

2 represent two noise sources present in the circuit and C is the

correlation factor between the two sources. If the noise mechanisms responsible for

the two noise sources are completely independent, then the two sources are

uncorrelated (C = 0).

There are three main types of noise in electronic circuits: thermal noise, flicker

noise and shot noise. These three types of noise are explained in detail in the next

section. Popcorn noise is another type of noise present in electronic circuits, which is

mostly present in some forms of bipolar transistors. Since bipolar transistors are not

used in the proposed charge amplifier, popcorn noise is not be considered in this work.

2.1.1 Thermal Noise

Thermal noise is a random voltage or current generated in a conductor by the thermal

agitation of its charge carriers. For the most part, thermal noise is “white”, meaning

that its power spectral density is constant as a function of frequency. Additionally,

thermal noise has a Gaussian probability density function. The power spectral density

of thermal noise is [2]

PTH = kBTΔf (2.2)

where kB is Boltzmann's constant, T is temperature and Δf is the frequency band of

2.1. Fundamental Noise Sources 9

interest. As expected, the power spectral density is proportional to the temperature.

The thermal noise voltage and current for a resistor can be found to be [2]

v n2=4k BTRΔ f (2.3)

in2=

4k BT Δ fR

(2.4)

2.1.2 Flicker Noise

Flicker noise is a type of noise that is present only when current is flowing through a

transistor. Flicker noise has a 1/f noise power spectrum [3], which is why it is

commonly referred to as 1/f noise or pink noise. The physical origins of flicker noise

are not well-understood, and theories developed on this matter vary quite a bit.

However, flicker noise is generally related to imperfections in material, such as traps

created at interfaces of different materials, impurities and grain boundaries. These

imperfections create energy states that can either trap a carrier or alter the movement

and mobility of charge carriers. In a general notation flicker noise can be expressed as

[2]

i f2 =KI βΔ f

f α (2.5)

where K is a proportionality constant specific to the processing technology. α and β

are both constants; α ranges from 0.5 to 2, and β is close to 1.


2.1.3 Shot Noise

Shot noise is present in transistors with a direct current flow because of the quantized

nature of charge. Shot noise occurs in devices in which a potential barrier exists, such

as diodes and transistors [3]. Shot noise becomes prevalent when the number of

carriers are low enough so that the individual charges have a notable impact on the

overall current. The analytical expression for shot noise is [3]

i sh2 =2qI DΔ f (2.6)

where, q is the electronic charge (1.6 x 10-19 C) and IDC represents the direct current

flowing through the device. As evident from Equation (2.6), shot noise is proportional

to the DC current. Also, shot noise exhibits a white power spectrum similar to thermal

noise.

2.2 Noise in MOSFET Devices

In the previous section, an overview of the most prominent types of noise present in

low and moderate frequency electronic circuits was presented. In this section,

analytical expressions are given for the main types of noise present in MOSFET

devices.

2.2.1 Thermal Noise In MOSFET Devices

The channel of MOSFET devices acts as a resistance and therefore exhibits thermal

noise. Since the channel resistance of a MOSFET is different in the two operating

regions of triode and saturation, the noise in each region must be dealt with separately.

2.2. Noise in MOSFET Devices 11

Analytical expressions for thermal noise in the saturation and triode regions are [4]

ith2 =8

3k BTgmΔ f saturation (2.7)

ith2 =4k BT γgdoΔ f triode (2.8)

respectively, where gdo is the channel's transconductance with zero drain-to-source

voltage. The value of the parameter γ varies between 1 and 2/3 for drain voltages from

zero to the onset of saturation.

It is often useful to think of noise in terms of a voltage source at the gate of the

MOSFET. The above noise currents may be referred to the input of the MOSFET as

noise voltages by dividing both sides of the equations by gm2, in which results in

v th2 =

8k BT Δ f3gm

saturation (2.9)

v th2 =

4k BT γgdoΔ fgm

2 triode (2.10)

From the above expressions for thermal noise in MOSFET devices, it is

evident that a high-transconductance transistor exhibits a large thermal noise

component in its drain current and little thermal noise voltage at its gate. In

optimizing transistor sizes, it is important to consider whether in the application of

interest the noise current or noise voltage should be minimized.


2.2.2 Flicker Noise in MOSFET Devices

When a transistor is in its on-state and a current flows between its source and drain,

flicker noise is also present. There are a number of different theories about the

physical source of flicker noise in MOSFET's. Studies have shown that possible

sources of flicker noise include traps at the Si-SiO2 interface [5], imperfections in

hetero-junctions [6] and crystal imperfections due to strain [7]. The flicker noise

current power can be modeled as [3]

i f2 =KI αΔ f

f b (2.11)

where K is a constant for a particular device, α is a constant in the range 0.5-2 and b is

a constant of about unity. Similarly, the flicker noise voltage power referred to the

input of the transistor can be written as [8]

v f2 = KΔ f

C oxWLf (2.12)

Equation (2.13) shows that in order to minimize flicker noise, devices must be large.

In addition, crystal defects must be minimized during device processing.

Flicker noise is often characterized by its corner frequency, fc, below which the

flicker noise increases substantially and above which thermal noise is dominant.

Studies have shown that the flicker noise in NMOSFETs is higher than in PMOSFETs

[9]. Researchers have not converged on an exact physical explanation for the

difference of flicker noise in PMOS devices compared to NMOS devices. One theory

explains the difference by suggesting that flicker noise is predominantly a surface

effect caused by traps in the semiconductor-oxide interface. The channel of NMOS

devices forms at the surface, whereas PMOS devices have a buried channel.

2.2. Noise in MOSFET Devices 13

Therefore, PMOS devices exhibit lower flicker noise than NMOS devices [10].

Another theory hypothesizes that a phenomenon called mobility fluctuation is

responsible for flicker noise [11]. From a circuit design point of view, the underlying

mechanism responsible for the difference in flicker noise between NMOS and PMOS

devices is not of much importance. The point to note is that PMOS devices exhibit

less flicker noise than NMOS devices and therefore should be used as the input

devices of amplifiers in cases where flicker noise is a problem.

2.2.3 Shot Noise In MOSFET Devices

As described earlier, shot noise is the result of discrete electrons carrying electric

current. The amount of shot noise is proportional to the current flowing through the

device. Additionally, this type of noise is observed where a potential barrier exists

such as in pn-junctions. The shot noise in a MOSFET is

i sh2 =2qI DΔ f (2.13)

where ID is the current flowing through the channel of the transistor. In RF

applications, the gate noise current can reach significant levels. However, gate shot

noise is usually not an important source of noise in low-frequency circuits.

In long-channel MOSFETs, the shot noise generated by the drain current is

usually negligible compared to the thermal and flicker noise present in these devices.

However, studies have shown that shot noise may be significant in submicron

transistors [12], [13]. In short-channel devices, the charge carriers have very little

distance to travel through the channel and therefore are not able to reach thermal

equilibrium. Consequently, the thermal noise of short-channel is less than in longer

channel devices [12]. Shot noise originates at the source of a MOS transistor and is

believed to be a result of diffusion current at the source [13].


2.3 Effect of Feedback on Noise

Feedback is widely used in analog circuit design, and thus its influence on noise merits

attention in this dissertation. Feedback is used extensively in circuit design in order to

reduce the influence of component nonlinearity, as well as variations that arise owing

to process variations [2]. For example, charge amplifiers, also known as charge

integrators, almost always employ feedback. Therefore, it is important to have a clear

understanding of how feedback effects the noise level in the output of such circuits.

Since the signal-to-noise ratio is the measure of noise that we are primarily concerned

with, we consider the effect of feedback on the signal-to-noise ratio of a circuit.

Let us assume that a circuit, block A, shown in Figure 2.1(a), has a gain of a

and an input-referred noise value of N. Therefore, for an input signal, In, the output is

Out = aIn + aN (2.14)

Accordingly, the ratio of the output signal, S, to noise is

SN

=aInaN

=InN (2.15)

Now let's assume that the noise-less block with a gain f, is connected in feedback with

block A, as shown in Figure 2.1(b). Assuming a is large, the total gain, G, is [2]

G= a1+af

≈ 1f (2.16)

The output value of the system and the signal-to-noise ratio may be calculated

Out= 1f

In+ 1f

N (2.17)

2.4. Summary 15

Figure 2.1: (a) Noisy amplifier block, (b) Feedback-connect noisy amplifier

Finally, signal-to-noise ratio of the feedback system may be calculated

SN

=(1/ f ) In(1/ f )N

= InN (2.18)

Thus, the feedback has had no effect on the signal-to-noise ratio of the system.

2.4 Summary

In this chapter, the three main types of noise in MOS devices were presented: thermal,

flicker and shot noise. Thermal noise depends on temperature and the impedance of

devices. Flicker noise is a process-dependent phenomenon and can be reduced by

using large widths and lengths for MOSFETs. Shot noise is not as prominent as a

noise source as thermal and flicker noise are in MOS devices and is a result of the

discreteness of the transport of charge. Finally, it was shown that a feedback network

essentially has no effect on the noise level of a circuit, other than the noise that its own

components may introduce.

In Outa

Block A

In Outa

Block A

f

(a) (b)

Chapter 3

The Charge Amplifier

The charge amplifier is a key component of many electronic systems with applications

in gamma and X-ray imaging, nuclear physics, aerospace, particle physics, medical

and nuclear electronics, portable instrumentation, optical systems, electro-mechanical

systems and memory devices. A charge amplifier typically serves as the interface

between an input signal charge and the subsequent processing of that signal in the

voltage domain. This chapter begins with a description of the basic architecture and

operation of a charge amplifier. The performance metrics are also introduced.

Subsequently, a discussion on the noise behavior of the charge amplifier is presented.

Finally, a number of applications in which charge amplifiers are used are described.

3.1 Principle of Operation

A charge amplifier, when implemented as a current integrator, integrates a pulse of

current and produces an output voltage proportional to the integrated charge. Thus, it

functions as a charge-to-voltage converter. Typically, a charge amplifier has a large

input impedance and a low output impedance.

17

18 Chapter 3: The Charge Amplifier

Figure 3.1: Schematic diagram of a basic charge amplifier

Figure 3.1 shows the schematic diagram of a basic charge amplifier when

implemented as an operational amplifier with a capacitance connected in a negative

feedback configuration. Cf is the feedback capacitance, while Cin is the input

capacitance to ground. The input capacitance is composed of the input capacitance of

the amplifier as well as the capacitance of any device connected to the input as the

source of the input current signal, such as a photo-diode. In this example, the input is

a current pulse, Iin, and the output is a voltage, Vout.

The transfer function of a charge amplifier is a relationship between the output

voltage Vout and the input current Iin or the input charge. It can be established easily

using Kirchhoff's current law and the capacitor current-voltage relationship.

If it is assumed that the amplifier has a large input impedance, and therefore no

current flows into its negative input, then

Iin = ICin + ICf (3.1)

A

_

+

Cf

Vin

Vout

Iin

Cin

3.1. Principle of Operation 19

where ICin is the current flowing through the Cin, while ICf is the current flowing into

the feedback capacitance Cf. Using the capacitor current-voltage relationship, it

follows that

I in=C in

dV Cin

dt+C f

dV Cf

dt

= C in

dV in

dt+C f

d (dV in−dV out )dt

(3.2)

Next assume that the gain of the amplifier, A, is infinite. In that case, the

voltage at the two input nodes of the amplifier must be the same, and it follows that

I in=−C f

dV out

dt (3.3)

or equivalently,

dV out

dt=

−I in

C f . (3.4)

When Equation (3.4) is integrated over time, then

V out=−Qin

C f (3.5)


where Qin is the total input charge. Thus, if the gain, A, and the input impedance of the

op amp are sufficiently large, then the charge amplifier converts the input charge to an

output voltage with a proportionality constant of 1/Cf. ��勘Ћ汌��ǐ��%�凸Ћ汬�t勘Ћ汸��厸Ћ沄��厸Ћ沐��厸Ћ沜��剨Ћ沨�s剨Ћ沴�a剨Ћ泀�-剨Ћ泌�i剨Ћ泘�h剨Ћ泤�nقʋ泰䎔قʋ泼䍜قʋ洈䌤剨Ћ洔�y剨Ћ洠�u剨Ћ洬�fقʋ洸횬瑑قʋ浄횬瑑قʋ浐횬瑑厸Ћ浜�䅀厸Ћ浨�䅀厸Ћ浴�䄠跠Ќ赼ti剨Ћ涌d 剨Ћ涘de剨Ћ涤de剨Ћ涰�e凸Ћ涼�h剨Ћ淈�e剨Ћ淔�e剨Ћ淠�f凸Ћ淬�e剨Ћ淸�8 1/Cf.

3.2 Reset Mechanisms

In a charge amplifier such as that depicted in Figure 3.1, a mechanism must be in place

for resetting the charge collected on the integrating capacitor. There are two types of

charge that accumulate on this capacitor: signal charge and leakage charge. These

charges must be cleared away; in other words the charge amplifier must be reset. The

signal charge must be cleared away so that a new signal charge can be measured.

Leakage charge must be removed in order to prevent saturation of the charge amplifier.

The main sources of leakage charge is leakage through the feedback network, gate

leakage current of the input transistor and leakage charge from the sensor connected to

the charge amplifier. The reset of the charge amplifier may be performed with a pulsed

method or a continuous method. Additionally, the continuous reset method may be

performed in a constant-current or current-adaptive fashion. The reset operation is

also often used as a means of biasing the input FET of the amplifier. In this section,

the various methods of charge amplifier reset are described along with their tradeoffs.

3.2.1 Pulsed Reset

In the pulsed reset method, the input of the charge amplifier is cleared by shorting the

input of the charge amplifier to its output for a short period of time. The reset pulse is

activated after the output of the charge amplifier is sent to the ADC and the charge

amplifier is being prepared to receive the next input signal. Figure 3.2 shows a charge

amplifier using pulsed reset. The input and output are shorted using a simple

MOSFET. During reset, the reset pulse is high, the transistor is on and the input and

3.2. Reset Mechanisms 21

Figure 3.2: Pulsed reset method in charge amplifiers

output are connected. Subsequently, the reset pulse goes low, thus disconnecting the

input and output. The charge amplifier is now available for current integration. The

off resistance of the reset transistor is usually large enough to not alter the original

transfer function of the charge amplifier.

There are a number of tradeoffs involved in the pulsed reset method, which

need to be considered in the context of the specific application. One drawback of the

pulsed reset method is the reset dead time; in other words the unavailability of the

charge amplifier for signal reception during reset. While the reset signal is high and

the input and output are connected, the charge amplifier is not able to integrate current,

and it will sink away any current flowing into its input. Depending on the type of

input device, input signal strength and charge amplifier design, the dead time could

vary from a few tens of nano-seconds to a few hundred micro-seconds [14], [15], [16].

The dead time of the pulsed reset method is not a limiting factor when the input signal

A

_

+

Cf

Vin

Vout

Iin

Cin

MR

Reset


is received as individual pulses.

Another drawback of the pulsed reset method is that the leakage current is not

compensated for. This leakage current is treated the same as the input current and is

converted to voltage error at the output. If the integration period is long, or the

leakage current is high, then the charge amplifier may saturate, which would prevent

the linear conversion of the input charge to an output voltage.

Finally, in designing a charge amplifier using the pulsed reset method the

reset noise must be considered. The reset noise is the result of thermal noise in the

reset switch [17]. Often the reset noise may be significantly reduced using correlated

double sampling [17], [18], [19].

3.2.2 Continuous Reset

In the continuous reset method, a small amount of current is constantly drained from

the input of the charge amplifier. This small reset current, which amounts to an

integrator leak, is designed to compensate for leakage current and also drain away any

input signal current slowly. The schematic of a charge amplifier using basic

continuous reset is shown in Figure 3.3. Rf is the feedback resistance that provides a

current path for the reset. The amount of feedback current is determined by the value

of Rf. The feedback current is usually designed such that it will compensate for the

leakage current of the input device and allow for a slow discharge of the input signal.

The time constant of the input signal discharge is given by τ = RfCf.

Assuming that an input device produces constant charge over a time interval

from t = 0 to to, then the input charge may be described in the Laplace transform

domain as [20]

Q(s)=Qs(1s− e−sto

s) (3.10)

3.2. Reset Mechanisms 23

Figure 3.3: Continuous reset method through a feedback resistor

where Qs is the total charge injected onto the input between t = 0 and t = to . Similarly,

the Laplace transform of the transfer function of the charge amplifier is given by [20]

T (s)=−1

C f

1s+1/ τ (3.11)

Finally, the expression for the output voltage is

V (s )=Q(s)T (s )=−Q s(1s−

e−sto

s)(

1C f

. 1s+1/ τ

) (3.12)

A

_

+

Cf

Vin

Vout

Iin

Cin

Rf


Furthermore, assuming to << τ, equation (3.12) may be simplified as

V out (t)=−Q s

C f

(1−e t / τ)t o/ τ

0 < t < to (3.13)

V out (t)=−Q s

C fet / τ t > to (3.14)

Equations (3.13) and (3.14) state that input charge Qs is converted to a voltage with

magnitude 1/Cf. ��勘Ћ汌��ǐ��%�凸Ћ汬�t勘Ћ汸��厸Ћ沄��厸Ћ沐��厸Ћ沜��剨Ћ沨�s剨Ћ沴�a剨Ћ泀�-剨Ћ泌�i剨Ћ泘�h剨Ћ泤�nقʋ泰䎔قʋ泼䍜قʋ洈䌤剨Ћ洔�y剨Ћ洠�u剨Ћ洬�fقʋ洸횬瑑قʋ浄횬瑑قʋ浐횬瑑厸Ћ浜�䅀厸Ћ浨�䅀厸Ћ浴�䄠跠Ќ赼ti剨Ћ涌d 剨Ћ涘de剨Ћ涤de剨Ћ涰�e凸Ћ涼�h剨Ћ淈�e剨Ћ淔�e剨Ћ淠�f凸Ћ淬�e剨Ћ淸�F 1/Cf. ��勘Ћ汌��ǐ��%�凸Ћ汬�t勘Ћ汸��厸Ћ沄��厸Ћ沐��厸Ћ沜��剨Ћ沨�s剨Ћ沴�a剨Ћ泀�-剨Ћ泌�i剨Ћ泘�h剨Ћ泤�nقʋ泰䎔قʋ泼䍜قʋ洈䌤剨Ћ洔�y剨Ћ洠�u剨Ћ洬�fقʋ洸횬瑑قʋ浄횬瑑قʋ浐횬瑑厸Ћ浜�䅀厸Ћ浨�䅀厸Ћ浴�䄠跠Ќ赼ti剨Ћ涌d 剨Ћ涘de剨Ћ涤de剨Ћ涰�e凸Ћ涼�h剨Ћ淈�e剨Ћ淔�e剨Ћ淠�f凸Ћ淬�e剨Ћ淸� Qs/Cf at the output of the amplifier and has a time constant τ.

The continuous reset method is appropriate in applications where leakage

current is high, and therefore a constant reset current is needed to prevent saturation of

the charge amplifier.

In the continuous reset method, the noise of the feedback resistor must be

accounted for. The reset resistor, Rf, contributes current noise into the input of the

charge amplifier. Therefore, Rf must be large enough to prevent degrading the input

sensitivity of the amplifier.

Transistors are commonly used to implement the feedback resistance. Such a

transistor can be biased into its sub-threshold regime to achieve a larger resistance

[21], or biased into its saturation region with a small W/L ratio [22]. The drawback of

using transistors as the reset resistor is that the resistance will vary greatly over process

corners and temperature and therefore must be calibrated.

There are a number of variations in the architecture of the basic continuous

reset method that prevent saturation of the amplifier and adjust for variable leakage

current [23], [24], [25], [26].

3.3. Performance Metrics 25

3.3 Performance Metrics

The charge amplifiers that are the subject of this thesis are current integrators that

convert charge to voltage. A charge amplifier is typically used as the interface between

a current signal source, such as a photo-diode or some form of sensor, and subsequent

signal processing and/or digitization.

There are a number of characteristics that are typically desirable in the

operation of a charge amplifier: high gain, low noise, high integration linearity, fast

rise time, low power, compact and high temperature stability. Generally, there are

trade-offs involved among these characteristics. Therefore, during the design of the

charge amplifier, the specific requirements of the intended application must be

considered. The performance metrics and some of their trade-offs are reviewed in this

section.

Gain

It is desirable to amplify the input charge as much as possible in the first stage of a

detector system in order to minimize the influence of noise introduced by subsequent

stages in the signal path. As shown in Equation (3.9), the gain of the charge amplifier

is 1/Cf. ��勘Ћ汌��ǐ��%�凸Ћ汬�t勘Ћ汸��厸Ћ沄��厸Ћ沐��厸Ћ沜��剨Ћ沨�s剨Ћ沴�a剨Ћ泀�-剨Ћ泌�i剨Ћ泘�h剨Ћ泤�nقʋ泰䎔قʋ泼䍜قʋ洈䌤剨Ћ洔�y剨Ћ洠�u剨Ћ洬�fقʋ洸횬瑑قʋ浄횬瑑قʋ浐횬瑑厸Ћ浜�䅀厸Ћ浨�䅀厸Ћ浴�䄠跠Ќ赼ti剨Ћ涌d 剨Ћ涘de剨Ћ涤de剨Ћ涰�e凸Ћ涼�h剨Ћ淈�e剨Ћ淔�e剨Ћ淠�f凸Ћ淬�e剨Ћ淸� F 1/Cf. ��勘Ћ汌��ǐ��%�凸Ћ汬�t勘Ћ汸��厸Ћ沄��厸Ћ沐��厸Ћ沜��剨Ћ沨�s剨Ћ沴�a剨Ћ泀�-剨Ћ泌�i剨Ћ泘�h剨Ћ泤�nقʋ泰䎔قʋ泼䍜قʋ洈䌤剨Ћ洔�y剨Ћ洠�u剨Ћ洬�fقʋ洸횬瑑قʋ浄횬瑑قʋ浐횬瑑厸Ћ浜�䅀厸Ћ浨�䅀厸Ћ浴�䄠跠Ќ赼ti剨Ћ涌d 剨Ћ涘de剨Ћ涤de剨Ћ涰�e凸Ћ涼�h剨Ћ淈�e剨Ћ淔�e剨Ћ淠�f凸Ћ淬�e剨Ћ淸� 1/Cf. Thus, a high-gain charge amplifier requires a low Cf. The minimum

capacitance value that can be used in the charge amplifier is dictated by the process

used to fabricate the amplifier.

In choosing a value for Cf, it is important to consider the expected magnitude of

the input charge. However, for large inputs the charge amplifier may saturate if its

gain is too large. Thus, the value of Cf should be chosen such that the maximum input

charge does not drive the charge amplifier into non-linear gain regions.


Noise

The noise of a charge amplifier is what limits the sensitivity of the system. The

minimum detectable signal is determined by the maximum input-referred noise. If the

charge amplifier gain is sufficiently high, then the noise of subsequent stages does not

influence the input-referred noise significantly. Thus, it is imperative that substantial

consideration be given to reducing the noise introduced by the amplifier.

Noise reduction methods typically delay the output signal or introduce periods

of time during which the charge amplifier is not usable. For example, correlated

double sampling (CDS) [27], requires the system to take two samples for each input.

The first sample is taken after the output of the charge amplifier settles subsequent to

the pulsed reset. Integration can not begin until the first CDS sample has been taken.

Thus, the impact of noise reduction methods on other performance metrics must be

considered in the design of a charge amplifier.

The noise level of a detector system may be limited by size restrictions on the

charge amplifier. As noted in Chapter 2, the flicker noise of a transistor is inversely

proportional to its size. Therefore, if there are limitations on the area available to

implement a charge amplifier, then the noise performance of the amplifier may suffer.

Rise TimeThe rise time of the output of a charge amplifier affects the operating frequency of a

detector system. In a charge amplifier, the rise time is determined by the amount of

DC current in the amplifier, as well as the capacitance loading at the output of the

amplifier.

There can be a trade-off between rise time and noise, depending on the noise

reduction method used. For example, as discussed in Chapter 7, the zero-pole

transformation noise reduction method increases the rise time of the output of the

charge amplifier.

3.3. Performance Metrics 27

Power

The maximum power budget of a charge amplifier is typically limited in wireless

applications such as heat and humidity sensors, motion sensors in navigation systems

and other portable electronic detector systems. As mentioned earlier, there are trade-

offs involved in designing for low power while achieving adequate noise and linearity

performance.

High power consumption can increase the temperature of the charge amplifier,

which can lead to increased thermal noise. Additionally, the leakage current of input

transistors tends to increase at higher temperatures.

Area

Some applications have a limitation on how much area an integrated charge amplifier

can occupy. For example, in applications where the readout circuit is directly bonded

on top of the pixel array, the individual circuitry for each pixel may need to fit within

the same area as the pixel itself.

As mentioned previously, there are trade-offs between the area of a charge

amplifier and its noise performance and gain performance. Additionally, in designing

a charge amplifier the size of any additional circuitry, such as the zero-pole

transformation scheme or correlated double sampling, must be considered.

Temperature Stability

The temperature of a charge amplifier may vary due to environmental temperature

changes or its power dissipation. For instance, many types of sensors, such as

thermostats, humidity and motion sensors, are used over a wide range of temperatures

(e.g. 0ºC -100ºC). Therefore, it is often important for the charge amplifier to maintain

its performance levels throughout a specified temperature range.


3.4 Noise

The noise level exhibited by a charge amplifier is an important performance metric

that determines the minimum signal that can be processed by the system. In this

section, the noise of the basic charge amplifier is analyzed in order to provide insight

on how to design low noise charge amplifiers.

The input transistor of the amplifier is usually the dominant source of noise in

a charge amplifier. Therefore, in this derivation, only the noise from the input device

is considered. The input MOSFET exhibits both thermal noise and flicker noise.

These two sources of noise are referred to the gate of the transistor as an equivalent

input noise voltage, as shown in Figure 3.4. From Equations (2.9) and (2.12), it

follows that

v th2 =

8K BT Δ f3g m

Thermal Noise (3.16)

and

v f2 = KΔ f

C oxWLf Flicker Noise (3.17)

The equivalent total input voltage is then

v ineq2 =v f

2 +v th2

(3.18)

3.4. Noise 29

Figure 3.4: Noise analysis of the charge amplifier

and equivalent output noise voltage is given by [28]

v outeq2 =vneq

2 .(C f +C in)

2

C f2

(3.19)

From Equation (3.19) it is apparent that the input capacitance has a significant

impact on the amount of noise voltage seen at the output of the charge amplifier. The

input capacitance is composed of the gate capacitance of the input MOSFET, Cg, and

A

_

+

Cf

Vout

Iin

Cin

vineq2

____


the capacitance of the input source, Cd. Equation (3.19) can be expanded to

v outeq2 =[

8K BTΔ f3g m

+ KΔ fC oxWLf

](C f +C g+C d)

2

C f2 (3.20)

Equation (3.20) clearly shows that Cd must be minimized for low noise

performance. Other than choosing a low-capacitance input current generator, the

capacitance of any connectors between the input device (i.e. diode, sensor, etc. ) and

the charge amplifier must be minimized. Common techniques for reducing

interconnect capacitance are directly bump-bonding the input device to the charge

amplifier or embedding the input device into the CMOS fabrication of the charge

amplifier.

The size of the input transistor must be carefully chosen in order to reduce

noise. As shown in Equation (3.20), flicker noise has an inverse dependence on the

size of the input transistor. Additionally, the thermal noise is inversely proportional to

the transconductance of the input transistor, which itself is proportional to the

width/length ratio of the channel of the transistor. Therefore, the equivalent input

noise voltage is inversely proportional to the transistor size. Furthermore, the output

noise voltage is proportional to Cg, and therefore proportional to the input transistor

size. An optimum transistor width thus exists for which the noise is minimized. This

topic is discussed further in Chapter 4.

3.5 Applications

Charge amplifiers are used in a variety of applications ranging from medical imaging

and particle physics to micro-electrical-mechanical systems. A number of

applications, along with their specific requirements for the charge amplifier are

described in this section.

3.5. Applications 31

3.5.1 X-ray Imaging

X-ray imaging is a mature field that has applications in many areas. In x-ray imaging,

an x-ray is directed towards a detector that converts the energy of the x-ray into an

electrical signal. A common type of detector used in x-ray imaging is a semiconductor

diode, in which an x-ray generates electron-hole pairs. The electron s and holes are

swept in opposite directions when the diode is reverse-biased, thereby creating current.

Subsequently, the current is integrated in a charge amplifier, and the output of the

charge amplifier is then digitized for further processing. The application of x-ray

imaging in crystallography, astronomy and x-ray fluorescence analysis material is

described below.

3.5.1.1 Crystallography

In crystallography the lattice structure of a crystal is determined using x-ray imaging.

A beam of x-rays is directed towards the crystal, which diffracts the x-ray in different

directions with varying intensities. By examining the direction and energy level of

the diffracted x-rays, the lattice structure of the crystal can be determined.

Crystallography is used, for example, to observe the behavior of proteins in

developing drugs.

The wavelength of the X-rays used in crystallography is on the order of

atomic dimensions ~ 0.1nm, which corresponds to a wave with an energy level of

12keV. The diffracted beams are examined by the means of a large pixel array

detector. Each pixel is composed of a detector diode, charge amplifier and, possibly,

other possible conditioning circuits. The array must be large enough to capture all of

the diffracted beams. In addition, each pixel must be small enough to provide

adequate resolution. Such detector systems usually require an area of ~ 20cm × 20cm,

a readout time of < 1s and a dynamic range of ~ 106 [29].


3.5.1.2 X-Ray Fluorescence Analysis (XRF)

X-ray fluorescence analysis uses x-rays to determine the composition of substance. A

low energy x-ray is emitted from a substance after it has been bombarded by a high

energy x-ray. The energy level of the emitted x-ray is specific to each substance, and

therefore can be used to identify its composition. Currently, not all substances may be

identified with XRF due to limitations of the current electronics. Substances that emit

very low x-rays require extremely low-noise detector systems for identification.

Therefore, there is interest in developing ultra low noise detector systems for use in

XRF applications.

An interesting application of XRF in medicine is determining the amount of

long-term lead exposure. The long-term exposure to lead can be studied by analyzing

the amount of lead in bone structures of the body. In this application, a beam of x-rays

is directed towards the bone, and subsequently the energy of the emitted x-rays is

measured. Analysis of the emitted x-rays reveals the amount of lead present in the

bone. These types of detector systems typically are about few hundred mm2 in area

and use x-rays with energies between 13keV-85keV [30].

3.5.1.3 X-ray Astronomy

X-ray astronomy is a branch of astronomy that observes the x-ray emission from

celestial objects. X-rays are emitted from extremely hot gaseous sources, such as

black holes and stars. Since, the earth's atmosphere absorbs most of the x-rays passing

through it, the astronomical x-ray detectors are placed on satellites above the

atmosphere. The energy of x-rays received in astronomical applications ranges from a

few keV to 100keV [31].

X-ray detectors can be used to observe transient phenomena in space, solar

fares, isolated and binary pulsars and active galactic nuclei (AGC) [32]. Similar


systems can be designed to monitor gamma-ray bursts in space.

3.5.2 Particle Physics

In particle physics, the study of high-energy particles has been enabled by advances in

detector electronics. The behavior of charge particles are studied using an accelerator.

Charged particles are accelerated to high speeds in opposite directions until they

collide. Upon collision, high-energy particles are created that are the subject of study

for particle physicists. By studying the mass and energy of the newly created

particles, scientists are able to learn about the nature and fundamental characteristics

of matter.

The mass of the created particles is determined through time-of-flight mass

spectrometry (TOFMS). In TOFMS, a charged particle moves in an electric field and

therefore has a non-zero velocity. Using the values measured for the kinetic energy

and velocity of the charged particle, the mass of the particle can be calculated. The

velocity is measured as the time it takes a particle to move from the point of creation

to a system that detects its arrival.

The detector is typically composed of an array of diodes connected to charge

amplifiers. Upon the incidence of a charged particle onto a detector diode, current is

generated and transferred to the charge amplifier. In these experiments detector

systems are used to cover very large areas up to 1.7m2. There are currently four major

colliders available for particle physics studies: ATLAS, CMS, ALICE and BTev. The

energy of the charged particles incident on the detectors is on the order of a few tens

of keV [33].

3.5.3 Optical Systems

A broad range of optical systems including digital cameras, camcorders, surveillance


motion detectors, digital scanners, copiers, fax machines and medical electronics such

as retinal cameras and radiography systems utilize charge amplifiers in their systems.

A typical optical system is composed of a photo-sensor followed by a charge amplifier

and digitizing electronics.

There are two basic types of photo-sensors in widespread use: charge-coupled

devices (CCD) and CMOS active-pixel sensors. Both types are used extensively in

optical products. They both convert illumination into an electrical current that is sent

to a charge amplifier for conversion to voltage and amplification.

Cameras that capture single still images, such as digital cameras, have lenient

requirements on the speed of signal acquisition and processing. However, electronic

systems such as camcorders and scanners require high-speed electronics in order to

capture as many images as possible in a given time period. Video-recording devices

capture images at rates as high as a few MHz. In such a system, each image must be

acquired, processed and the front-end electronics reset in less than 1µs [34]. Therefore,

in these systems, continuous reset is not often used, since the reset of an incoming

signal occurs over a long period of time.

Another application of charge amplifiers in is their use in motion surveillance

cameras. These devices detect the motion of an object by taking consecutive images

and detecting changes in the images. Such motion detectors are composed of a sensor,

charge amplifier and an analog subtractor. The sensor sends charge to the charge

amplifier after the first image is received. The charge is converted to voltage and its

value stored on a capacitor. Subsequently, the charge for the second image is received

and is converted to voltage. The second image is then subtracted from the first image

which has been stored. Depending on the the result of the subtraction, the surveillance

system determines whether or not an object has moved in front of the motion sensor

[35].


3.5.4 Medical ElectronicsAs discussed in previous sections, a large number of applications exists for charge

amplifiers in medical electronics, such as x-ray imaging, retinal cameras, radiography

and ultra-sonography . Most medical electronic devices that use charge or current

producing sensors utilize charge amplifiers in their systems. For example, a

calorimeter is a device that measures the heat produced during a chemical reaction.

Heat sensors are embedded in calorimeters and produce charge proportional to the

ambient temperature. Subsequently, the charge is sent to a charge amplifier for further

processing [36].

Innovative ballistocardiogram (BCG) devices, which are used to assess

cardiovascular function, also include charge amplifiers. BCG devices utilize

electromechanical film sensors (EMFi sensors), which produce charge in response to

pressure. These sensors are installed in chairs resembling office chairs, and the BCG

data is taken while the patient is seated on the chair. The purpose of this type of

cardiovascular activity evaluation is twofold. One is to provide a non-invasive method

of evaluating the vital signs of a patient. Additionally, it is known that the heart rates

of patients often increase during a physical examination. A BCG device has the

benefit of eliminating patient anxiety during examination. BCG devices typically

operate at frequencies of less than 100Hz [37].

3.5.5 Micro-Electro-Mechanical Systems (MEMS)

MEMS devices include a wide range of systems with applications in a a variety of

fields. Almost all MEMS sensors are used in conjunction with charge amplifiers.

Such sensory systems include gyroscopes, pressure sensors, accelerometers, bio and

chemo-sensors.

A common type of pressure sensor is constructed using piezoelectric

materials. These sensors contain a special type of material that generates charge in the

presence of mechanical pressure. A charge amplifier is used to examine the impulses


received through pressure change. MEMS pressure sensors are commonly utilized in

micro-fluidic applications [38].

Accelerometers are used in a variety of applications, such as airbag

deployment in cars, game controllers, personal media players, cellphones, and some

PCs for detection of free-fall. Accelerometers typically detect acceleration through

capacitive changes in the MEMS structure. The variation in capacitance is measured

using a charge amplifier [39].

3.6 Summary

In this chapter, the operation of a basic charge amplifier topology is described. A

charge amplifier is essentially a charge-to-voltage converter with a gain of 1/Cf. There are two reset methods commonly used: pulsed and continuous. Pulsed reset has the benefit of clearing the input often. However, there is addition L 1/Cf. There are two reset methods commonly used: pulsed and continuous. Pulsed reset has the benefit of clearing the input often. However, there is addition 1/Cf.

There are two reset methods commonly used: pulsed and continuous. Pulsed reset has

the benefit of clearing the input often. However, there is additional reset noise

introduced by the reset process. In continuous reset, the leakage is continuously

compensated. However, if the value of the feedback resistor is too small, then the

feedback resistor would contribute high noise current to the charge amplifier.

The main performance metrics for charge amplifiers are gain, noise,

integration linearity, rise time, power, area and temperature sensitivity. Typically,

there are tradeoffs involved in optimizing these performance metrics that are

application specific.

The main source of noise in charge amplifiers is the input MOSFET of the

basic amplifier. Thus, care must be taken to ensure adequately low noise is

contributed by the input device. Additionally, the output noise voltage is proportional

to the total capacitance seen at the input of the charge amplifier, which includes the

gate capacitance of the input MOSFET, feedback capacitance and the capacitance of

the current generating input device.

Charge amplifiers are used in most applications that employ a current-

producing sensor. The output current of the sensor is integrated in the charge

3.6. Summary 37

amplifier and converted to a voltage. In addition, sensors that are based on

capacitance variation may use charge amplifiers to detect the change in capacitance.

.

Chapter 4

Low-Noise Charge Amplifier Design

This chapter describes a step-by-step approach to the design of low-noise charge

amplifiers. As described earlier, the charge amplifier is essentially an operational

amplifier with a capacitor connected in feedback between its input and output.

Therefore, the voltage amplifier is the essential design piece of the charge amplifier.

Accordingly, this chapter focuses on the design of the voltage or open-loop amplifier,

and from here on would simply be referred to as the “amplifier”. As discussed in

Chapter 3, the amplifier must have the following characteristics: high open-loop gain,

low output noise, high speed, high linearity, low power and low area. In this chapter,

initially, the top-level architecture of the amplifier will be considered. Subsequently,

various open-loop amplifier topologies are analyzed and compared for use in charge

amplifiers. Next, specific details about choice of transistor sizing are presented.

Finally, a number of commonly used add-on methods for noise reduction are

introduced.

39

40 Chapter 4: Low-Noise Charge Amplifier Design

4.1 Amplification Stages

As explained in Chapter 3, the open-loop gain of the operational amplifier must be

large. One approach to achieve high gain is to cascade several amplifier stages.

However, since the amplifier is used in a feedback configuration, it would be

challenging to ensure stability in a multi-stage design. Using more than two stages in

feedback necessitates complex compensation of the amplifier in order to ensure

stability. Hence, the number of amplification stages is best limited to no more than

two.

Two stages of amplification can provide significantly higher gain than one

stage but some means of frequency compensation is required. However, ensuring

stability in a two-stage amplifier is usually a manageable task. In addition, the overall

open loop gain of the two-stage amplifier must be inverting, as depicted in Figure 4.1.

The most common method of compensation in a two-stage amplifier uses the

Miller effect in order to create a dominant pole [3]. In this case, the second stage of

the amplifier must be inverting, as shown in Figure 4.2. Also, to use a single

compensation capacitor the first stage of the op amp must provide differential-to-

single ended conversion, as shown in Figure 4.2.

In detector applications, the input source for a charge amplifier is typically

single-ended. The amplifier may be implemented with a differential input stage that

compares the input to a reference level. However, while providing immunity to

coupling and supply noise, fully differential amplifiers exhibit twice the output noise

power of single-ended amplifiers [3]. Therefore, in the design of the amplifier, the

dominant source of signal degradation must be determined. Differential amplifiers are

best suited for systems which suffer mostly from coupling and supply noise. Single-

ended amplifiers should be used in systems which are dominated by amplifier noise.

4.2. Single-Stage Amplifier Topology 41

(a) (b)

Figure 4.1: Two-stage amplifier configurations

Figure 4.2: Frequency compensation of the two-stage amplifier

4.2 Single-Stage Amplifier Topology

For the purposes of this thesis, we assume that the dominant source of signal

degradation is amplifier noise. Therefore, the focus is on the design of a single-ended

amplifier. In this section, a number of common topologies for single-ended amplifier

stages are analyzed for use in a charge amplifier. The objective is an amplifier

topology that provides high gain, high linearity, large output swing and low noise.

A

Cf

AI

inV

out

Cf

AI

inV

out

A

A

Cf

-A

Iin

Vout

Cf

Ccomp


4.2.1 Common-Source Amplifier

Shown in Figure 4.3 are the schematics of two examples of a common-source

amplifier, one with a resistor load and one with a PMOS transistor load. The gain of a

common-source amplifier is

A=gm .(R load∥ro) (4.1)

where gm is the transconductance of the input MOSFET and ro is the output resistance

of the input MOSFET. Rload is the resistance of the amplifier load. In the case where

the load is a MOSFET, such as the amplifier in Figure 4.3(b), Rload is the small-signal

output resistance of the MOSFET.

The gain of an amplifier such as that shown in Figure 4.3(b) is generally much

larger than that of Figure 4.3(a) due to the inherently large output resistance of a

MOSFET biased in saturation. The use of a comparable real resistor would not be

practical due to its large area. Also, a large voltage would be dropped across the

resistor, limiting the output swing of the amplifier. However, a resistor exhibits less

noise than a MOSFET. It only contributes thermal noise to the circuit, whereas a

MOSFET contributes both thermal noise and flicker noise. In practice, resistor loads

are not used because of the limited gain and output swing.

4.2.2 Cascode Amplifier

The maximum gain that one may achieve from a common source amplifier may not be

sufficient for use as a single-stage amplifier. As shown in Equation (4.1), the gain

depends on the transconductance of the input transistor and the output resistance of the

amplifier. The maximum transconductance of a MOSFET is limited by its current

4.2. Single-Stage Amplifier Topology 43

(a) (b)

Figure 4.3: Common-source amplifier configurations with (a) resistor load, (b) transistor load

and processing technology. The output resistance of an amplifier could be increased

by cascoding the MOSFETs. A cascode of MOSFETs comprises a common-source

amplifier followed by a common-gate MOSFET. A simple cascode amplifier is shown

in Figure 4.4.

A common-gate transistor in series with the common-source transistor

effectively increases the resistance seen at the output of the amplifier. The output

resistances looking up and down at the output of the cascode amplifier are

approximately

Rload=gm4 r o4 ro3 (4.2)

Ramp=gm2 ro2 r o1 (4.3)

Rload

Vout

Vin

Vout

Vin

Vbias


Figure 4.4: Cascode amplifier with cascode load

The output resistances of the input and load transistors (M1 and M3) are thus

amplified by the intrinsic gains of the common-gate MOSFETs. A cascode amplifier

is usually able to provide sufficiently high gain for use as a single-stage amplifier.

Next, consider the noise behavior of the cascode amplifier. In this noise

analysis, the thermal and flicker noise contributions of each transistor are combined

into an equivalent noise voltage source at its gate. Each MOSFET contributes current

noise to the output of the amplifier. The output noise current is approximated [43]

inout2 ≈gm1

2 vn12 +gm3

2 vn32 (4.4)

where vn1 and vn3 and are the input-referred noise voltages of the transistors M1 and

M3, respectively. Similarly, gm1 and gm3 are the transconductances of M1 and M3,

Vout

Vin

VBIAS2

VBIAS4

VBIAS3

Rload

Ramp

M1

M2

M3

M4

4.4. Transistor Sizing 45

respectively. The cascode transistors, M2 and M4, have small effective

transconductance due to source degeneration and thus, typically do not contribute

significant noise to the output [43].

4.2.3 Folded Cascode AmplifierA folded cascode amplifier is essentially a cascode amplifier in which the current in

the common-source transistor is reversed back to its originating source [3]. A folded

cascode amplifier with a cascoded current source is shown in Figure 4.5. The folded

cascode amplifier is used to shift the level of the output. This amplifier is useful in

charge amplifiers in which the bias of the input transistor is set by shorting its gate

node to the output of the charge amplifier.

4.3 Input MOSFET

The input MOSFET of an amplifier is typically the dominant source of noise in the

amplifier. As discussed in Chapter 2, the dominant noise sources in MOSFETs are

thermal noise and flicker noise. Typically, PMOS transistors have less flicker noise

than NMOS transistors. However, for the same transistors size, a PMOS transistor has

more thermal noise than an NMOS transistor.

4.4 Transistor Sizing

Sizing of transistors is a critical aspect of charge amplifier design. Expressions for

thermal and flicker noise of a MOSFET, show that the noise performance of each

transistor is dependent on its size. As an example, the transistors in the simple

amplifier as of Figure 4.6 are the input transistor M1, the cascode transistor M2 and

the current-source load transistor M3. In this section the sizing of each of these

transistors for noise reduction is considered.


Figure 4.5: Folded cascode amplifier

Figure 4.6: Simple amplifier for noise analysis

Vout

VBIAS4

VBIAS3

VBIAS2

M1

M4

Vin V

BIAS5

M2

M5

M3

Vout

VBIAS2

VBIAS3

M2

Vin M1

M3

4.4. Transistor Sizing 47

The input-referred noise voltage of the amplifier in Figure 4.6 can be written as

v in2 =vn1

2 +Gm22 vn2

2 / gm12 +gm3

2 vn32 / gm1

2 (4.2)

where v n1 , v n2 and v n3 are the input-referred noise voltages of the M1, M2 and M3,

respectively. Similarly, gm1 and gm3 are the transconductances of M1 and M3. Gm2 is

the effective transconducatnce of M2, with source degeneration (the transistor M1 is at

the source of M2) [43]. If the amplifier in Figure 4.6 is used as the op amp of a charge

amplifier, then the output noise voltage of the charge amplifier is [44]

v nout

2 =v in2 (C f +C g+C det)

C f (4.3)

where Cf is the feedback capacitance, Cg is the gate capacitance of the input transistor

and Cdet is the capacitance of the detector serving as the input source.

The noise contribution of the cascode transistor is minimal since its effective

transconductance is smaller than that of the input transistor due to source degeneration

[43]. Therefore, the sizing of the cascode transistor is not critical to the noise

performance of the amplifier.

From Equation (4.2), the noise contribution of the load transistor is minimal if

its transconductance is smaller than that of the input transistor. Typically, in order to

achieve high gain, the input transistor's transconductance is large compared to that of

the load transistor.

The sizing of the input transistor is not as straightforward as the sizing of the

cascode and load transistors. Using a large input transistor reduces the input-referred

noise voltage. However, as shown in Equation 4.3, the output noise is proportional to

the input capacitance, which includes Cg. Therefore, an optimum sizing exists for the

input transistor which is dependent on the values of Cf and Cdet.

With proper transistor sizing the input-referred noise voltage is dominated by


the noise of the input transistor, so that v in2 ≈ vn1

2 . The optimum sizing for the input

transistor is next derived when the noise of the input transistor is dominated by: 1)

thermal noise, 2) flicker noise.

Case 1) Dominant Noise Source: Thermal Noise

Assume a charge amplifier in which the input transistor of its op amp is the dominant

source of noise. From Equation (2.9) with gm = ωTCg, where ωT is the transit

frequency of the transistor, the input-referred noise of the charge amplifier is

v th2 =

8K BT Δ f3ωTC g

(4.4)

It then follows from Equation (4.3) that the output noise voltage is

v nout2 =

8K BTΔ f3ωT C g

(C f +C g+C det)2

C f2 (4.5)

A minimum v nout2 can be found with respect to the size of the input transistor.

Assuming that ωT is constant, then the noise is minimum when Cg = (Cf + Cdet).

A similar method may be used to find the optimal input transistor size for the

case in which the DC current is fixed. Since the dark current of diode-based sensors

increases with temperature, many applications have power consumption limitations.

Assuming that the DC current is constant, then the noise is minimum when Cg = (Cf +

Cdet)/3.

Case 2) Dominant Noise Source: Flicker Noise

From Equations (2.12) and (4.3), an expression for the output noise voltage for the

4.5. Correlated Double Sampling 49

case where flicker noise is dominant ( v in2 =v f

2 ) may be written as

v nout2 =v f

2 (C f +C g+Cdet)2

C f2

= KΔ fCoxW L f

(C f +Cg+C det)2

C f2 (4.6)

The minimum value of Equation (4.6) occurs when the gate capacitance is equal to the

sum of the feedback capacitance and the detector capacitance, or in other words: Cg =

(Cf + Cdet).

In conclusion, the optimal sizing of the input transistor is dependent on the

characteristics of the system in use and the dominant noise source in the system. The

optimal sizing may differ in cases where other parameters of the circuit, such as the

current are fixed due to other constraints.

4.5 Correlated Double SamplingCorrelated double sampling (CDS) is a technique commonly used in sensor systems

to suppress fixed pattern noise (FPN) and reset noise [45]. FPN in pixel array systems

has a number of sources: mismatch among pixels due to process variation, mismatch

in the offsets of per pixel charge amplifiers and low-frequency noise in transistors.

The concept of correlated double sampling is illustrated in Figure 4.7. Initially

the charge amplifier is reset through the switch. After the reset switch has opened, the

output voltage is stored on the Ref capacitor. The stored voltage includes FPN and

reset noise

V Ref =FPN+N Reset (4.7)

Subsequently, the input arrives at the input of the charge amplifier and its integrated

value appears at the output of the charge amplifier. The output signal is stored on the


Figure 4.7: Concept of correlated double sampling

Sig capacitor. The voltage stored on the Sig capacitor includes noise from the reset

phase, the signal, S, and amplifier noise

V Sig=S+N amp+FPN +N Reset (4.8)

Finally, Vref is subtracted from Vsig, thus eliminating the reset noise and FPN

from the final output,

V out=S+N amp (4.9)

In general, CDS is more effective in systems with low input capacitance [47].

Various implementations of CDS exist in detector systems [48], [49], [50], [51]. These

implementations differ in implementation area, speed and effectiveness in reducing

noise.

4.6 Pulse ShapersA pulse shaper is a common circuit used in detector systems for noise reduction [52].

A pulse shaper limits the bandwidth of the output signal to the frequency of the input

signal, thereby attenuating noise in the frequencies outside of the input bandwidth.

However, the input signal is also shaped by the transfer function of the shaper.

+_

S

Reset

Ref

SigOut

4.7. Signal Averaging 51

Figure 4.8 shows the block diagram of a typical detector system that employs a

pulse shaper. The pulse shaper consists of a differentiator followed by an integrator.

The differentiator implements a high-pass filter, while the integrator implements a

low-pass filter. This type of pulse shaper is also known as a CR-RC shaper. The

combination of the high and low pass filters creates a band-pass filter that is centered

about the bandwidth of the incoming signal [52].

Several variations exist on the implementation of pulse shapers [54], [55], [56],

[57], [58], [59], [60]. Their typical tradeoffs are circuit complexity, power

consumption, speed, output noise level, gain and linearity.

4.7 Signal Averaging

Averaging is a technique used in signal processing to improve the signal-to-noise ratio.

In an ideal case, averaging improves the signal-to-noise ratio by a factor equal to the

square root of the number of measured samples. In other words [61]

SN

=Sσ √ N (4.10)

where S is the signal strength, σ is the standard deviation and N is the number of

samples. In order for Equation (4.10) to hold the signal and noise must be

uncorrelated, the strength of the measured signal should be constant throughout all

measurements, and the noise must be truly random with a mean of zero and a constant

variance of σ. Signal averaging may be used in the front-end electronics of detector

systems in order to reduce the charge amplifier noise [62].


Figure 4.8: CR-RC shaper

4.8 SummaryThis chapter provides an overview of the design of low-noise charge amplifiers. The

tradeoffs among various circuit topologies of the open-loop voltage amplifier were

reviewed. Also, in this chapter, the choice of an NMOS or PMOS for the input

transistor along with sizing of the transistor channel were discussed. The sizing of the

cascode transistors were determined to be of low-impact on the output noise.

The chapter concluded with a short description of a number of techniques

commonly used to reduce noise in detector systems. Among the described noise

reduction methods, correlated double sampling is perhaps the most commonly used

technique with minimal draw-backs. CDS reduces the noise of detector systems by

suppressing fixed pattern noise and reset noise from the output. Also, the

implementation of pulse shapers is effective in improving the noise performance of

detector systems by limiting the bandwidth of the noise in the output. However, the

signal is also shaped by the pulse shaper.

In

Differentiator Integrator

Chapter 5

Zero-Pole Transformation Noise Reduction

The previous chapters have presented a basis for understanding the purpose and

operation of the zero-pole transformation technique. The proposed technique can

reduce noise levels in charge amplifiers without introducing much complexity into the

design of the detector system. In this chapter, initially, the concept of boosting and

de-boosting a signal, upon which the proposed technique is based, is explained. Next,

the theory of operation and implementation of zero-pole transformation are described.

The chapter then continues with an analysis of the noise performance of a zero-pole

transformed charge amplifier. Subsequently, the effect of input capacitance and

mismatch on the proposed technique is analyzed. Finally, the chapter concludes with a

discussion on the tradeoffs involved with the implementation of this method.

53

54 Chapter 5: The Zero-Pole Transformation Technique

5.1 Boosting and De-boosting

The boosting and de-boosting of a signal is a means of reducing the noise level of a

system. The method is based on filtering the input and the output of a system with

inverse transfer functions so as to attenuate noise introduced by the system without

modifying the input signal.

Consider a simple system that includes only one gain block, as shown in Figure

5.1(a), with a gain of G. The output is

Out=G×In+N (5.1)

where N is the amplifier noise.

With boosting and de-boosting, two extra blocks are introduced into the

system, as shown in Figure 5.1(b). Before the input enters the gain block, a boosting

block with a transfer function of H, filters the input. Additionally, a de-boosting block

is added at the output of the gain block with a transfer function of H', the inverse of H.

The value of the output signal is

Out=n2×H '

Out=(n1×G+N )×H '

Out=(( In×H )×G+N )×H ' (5.2)

In the derivation of Equation (5.2), it has been assumed that the noise

contributions of the boosting and de-boosting blocks are negligible compared to the

noise of the gain block. This is usually a valid assumption in practical applications of

5.1. Boosting and De-boosting 55

Figure 5.1: (a) Basic system, (b) System with boosting and de-boosting

the boosting and de-boosting technique. Equation (5.2) may be re-arranged as

Out= In×G×H ×H '+N×H ' (5.3)

In systems that employ boosting and de-boosting, the two transfer functions H and H'

are chosen so that they are inverses of each other, that is H ×H '=1 . In that case, the

transfer function of the overall system with boosting and de-boosting is

Out= In×G+N×H ' (5.4)

GIn Out

Gn1 n2In Out

H'H

Boosting Block De-boosting Block

(a)

(b)


Equation (5.4) shows that with boosting and de-boosting, the signal passes

through the system unmodified by the boosting and de-boosting functions. However,

the noise of the base system is filtered by the de-boosting function A'.

As described above, the input boosting and de-boosting technique promises a

method for reducing noise in systems. If the boosting and de-boosting functions are

noiseless and their product equals unity, the de-boosting function can be used to

reduce the noise of any system. In practice, difficulty arises in constructing the

boosting and de-boosting blocks themselves to be low noise. A prominent noise

reduction method known as chopper stabilization performs an operation similar to

boosting and de-boosting [63], [64], [65].

5.2 The Zero-Pole Transformation Theory of Operation

Zero-pole transformation is based on the concept of boosting and de-boosting

described in Section 5.1. The proposed technique may be implemented in charge

amplifiers in order to reduce noise. In this method, the boosting function is

implemented as a unity gain function with a zero in the frequency domain

A=1s /z (5.5)

The de-boosting function is implemented as a unity function with a pole in the

frequency domain

A '= 11s/ p

(5.6)

In order for the product of the two transfer function A and A', to equal unity, the zero

and pole must be the same, i.e. z= p .

5.3. Architecture of a Zero-Pole Transformed Charge Amplifier 57

With zero-pole transformation, the signal passes through the system

unmodified by the boosting and de-boosting functions. However, the noise of the

system is filtered by the de-boosting function. Theoretically, since the signal is not

altered by the combination of the zero and pole functions, the frequency of these two

functions may arbitrarily be chosen to be low. Thus, zero-pole transformation

promises the reduction of noise down to extremely low frequencies. In practice, non-

idealities involved with the physical implementation of the zero-pole transformation

limit how low the frequencies of the zero and pole functions may be placed.

5.3 Architecture of a Zero-Pole TransformedCharge Amplifier

In this section, the physical implementation of the zero-pole transformation method in

a charge amplifier is described. The basic structure of a typical charge amplifier was

described in Chapter 3. The basic amplifier is composed simply of an operational

amplifier with a capacitor connected in feedback. The transfer function of the basic

charge amplifier is

VoutQin

=−1C f

(5.7)

A zero-pole transformed charge amplifier is shown in Figure 5.2. The boosting

function is implemented by inserting the resistor Rz in series with the feedback

capacitor, Cf. Rz creates a zero in the transfer function of the charge amplifier at the

frequency ωz = ─1/RzCf. The input capacitance is Cin = Cg + Cd. Cg is the gate

capacitance of the input MOSFET and Cd is the capacitance of the detector connected

to the input of the charge amplifier. Assuming that the op amp gain, A, is large, the

transfer function at node Vz is

V z

Q in=

−(1+sRzC f )C f

(5.8)


Figure 5.2: Zero-Pole transformed charge amplifier

The de-boosting function is implemented by an RC filter, as shown in Figure 5.2 by

the combination of Rp and Cp. The filter creates a pole at the output such that

V out

V z= 1

(1+sR pC p) (5.9)

Thus, the transfer function of the zero-pole transformed charge amplifier is

V out

Q in=

−(1+sRzC f )C f (1+sR pC p)

(5.10)

It is clear from Equation (5.10) that if RzCf = RpCp, then the transfer function of the

zero-pole transformation charge amplifier reduces to that of a basic charge amplifier.

Therefore, a signal may pass through the zero-pole transformed charge amplifier

without being modified by the boosting and de-boosting functions.

Vout

In

RefReset

Rz

Cf

Rp

Cp

Vz

A_

+C

in

5.4. Noise Analysis of the Zero-Pole Transformed Charge Amplifier 59

5.4 Noise Analysis of the Zero-Pole TransformedCharge Amplifier

The transfer function of the zero-pole transformed charge amplifier was derived in the

previous section. From Equation (5.10) it is clear that if RzCf = RpCp, then the signal

passes through the system unaffected by boosting and de-boosting. In this section, the

effect of boosting and de-boosting on the noise of the charge amplifier is analyzed.

Figure 5.3 shows the diagram of a basic charge amplifier. The noise of the op

amp is referred to its input as the voltage source v ineq2 . According to Equation (4.3),

the output noise of the charge amplifier in Figure 5.3 is

v outeq2 =v ineq

2 (C f +C in)2

C f2 (5.11)

From Equations (5.11) and (3.5), it follows that the input-referred noise of a basic

charge amplifier is

ENC in2 =v ineq

2 (C f +C in )2 (5.12)

where ENCin is the equivalent noise charge at the input.

Next we consider noise of the zero-pole transformed charge amplifier shown

in Figure 5.4. v ineq2 is the noise of the op amp referred to its input. The equivalent

input noise current, iineq2 , is v ineq

2 / Z ia . Zia is the impedance seen at the input of the

charge amplifier with the node Vz shorted to ground

Z ia=(1+sRz C f )

s (C f +C in+sRz C f C in) (5.13)


Figure 5.3: Noise analysis of the basic charge amplifier

Figure 5.4: Noise analysis of the zero-pole transformed charge amplifier

A

_

+

Cf

Vout

Iin

Cin

vineq

2____

A

_

+

Cf

Iin

Cin

vineq

2

Rz

Vout

Rp

Cp

___V

z

5.4. Noise Analysis of the Zero-Pole Transformed Charge Amplifier 61

Thus, the input-referred noise current is

iineq2 =v ineq

2 s2(C f +C in+sRz C f C in)2

(1+sRz C f )2 (5.14)

The transfer function in Equation (5.10) may be re-written for an input current

V out

I in=

−(1+sRzC f )sC f (1+sR pC p)

(5.15)

From Equations (5.14) and (5.15), the output noise voltage due to v ineq2 is

v outeq2 =v ineq

2 (1+sRzC f )2

C f2 (1+sR pC p)

2

(C f +C in+sRz C f C in)2

(1+sRz C f )2

=vineq2 [(C in+C f )(1+sRzC in C f /(C in+C f ))]

2

C f2

1(1+sC pRp)

2 (5.16)

Next, assume that Rz and Rp are sufficiently large such that, down to low

frequencies (~ 1kHz), the following two inequalities hold

sRz

C in C f

(C in+C f )>1 (5.17)

sR pC p>1 (5.18)

In addition, if Cp = Cf, then Equation (5.14) can be simplified to

v outeq2 =v ineq

2 (C in+C f )2

C f2

C in2

(C in+C f )2 (5.19)


The input-referred noise is

ENC in2 =v ineq

2 (C in+C f )2 C in

2

(C in+C f )2 (5.20)

Using Equations (5.12) and (5.20) the ratio of the input-referred noise of a

zero-pole transformed charge amplifier to that of a basic charge amplifier is

ENC zero− pole

ENC basic=

C in

(C in+C f ) (5.21)

The percent noise reduction achieved through zero-pole transformation is

Noise Reduction=C f

(C in+C f )×100% (5.22)

The zero-pole transformation is best used in applications in which Cf > Cin or Cf and

Cin are comparable in size.

5.5 The Secondary Pole

If the op amp gain, A, is not assumed to be infinitely large, then the transfer function

of the charge amplifier in Figure 5.2 is

V out

Q in=

−(1+sRzC f )C f (1+sR pC p)(1+sC inRz / A)

(5.23)

Thus, there is a secondary pole located at

psecondary=−1

(C in R z/ A) (5.24)

which limits the bandwidth of the zero-pole transformed charge amplifier.

5.6. Resistor Implementation 63

5.6 Resistor Implementation

In order to achieve significant noise reduction using zero-pole transformation, the

resistors Rz and Rp must be quite large because of the limited capacitor size in an

integrated circuit. These resistors should be in the gigaohm range. Therefore, an

appropriate method of implementing such large resistors must be devised.

In this section, voltage-controlled MOSFET resistors and MOS-bipolar

resistors, which are both often used to implement large resistors, are introduced. In

addition, a structure using MOS-bipolar resistors for use in zero-pole transformation

is presented.

Voltage-Controlled MOSFET Resistor

Voltage-controlled MOSFETs are commonly used as large resistors in integrated

circuits [66], [67], [68], [69]. The gate-to-source voltage of the MOSFET is used to

control the channel resistance of the transistor. In order to achieve large resistance, the

MOSFETs are operated in the sub-threshold region.

If it is assumed that the source and bulk are tied together and that the drain-to-

source voltage is less than 25mV, the drain-to-source current of a MOSFET operating

in the sub-threshold region is [70]

I ds=I d0WL

eV gs−V th

nV T (−V ds

nV T) (5.25)

where Id0 is a constant and W and L are the electrical channel width and length of the

transistor, respectively. Vgs is the gate-to-source voltage, VT = kT/q and Vth is the

threshold voltage. Vds is the drain-to-source voltage and n = ( 1 + CD / Cox ). CD and

Cox are the depletion layer and gate oxide capacitance, respectively. The channel


resistance of a MOSFET in sub-threshold may be derived from Equation (5.23) as

RMOSFEET=(

∂ I ds

∂ dV ds)−1

=nV T

I d0WL

eV gs−V th

nV T (5.26)

Figure 5.5 shows the resistances of NMOS and PMOS transistors of a 0.18-µm

technology as a function of their respective gate voltages. The resistances vary

exponentially with Vgs. Therefore, the resistance is extremely sensitive to this voltage.

This high sensitivity can be troublesome in applications which resistor matching is

important. Additionally, maintaining a constant resistance is challenging in

applications in which the MOSFET source voltage varies depending on the input

signal.

One common method of reducing the variation of MOSFET resistance versus

Vgs is to place NMOS and PMOS transistors in series. Figure 5.5 shows an example of

the value of such a series resistance. In this example, the NMOS and PMOS

transistors have been tuned to have equal channel resistances at Vds = 0, which in

practice, would be difficult to achieve. In addition, the series resistance is not

sufficiently constant across Vgs for it to be used in zero-pole transformation.

MOS-Bipolar ResistorMOS-bipolar resistors are also used to implement large resistors [71]. As shown in

Figure 5.6, a MOS-bipolar resistor is essentially a MOSFET with its gate and drain

nodes connected to each other. In the case of a PMOSFET it behaves as a diode-

connected transistor for Vgs < 0. For Vgs > 0, it behaves as a diode-connected bipolar

junction transistor since the parasitic source-well-drain pnp bipolar junction transistor

is activated [71], [72].


Figure 5.5: Resistance of MOSFETs vs. gate to source voltage

Figure 5.6: MOS-bipolar resistor


The gate-to-source voltage of a MOS-bipolar resistor typically varies less than

the gate-to-source of a voltage-controlled MOSFET resistor. In a MOS-bipolar

resistor the gate and source voltages move together, whereas in the voltage-controlled

MOSFET the gate voltage is held constant and only the source can vary with the input

signal.

Figure 5.7 shows the resistance of a MOS-bipolar resistor versus its Vds using

simulation data for a PMOSFET in 0.18-µm technology with a nominal threshold

voltage of 0.6V. As mentioned earlier, depending on the value of Vgs, the transistor either behaves as a diode-connected MOSFET or a diode-connected BJT. In this case, as Vgs H 0.6V. As mentioned earlier, depending on the value of Vgs, the transistor

either behaves as a diode-connected MOSFET or a diode-connected BJT. In this case,

as Vgs decreases below 0.6V. As mentioned earlier, depending on the value of Vgs, the transistor either behaves as a diode-connected MOSFET or a diode-connected BJT. In this case, as Vgs H 0.6V. As mentioned earlier, depending on the value of Vgs, the transistor either behaves as a diode-connected MOSFET or a diode-connected BJT. In this case, as Vgs 0.2V, the PMOSFET diode becomes more forward-biased,

and consequently the resistance drops. Also, as Vgs increases beyond 0.2V, the

parasitic BJT becomes strongly forward-biased, and therefore its resistance also

decreases.

MOS-bipolar resistors are not symmetrical about 0V. When a signal arrives at

the input of the charge amplifier, the voltage across Rz and Rp move in the opposite

direction. Thus, it is important that Rz and Rp be symmetrical in order for them to

follow each other during the operation of the charge amplifier. In addition, similar to

voltage-controlled MOSFETs, the resistance of MOS-bipolar resistors varies

significantly across Vgs = Vds. However, simple combinations of MOS-bipolar resistors

can be used that provides a relatively stable and symmetric resistance. These

structures are described next.

Series-Reverse-Connected MOS-Bipolar Resistors

By placing two MOS-bipolar resistors in series, in the opposite direction, as shown in

Figure 5.8, a symmetrical resistance can be achieved. The resistance of a MOS-

bipolar pair versus a single MOS-bipolar resistor is shown in Figure 5.9.

When |Vds | moves from 0 to 0.15V, the resistance of the MOS-bipolar pair

varies by a factor of 3 in the simulated 0.18-µm technology. This variation may be


Figure 5.7: Resistance of MOS-bipolar resistor vs. Vds

reduced by connecting a number of MOS-bipolar pairs in series. Such a structure is

shown in Figure 5.10. The resistance of MOS-bipolar resistors vary exponentially

with Vds. By cascading MOS-bipolar pairs, the voltage across the resistors is dropped

linearly among all of the pairs, thereby reducing the net resistance variation.

Figure 5.11 shows the resistance of a single MOS-bipolar pair along with the

resistance of a number of cascaded pairs. For |Vds| < 0.15V, the resistances of the 2, 4

and 8 pair cascades vary by factors of 1.9, 1.2 and 1.1, respectively. Thus, cascading

MOS-bipolar pairs provides a relatively stable resistance.

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.40.00E+00

1.00E+11

2.00E+11

3.00E+11

4.00E+11

5.00E+11

6.00E+11

7.00E+11

8.00E+11

9.00E+11

Vds(V)

Res

ista

nce

(Ohm

s)


Figure 5.8: Series-reverse-connected MOS-bipolar pair

Figure 5.9: Reverse-connected MOS-bipolar pair vs. single MOS-bipolar

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.40.0E+00

2.0E+11

4.0E+11

6.0E+11

8.0E+11

1.0E+12

1.2E+12

MOS-Bipolar Duo Single MOS-Bipolar

Vdrive(V)

Res

ista

nce(

Ohm

s)

Single MOS-Bipolar

MOS-Bipolar Pair


Figure 5.10: N number of MOS-bipolar pairs connected in series

Figure 5.11: Resistance of MOS-bipolar pairs connected in series

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.40.0E+00

5.0E+11

1.0E+12

1.5E+12

2.0E+12

2.5E+12

3.0E+12

3.5E+12

4.0E+12

4.5E+12

Eight Duo's Four Duo's Two Duo's One Duo

Vdrive(V)

Res

ista

nce(

Ohm

s)

1 Pair2 Pairs4 Pairs8 Pairs

Vds

(V)

N Pairs


A disadvantage of using MOS-bipolar resistors is that they vary significantly

across process corners. Resistance values can vary by factors as high as 500 across

the process corners. Therefore, it is imperative that any design using MOS-bipolar

resistors include digital calibration.

5.7 Zero-Pole Mismatch

In Section 5.2, it was shown that the effectiveness of zero-pole transformation depends

on the matching of the zero and pole frequencies. In order for these frequencies to

match it is necessary that RzCf = RpCp. In zero-pole transformation, the dominant

source of mismatch of the zero and pole frequencies, is the mismatch between Rz and

Rp.

Assume that the dominant source of mismatch among the MOS-bipolar

resistors is the variation of their threshold voltages, Vth. The mismatch in the resistors

may be estimated to the first order using Equation (5.26)

Δ RR

=eΔV th

nV T (5.27)

or

σΔR=eσΔVth

nV T

(5.28)

where σΔVth=AVt /√WL . In 0.18-µm technology AVt ≈ 4mV-µm and n ≈ 1.5. Thus,

the expected variation in the value of a MOS-bipolar resistor with W/L = 1µm/1µm is

approximately 10%.

Zero-pole cancellation is a technique commonly used in integrated circuit

design to increase the bandwidth of circuits [3]. Thus, imperfect zero-pole mismatch

is a challenge in many frequency compensated circuits. According to [74], the

5.8. Tradeoffs 71

effect of imperfect zero and pole cancellation on the output amplitude and phase

response of a circuit is typically negligible. However, a mismatch in the frequency of

a zero and a pole has a large impact on the settling time of the response. Moreover,

the increase in the settling time due to mismatch is more severe when the zero and

pole are at low frequencies [74].

The transfer function of the zero-pole transformed charge amplifier given in

Equation (5.10), may be re-written as

V out

I in=

−(1+s /ωz)sC f (1+s /ω p)

(5.29)

where ωz= 1/(RzCf) and ωp= 1/(RpCp). The step response of Equation (5.29) may be

derived using the inverse Laplace transform

L−1(V out

I in)=L−1 {−

(1+s /ωz)sC f (1+s /ωp)

}

= 1C f

L−1{ 1s (1+s /ωp)

+(s /ωz)

s (1+s/ω p)}

= 1C f

[ (1−e- ωp t)u (t)+ωp /ωz e- ωp t u (t)]

= 1C f

u(t )[1+e -ω p t(ω p/ωz−1) ] (5.30)

Equation (5.28) shows that the settling time is proportional to the pole of the system,

while the settling error is proportional to the mismatch between the zero and the pole.

5.8 Tradeoffs

In this section, three tradeoffs that must be addressed when implementing zero-pole

transformation are considered. First is the reduction in the input range of a zero-pole

transformed charge amplifier. Second, the tradeoff between the amount of noise


attenuation achieved through the proposed method and the maximum operating

frequency of the charge amplifier is analyzed. Finally, the amount of area required to

implement of zero-pole transformation is discussed.

5.8.1 Reduced Input Range

The input range of a zero-pole transformed charge amplifier is lower compared to a

basic charge amplifier. This reduction is due to the presence of a zero in the transfer

function of the charge amplifier. Although, overall the signal is unaffected by the zero

and pole in the transfer function of the charge amplifier; the signal swings at the

intermediary nodes are altered.

As shown in Equation (5.8), Vz in Figure 5.2 has a zero in its transfer function,

which means it has large voltage swings. Figure 5.12 shows simulation results from a

zero-pole transformed charge amplifier with a supply voltage of 1.8V. When an input

arrives at the input of the charge amplifier, Vz makes a jump and then decays to its dc

value, whereas Vout quickly jumps to its final value.

The zero in the response of Vz may cause the charge amplifier to saturate. The

lower the zero is in frequency, the larger the voltage swing will be at Vz . Parasitic

poles somewhat compensate the zero, such that the swing at Vz is not infinitely large.

The input signal range must be small enough so that the response at Vz does not

saturate the charge amplifier. The main components of the parasitic capacitance are

Cgb and Cgs of the MOS-bipolar resistors. These capacitances appear in parallel to the

resistor, as shown in Figure 5.13, and thus form a pole in the transfer function of Vz.

As noted previously, the amount of noise reduced through zero-pole

transformation depends on the frequency of the zero. Thus, a tradeoff exists between

the input signal range and the amount of noise reduction in a zero-pole transformed

charge amplifier.

5.9. Summary 73

Figure 5.12: Saturation of the intermediary node Vz

Figure 5.13: Parasitics of MOS-bipolar resistors

5.8.2 Speed

As discussed in Section 5.5, there is a secondary pole formed by the combination of

the amplifier's input capacitance and Rz. This pole limits the bandwidth of the zero-

pole transformed charge amplifier. Increased noise reduction is achieved by zero-pole

0 20

Time (μs)

00.5

1.7

V z (V)

1.1 Vz

Vout

10

RMOS-bipolar

Cgs

+ Cgb

+ Cdb

+ Cds


transformation when Rz is large. Therefore, there is a direct tradeoff between the

amount of noise reduced by zero-pole transformation and the bandwidth of the charge

amplifier.

5.8.3 Area

Implementation of the zero-pole transformation requires the addition of Rz, Rp and Cp

to a charge amplifier. The capacitor Cp can be designed within minimal area. The

resistors are implemented with MOS-bipolar resistors. Although, individual MOS-

bipolar resistors are small, combinations of them must be used, as described in Section

5.6, in order to reduce the variation in resistance. In addition, due to the large

variations of these resistors across process corners, digital calibration must be

included. The implementation of Rz and Rp in a 0.18-µm technology would occupy an

area of approximately 60µm x 60µm.

5.9 SummaryIn this chapter zero-pole transformation for noise reduction in charge amplifiers was

described. It was shown that the proposed technique could significantly reduce the

noise of a charge amplifier by filtering the noise without modifying the input signal.

The effect of input capacitance and device mismatch on the performance of the

zero-pole transformation technique were examined. The input capacitance of the

amplifier creates a parasitic pole and thereby reduces the bandwidth of the circuit.

Device mismatch increases the settling time of the output and also introduces a

settling error. The settling error essentially modifies the gain of the charge amplifier.

If needed, the settling error may be corrected for using digital calibration or post-

processing techniques. Finally, reduced input range and speed were noted as the main

tradeoffs of the amount of noise reduction achievable with zero-pole transformation.

Chapter 6

Charge Injection in the Zero-Pole Transformed Charge Amplifier

In Chapter 3, the basic feedback charge amplifier was described. As discussed there,

the feedback capacitor is reset after the signal is processed, and two means of reset

were presented: continuous and pulsed. In pulsed reset, charge is injected onto the

input of the charge amplifier by the reset switch. In this chapter, the issues related to

this charge injection by the reset switch in a zero-pole transformed charge amplifier

are examined. Additionally, a number of techniques for reducing the amount of

injected charge are presented.

6.1 Charge Injection Issues

Numerous studies have reported on the use of transistors as switches in switched-

capacitor circuits [75]-[83]. The transistor is not an ideal switch. When a transistor

switch turns off, charge is injected into the nodes on both sides of the transistor. In a

75

76 Chapter 6: Charge Injection in the Zero-Pole Transformed Charge Amplifier

basic charge amplifier, the charge injected onto the input node can be treated as a

current pulse into this node. The resulting voltage step at the output of the charge

amplifier can be canceled in the final output of the system by using correlated double

sampling. However, the injected charge can cause saturation of the charge amplifier if

the injected charge is sufficiently large.

The possibility of saturation of the charge amplifier by the charge injected from

the reset switch is higher in a zero-pole transformed charge amplifier compared to a

basic charge amplifier because of the reduction of the input range of the zero-pole

transformed charge amplifier described in Section 5.8. In addition, as discussed in

Section 5.7, resistor mismatch in the zero-pole transformed charge amplifier creates

long settling times at the output. The injected charge will not be completely

eliminated from the output of the system by correlated double sampling if the output

has not completely settled before the first sample is stored. Thus, circuit techniques

are needed to reduce the amount of charge injected onto the input node by the reset

switch.

6.2 Sources of Charge Injection

There are three main sources of charge injection in MOS switches: channel charge,

gate-to-diffusion overlap charge and charge due to interface traps [77]. These sources

of charge injection are described below.

When a transistor switch is on, a conduction channel exists between the source

and the drain. When the gate voltage drops below the threshold voltage, the channel

disappears and channel charge is transferred to both the source and drain of the

transistor.

Figure 6.1 shows a transistor switch between an input node and a hold node.

The amount of channel charge injected onto each node depends on the rate at which

6.2. Sources of Charge Injection 77

Figure 6.1: Basic structure of a MOS switch with input and load nodes

the gate voltage falls when turning off the switch and the capacitance at each node.

With a fast voltage drop rate, the channel charge is divided equally between the input

and load nodes. However, for low gate fall times, the channel charge is divided

between the input and load nodes according to their respective capacitances to ground

[77].

Charge is also injected due to feed-through of the transistor gate voltage to the

source and drain through the overlap capacitances [84]. For a symmetric transistor

overlap capacitances are

Cov=Cox WL D (6.1)

where LD is the extent of the overlap of the gate with the source/drain.

The third source of injected charge is that from traps at the interface between

the channel and the gate dielectric. Typically, this charge is not significant, and it is

not considered in this work.

CL

CI

VH

VL


6.3 Techniques for Reducing Charge Injection

A number of techniques exist that suppress the effect of injected charge. Some of

these techniques are described in this section. Other advanced circuit techniques may

also be used but are not appropriate for per-pixel applications [85], [86].

6.3.1 Transistor Switch Size

The channel charge is proportional to both the width and length of the channel, while

gate-to-source/drain feed-through charge is proportional to the width of the channel.

Thus, the width and length of the transistor switch should be kept to a minimum [87].

However, the on-resistance of a minimum sized transistor switch may not be

sufficiently low.

Figure 6.2 shows charge injection simulation results for various switch sizes.

The y-axis in Figure 6.2 is the transient output voltage of a charge amplifier while the

reset switch is turning off.

6.3.2 Switch Turn-Off Speed

The amount of injected charge is reduced when the transistor is switched off slowly

[87]. Figure 6.3 shows the output voltage of a charge amplifier while the reset

transistor is switching off. Simulation results are presented for four turn-off times.

The turn-off time, toff, is the amount of time for the gate voltage to drop from high to

low. The graphs corresponding to the turn-off speeds of 200ns and 400ns lie on top of

each other. Therefore, there is no further reduction in the amount of charge injection

when increasing the turn-off time from 200ns to 400ns. The maximum allowable turn-

off speed is determined by the application specifications.

6.3. Techniques for Reducing Charge Injection 79

Figure 6.2: Charge injection for various transistor sizes

Figure 6.3: Charge injection for various turn-off times

0 5Time (μs)

0590

595

Cha

rge

Am

plifi

er O

utpu

t (m

V)2W/L

W/2L

W/L

0 5Time (μs)

0590

595

Cha

rge

Am

plifi

er O

utpu

t (m

V) toff

= 50ns

toff

= 100ns

toff

= 200ns , 400ns


6.3.3 Gate Voltage Swing of MOS Switch

The amount of injected charge may be reduced by decreasing the swing of the

transistor gate voltage. Typically, the gate voltage swings between the power supplies,

from Vdd to GND. Alternatively, the gate voltage may be dropped from Vdd to a non-

zero voltage VL. VL must be low enough such that the switch has sufficiently high off-

resistance.

Figure 6.4 shows the output of a charge amplifier during reset for various

values of VL. As shown, increasing VL reduces the amount of injected charge from the

reset transistor. In this simulation, for VL > 0.4V, the off-resistance of the transistor is

not sufficiently large.

6.3.4 Dummy Transistors

Dummy transistors can be used to partially cancel injected charge [88]. Figure 6.5

shows a transistor switch with dummy transistors. Many complicated clocking

schemes may be used for the two dummy transistors. In a simple version, the gate

voltage of the dummy transistors is the complement of Vg . In this case, as the gate of

the dummy transistor transitions, opposite charge to that from the switch is injected

onto the source and drain nodes.

Typically, the size of the dummy transistor is half of that of the switch, which

results in a dummy gate capacitance equal to half of that of the switch. Thus, if the

dummy gate voltage swings opposite to that of Vg and charge from the switch is split

equally between its source and drain nodes, then the injected charge from the dummy

transistor and switch cancel each other. However, as mentioned in Section (6.2), the

division of injected charge into the source and drain depends on the capacitance on

each node and the rate of the gate voltage transition. In practice, perfect cancellation

using half-sized dummy transistors is not achievable. Simulations may be performed

to predict appropriate dummy transistor sizes for near-perfect charge cancellation.

6.3. Techniques for Reducing Charge Injection 81

Figure 6.4: Charge injection for various gate low voltage values

Figure 6.5: Use of dummy switches for compensation of injected charge.

CL

CI

VH

VL

VH

VL

VH

VL

Dummy Dummy

0 5Time (μs)

0590

595C

harg

e A

mpl

ifier

Out

put (

mV) V

L = 0V

VL = 0.1V

VL = 0.2V

VL = 0.4V


6.4 Summary

In this chapter, charge injection in transistor switches and the challenges it presents in

charge amplifiers were reviewed. These issues are especially challenging when

implementing the zero-pole transformation technique in a charge amplifier because of

the reduced input range that accompanies this approach.

Channel charge injection and clock feed-through are the main sources of charge

injected onto the source and drain nodes. A number of techniques were described for

mitigating charge injection in transistor switches. These techniques include reducing

the switch size, reducing switch speed, decreasing the gate voltage swing and the use

of dummy transistors.

Chapter 7The Experimental Zero-Pole Transformed Charge Amplifier

In Chapter 5, the basic theory of operation of the zero-pole transformed charge

amplifier was discussed. An experimental charge amplifier that embeds the proposed

method has been fabricated and tested. This chapter focuses on the the design and

testing of that amplifier. Initially, the system architecture and circuit design of the

experimental amplifier are described. Next, the test setup of the experimental

amplifier is reviewed. Finally, the experimental testing results are presented.

7.1 System Architecture

Figure 7.1 shows the top-level architecture of the experimental chip. The output of the

zero-pole transformed charge amplifier is amplified by the Second Amplifier and the

signal is then buffered by the Buffer block before being driven off-chip. The Clocks

and Digital Calibration block is responsible for producing the necessary clocks and

also contains the circuitry for the digital calibration options included on the chip. The

Input Generation block generates an input signal that is typical of what might be

83

84 Chapter 7: The Experimental Zero-Pole Transformed Charge Amplifier

Figure 7.1: Architecture of the experimental system

provided by a detector in a typical x-ray imaging application. Finally, the Bias block

provides the necessary voltage and current biases for the system.

7.1.1 The Zero-Pole Transformed Charge Amplifier

Figure 7.2 shows a schematic of the zero-pole transformed charge amplifier. The

capacitors Cf and Cp are implemented using M5-M6 parallel plate capacitors. The

value of both capacitors is 60fF. Parallel plate capacitors are used instead of comb

Clocks and Digital Calibration

Input Generation

Zero-PoleTransformedCharge Amp

Second Amp Buffer

Bias

Output

7.1. System Architecture 85

Figure 7.2: Zero-Pole transformed charge amplifier

structure capacitors, since they have lower parasitic capacitance. The resistors Rz and

Rp are implemented using MOS-bipolar duo resistors as shown in Figure 7.3. Digital

calibration can be used to select from eight different resistance values. The nominal

resistance values for each setting is shown in Table 7.1. One of the calibration levels

sets Rz and Rp to approximately 0Ω. This setting essentially transforms the charge

amplifier to a traditional charge amplifier. In order to reduce parasitic capacitance,

minimum-sized transistor switches have been placed on both sides of the structure.

The total capacitance contributed by the switches on each side of the resistor structure

is ~ 1fF. As discussed in Chapter 5, the parasitic capacitance of the MOS-bipolar

resistors appear in parallel to the resistance of each MOS-bipolar resistor and

depending on the size of the transistor ranges from 0.5-7fF.

The open-loop amplifier, A, is a folded cascode circuit as shown in Figure 7.4.

The transistor sizes of the open-loop amplifier are shown in Table 7.2. Thermal noise

is the dominant source of noise in this charge amplifier. Thus, the input transistor is

chosen to be an NMOS since it has less thermal noise than a PMOS. The input

transistor was sized such that Cg ≈ (Cf + Cd)/2. In this design, the current in the charge

amplifier is assumed to be fixed. According to the discussion in Chapter 4, the gate

capacitance must be set to (Cf + Cd)/3. However, in this case if Cg was sized as

VoutIn

Cf

Cp

Reset

A


Figure 7.3: Circuit diagram of resistors Rz and Rp

Bit1 Bit1

Bit2 Bit2

Bit3 Bit3

Bit4 Bit4

Bit5 Bit5

Bit0

Bit6 Bit6

Bit7 Bit7


Setting # of MOS-bipolar resistors in series

Size of each transistor (W/L)

Total Nominal Resistance

0 0 (1 transistor switch) 0.22µm/0.18µm ~ 0GΩ

1 4 3.5µm/0.18µm 0.9GΩ

2 4 1.75µm/0.18µm 1.5GΩ

3 4 0.88µm/0.18µm 3GΩ

4 4 0.44µm/0.18µm 6GΩ

5 4 0.22µm/0.18µm 12GΩ

6 8 0.22µm/0.18µm 24GΩ

7 16 0.22µm/0.18µm 48GΩ

Table 7.1: Various calibration levels for Rz and Rp

Figure 7.4: Experimental folded cascode amplifier

Vout

VBIAS4

VBIAS3

VBIAS2

M1M4

Vin

M2

M3

88 Chapter 7: The Experimental ZP Mod/Demodulation Charge Amplifier

Transistor Width Length No. in Parallel(M)

M1 8 µm 0.8 µm 4

M2 2.5 µm 1 µm 5

M3 0.75 µm 0.75 µm 1

M4 2 µm 2 µm 1

Table 7.2: Open-loop amplifier transistor sizes

discussed in Chapter 4, then flicker noise would become significant. The current

source, M4, is not cascoded in order to increase dynamic range. The current through

M2 and M4 are 30µA and 1µA, respectively, and the target bandwidth is ~ 1MHz.

The bias voltages VBIAS2, VBIAS3 and VBIAS4 are set by the Bias circuitry to 1.09V,

1V and 0.49V, respectively. Vin is set to 0.47V during reset by shorting Vin to Vout.

Often, in detector systems the type of input charge is known in advance, and

thus the amplifier may be optimized accordingly to increase dynamic range. In this

case, the amplifier has been optimized for a negative input charge. The voltage at the

node Vout is approximately 0.5V, which gives 1.3V of headroom to the supply voltage.

The leakage charge is not expected to be significant, thus the charge amplifier

is reset through a pulsed switch. The reset switch is a minimum-sized NMOS

transistor (W/L = 0.22µm /0.18µm). The simulated injected charge was sufficiently

low. Hence, no dummy transistors were used to cancel injected charge.

7.1.2 Second Amplifier

Figure 7.5 shows a schematic of the second amplifier, which is a switched capacitor

voltage amplifier. Camp is 60fF and Cf2 is 10fF. Both capacitors are as parallel plate

(metal5-oxide-metal6) capacitors. The voltage gain of the amplifier is [8]

A=V out

V in=

Camp

C f2=6 (7.1)


Figure 7.5: Second amplifier of the experimental chip

The capacitance Camp is the same capacitance as Cp from the zero-pole transformed

charge amplifier. One side of the capacitor Cp is connected to the output of the charge

amplifier. The other side of Cp is connected to the input of the second amplifier. It is

also through this connection, that the correlated double sampling technique is

implemented. The circuit diagram of the open-loop amplifier and its transistor sizes

are the same shown in Figure 7.4 and Table 7.2 respectively.

7.1.3 Buffer

The Buffer block has a low output impedance and is able to drive high capacitance

loads. The Buffer is designed as a simple differential amplifier in negative feedback as

shown in Figure 7.6. VBIAS5 is set to 1.08V by the Bias circuitry and the current

through M5 is 0.5mA. Table 7.3 shows the transistor sizings for the Buffer block.

Reset

Vout

InC

amp

Cf2

A


Figure 7.6: Circuit diagram of the Buffer block


M1 15 µm 2µm 12

M2 15 µm 2 µm 12

M3 15 µm 2 µm 3

M4 15 µm 2 µm 3

M5 15 µm 2 µm 24

Table 7.3: Buffer block transistor sizes

Vout

VBIAS5

M4

Vin

M5

M2

M3

M1


7.1.4 Input Generation

The input of a charge amplifier is typically a current pulse. In practical applications,

the input signal is generated by a detector connected to the charge amplifier through

bump-bonding or is embedded into the silicon in which the charge amplifier is

fabricated. Connecting a detector to the charge amplifier entails associated

complications that are beyond the scope of this research.

In this work, the input signal is generated on the chip itself by the circuit

shown in Figure 7.7. The resistor R is equal to 2kΩ. This circuit is capable of

generating charge in the range of 0.1fC to 1fC. The node In, drives the input of the

charge amplifier. Vclk is a pulse that transitions from 0V to 1.8V some time after the

charge amplifier has reset. When Vclk is 0V, the voltage Vc is

V c=R

45RV b=

V b

45 (7.2)

Vb is set by an off-chip regulator to a value between 0V and 1.8V. When Vclk becomes

high, the NMOS switch turns on and VC is grounded. Assuming that the open loop

gain of the charge amplifier is large, the node In is a virtual ground. Due to the

voltage change across the capacitor, C, a charge is injected onto node In. This charge

is

Qin=−V b

45C (7.3)

The charge Qin is injected onto the input of the charge amplifier. The amount

of the injected charge may be varied by changing Vb off-chip.


Figure 7.7: The input generation block of the experimental chip

7.1.5 Clocks and Digital Calibration

The experimental chip has the following clocks: Reset, Reset2 and Vclk. The timing of

these clock signals is shown in Figure 7.8. The Reset and Reset2 clocks are used to

reset the charge amplifier and second amplifier, respectively. In addition, the

difference in timing between Reset and Reset2 is used to implement correlated double

sampling. Reset2 remains high after Reset1 becomes low, thereby storing the output

of the charge amplifier on the capacitor Camp. Once Reset2 becomes low, the stored

voltage on Camp is subtracted from the output of the charge amplifier. Finally, Vclk

rises approximately 5µs after the Reset2 signal goes low.

As discussed in Chapter 5, the output response of the charge amplifier may

have a long settling time due to resistor mismatch and the secondary pole. Digital

calibration is available to vary the timing between the two reset pulses in order to

VC

Vclk

Vb

R

44R

C = 25fF

In (virtual ground)


Figure 7.8: Timing of on-chip clocks

ensure that the output of the charge amplifier has settled, before the first CDS sample

is stored.

The Reset pulse is generated from an off-chip clock with a delay block that has

two inverters that are sized to slow the fall of the signal to approximately 400ns.

These inverters are shown in Figure 7.9, and their transistor sizes are shown in Table

7.4. The fall of Reset is slowed to reduce charge injection from the reset switch.

The circuit that generates Reset2 and Vclk is shown in Figure 7.10. Reset2 is

generated from the Reset clock, by inserting a number of delay blocks between the

two. The circuit and sizings of the the Delay 400ns block is the same as shown in

Figure 7.7 and Table 7.4, respectively. The delay between Reset and Reset2 may be

set to 1.6µs, 3.2µs, 6.4µs and 9.6µs using digital calibration. Similarly, Vclk is

generated with a number of delay blocks from Reset2 .

Reset

Reset2

Vclk

5µs

1.6µs

1µs

0.4µs0.1µs

1.8V

0V

1.8V

0V

1.8V

0V


Figure 7.9: Generation of Reset from CLK


M1 0.7 µm 0.18 µm 4

M2 0.22 µm 20 µm 1

M3 0.22 µm 20 µm 1

M4 0.7 µm 0.18 µm 4

Table 7.4: Transistor sizes of Reset generator circuit

M1

M2

CLK

M3

M4

Reset


Figure 7.10: Generation circuits of Reset2 and VCLK

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

Delay400ns

MUX

CalibrationBits

Reset2

Reset

Delay400ns

Delay400ns

Reset2 VCLK


7.1.6 Bias Circuitry

The bias currents for the charge amplifier, second amplifier and the buffer are

generated using current mirrors as shown in Figure 7.11. Each of the reference current

paths contain a diode-connected PMOS transistor on-chip connected between the

power supply and a floating node. The floating nodes connect to the off-chip

potentiometers. The reference currents are designed to be approximately 100µA.

The various voltage supplies and biases are each generated with a low-noise

off-chip regulator as shown in Figure 7.12. Each regulator generates a voltage

proportional to the resistance of a potentiometer connected between one of its pins and

ground. The regulated voltages are each independently modifiable through their

individual potentiometers.

7.1.7 Chip Micrograph

Figure 7.13 shows the micrograph of the chip fabricated in 0.18μm National

Semiconductor technology. The main circuitry of the chip has been placed in the

center, in order to minimize the routing for power supplies, grounds and the analog

output. There are a total of 24 pins in the chip. The size of the chip is approximately

1.4mm x 1.4mm. The circuitry of the chip occupies an area of about 0.5mm x 0.5mm.

7.2 Test Setup

Figure 7.14 shows a photo of the test setup in the laboratory. The setup is composed

of a printed circuit board (PCB), metal shield, power supply, signal generator and an

oscilloscope. The PCB is placed inside the metal shield in order to reduce

electromagnetic interference.

A close-up view of the PCB is shown in Figure 7.15. The chip is packaged in a

leadless QFN package. The “elastomer” socket is used to hold the chip in place and

7.2. Test Setup 97

Figure 7.11: Bias current generation

Figure 12: Bias voltage generation

VBIAS M1

Off-Chip

VoltageRegulator

To Chip

RegulatedVoltage

1 2


Figure 7.13: Chip micorgraph

route the pins of the package to the board. The elastomer socket is able to connect the

pins to the board without any soldering required. The power supply is bypassed to

ground by 10nF, 100nF, 1μF, 10μF and 100μF, 22000μF capacitors [89].

The use of capacitors with different values enables the filtering of noise at

various frequencies. A number of other potentiometers are placed on the PCB in order

to control the bias currents and voltages of the chip. Finally, five digital bits are

programmable on the board via jumper cables.

7.2. Test Setup 99

Figure 7.14: Experimental test setup

Figure 7.15: Printed circuit board


A block diagram of the experimental setup is shown in Figure 7.16. The PCB

receives three inputs off-chip: VDD, GND and CLK. VDD is 3.3V and is sent to the

voltage regulators on the board. The regulated on-chip voltage supplies are all

approximately 1.8V. CLK is a pulse with a frequency of 20KHz, width of 1μs, and

rise and fall times of 5ns. The high and low levels of the CLK are 1.8V and 0V,

respectively. The output of the charge amplifier is sent from the PCB to an

oscilloscope for measurement.

The power supply used in the setup is the HP 6253A system, which was chosen

for its low-noise. The HP 6253A exhibits an rms noise voltage of only 350µV. The

signal generator used to generate the external clock, CLK, is an Agilent E3630A. The

noise level of the signal generator was determined not to be crucial to the noise

performance of the charge amplifier.

Two different oscilloscopes are used to analyze the analog output of the

experimental chip. One is the HP Infinium oscilloscope, which has low on-screen

resolution (20mV/div) but is capable of measuring the standard deviation of the output

signal to sufficient accuracy. The second oscilloscope used is the HP 54645D, which

has high on-screen resolution (5mV/div) and is useful for viewing a few mV's of

variation in the output of the chip.

Initially, an on-board, extremely low-noise ADC was used to digitize the

analog output of the experimental chip. However, the ADC clocks were found to be

feeding back into the output of the charge amplifier, thereby increasing the measured

noise. Therefore, the ADC was removed and the measurements were made in the

analog domain.

Since, the aim of the design was to achieve extremely low-noise levels, extra

caution was taken in the routing of all of the signals and supply/bias levels. VDD,

GND and CLK were all routed using metal-insulated wires. The outer metal provides

complete shielding of the signals, so that no electromagnetic fields could exist inside

the wire. The use of metal-insulated wires were found to have a significant impact on

the output noise level, especially when used for the VDD and GND signals.

7.2. Test Setup 101

Pow

erSu

pply

Sign

alG

ener

ator

Cur

rent

Bia

ses

Volta

geR

egul

ator

sD

igita

lC

alib

ratio

n

Cha

rge

Am

plifi

er

Osc

illos

cope

VD

D

GN

D

CLK

Ana

log

Out

put

Figu

re 7

.16:

Blo

ck d

iagr

am o

f tes

t set

up


7.3 Measured Performance

Figures 7.17 shows the Analog Output of the system in Figure 7.16, when the

amplifier is calibrated as a traditional charge amplifier, with generated inputs of 0fC

and 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds toO 1fC. There is unwanted feed-through between Vclk and the input of the charge

amplifier. When Vclk rises, feed-through charge is injected into the input, which adds

to the charge from the Input Generation circuit. The gain was measured by computing

the difference between the two output responses in Figure 7.17. The gain of the

traditional charge amplifier is 95mV/fC and its input-referred noise is 165ENC.

The Analog Output (Figure 7.16) of the zero-pole transformation charge

amplifier are shown in Figure 7.18 for generated inputs of 0fC and 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds toO 1fC. The

unwanted charge due to feed-through between Vclk and the input of the charge

amplifier causes difficulty in measurements with the proposed charge amplifier. As

discussed in Chapter 5, the proposed charge amplifier is susceptible to saturation. In

this design, the charge amplifier has been optimized for negative input charge.

However, the feed-through charge is positive and is large enough to saturate the charge

amplifier. After 40µs, the charge amplifier recovers and measurements may be taken.

The measured gain of the zero-pole transformation charge amplifier is

102mV/fC, which is 7% higher than the gain of the traditional charge amplifier. From

Equation (5.28), the higher gain is due to a mismatch of 7% between the resistors Rz

and Rp ( Rz / Rp= 1.07). The input-referred noise of the proposed charge amplifier is

102ENC, which is a reduction of 39% compared to the traditional charge amplifier.

In the experimental charge amplifier, Cin = 85fF and Cf = 60fF. According to

Equation (5.22), the expected amount of input-referred noise reduction is

% Noise Reduction=C in

(C in+C f )= 60fF

(60fF+85fF)=41% (7.4)

which is in agreement with the reduction measured in the lab.

7.3. Measured Performance 103

(a)

(b)

Figure 7.17: Output of traditional charge amplifier (a) Qinject = 0fC (b) Qinject = 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds toO 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds to 1fC

0 10 20 30 40 50 60 70 80 90 100Time(µs)

750

700

650

600

Out

put (

mV)

0

1.8 Pulses(V)

VCLK

Reset

Reset2

550

500

450

0 10 20 30 40 50 60 70 80 90 100

Time(µs)

750

700

650

600

Out

put (

mV)

0

1.8 Pulses(V)

VCLK

Reset

Reset2

550

500

450


(a)

(b)

Figure 7.18: Output of zero-pole transformed charge amp (a) Qinject = 0fC (b) Qinject = 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds to 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds to 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds toO 1fC. There is unwanted feed-through between Vclk and the input of the charge amplifier. When Vclk rises, feed-through charge is injected into the input, which adds to1fC

0 10 20 30 40 50 60 70 80 90 100Time(µs)

750

700

650

600

Out

put (

mV)

0

1.8 Pulses(V)

VCLK

Reset

Reset2

550

500

450

0 10 20 30 40 50 60 70 80 90 100Time(µs)

700

650

600

Out

put (

mV)

0

1.8 Pulses(V)

VCLK

Reset

Reset2

550

500

450

7.3. Measured Performance 105

Figure 7.19 compares the input-referred noise of the traditional and zero-pole

transformed charge amplifiers. Measurements were taken for varying integration

times. The integration time is the difference between the fall of one reset pulse and

the rise of the next reset pulse. As the integration time increases, the amount of output

noise increases due to the presence of low-frequency noise.

Figure 7.20 shows the measured versus the simulated input-referred noise. The

discrepancy between the two noise measurements is due to the three factors. One is

the presence of power supply noise in lab measurements, which was not modeled in

the simulations. Another is that the experimental noise measurement is exposed to

environmental radiation. Finally, in order to increase the speed of simulations, they

only included noise from the input transistor of the charge amplifier. It should be

noted that even though power supply noise and environmental radiation are present in

the laboratory, they are expected to be reduced by the same amount as shown in

Equation (5.22) as long as those noise sources can be represented as a noise voltage at

the input of the charge amplifier.

In the experimental charge amplifier, a 40% noise reduction was achieved

using zero-pole transformation. As explained in Chapter 5, the amount of noise

reduction depends on the ratio of Cin and Cf. In order to understand the applicability of

zero-pole transformation to various charge amplifiers a survey of the literature was

performed and the respective values for Cin and Cf were recorded. Subsequently, the

amount of expected noise reduction using the zero-pole transformation in those charge

amplifiers was computed from Equation (5.22). The results of this analysis are shown

in Figure 7.21. Each point in the graph is the percent of noise reduction that one of the

charge amplifiers in the literature can achieve using the proposed method.

Approximately, half of the studied charge amplifiers can achieve 30% or more noise

reduction using zero-pole transformation.


Figure 7.19: Charge amplifier noise measurement

Figure 7.20: Charge amplifier simulation noise vs. measurement noise

0 50 100 150 200 250

250

200

150

100

50

Integration Time (μs)

Inpu

t-Ref

erre

d N

oise

(EN

C)

Traditional Charge Amp

Zero-Pole Transformed Charge Amp

0 50 100 150 200 250

150

100

50

0

Integration Time (μs)

Inpu

t-Ref

erre

d N

oise

(EN

C)

Measured Noise

Simulated Noise

7.4. Summary 107

Figure 7.21: Extended noise reduction results

7.4 Summary

In this chapter, the design of an experimental zero-pole transformed charge amplifier,

along with its test results, were presented. The experimental amplifier occupies an

area of 90µmx40µm.

The proposed method offers a noise reduction of approximately 40% compared

to a traditional charge amplifier. The input-referred noise of the zero-pole transformed

charge amplifier is 102ENC. Approximately half of the charge amplifiers surveyed in

literature could achieve at least 30% of noise reduction when using zero-pole

transformation.

100

80

60

40

20

0

% N

oise

Red

uctio

n

Chapter 8Conclusion

8.1 Summary

The objective of this research has been to establish a flow for the design of a low-

noise charge amplifier and to explore the use of a zero-pole transformation for noise

reduction in charge amplifiers. The design of charge amplifiers with lower noise than

exhibited by those currently available will improve the quality of imaging and the

accuracy of particle physics studies.

In this work, the various circuit topologies available for the design of a charge

amplifier were explored, and the most appropriate for the intended applications were

specified. Additionally, design details, such as the choice of transistor type and sizing

were described for optimizing the noise performance of the charge amplifier. A

number of common noise reduction techniques were also presented, and their

respective tradeoffs were discussed.

The theory of operation of zero-pole transformation for noise reduction was

explained. The proposed method can greatly reduce the input-referred noise of

systems in applications where the input capacitance is smaller than, or comparable to,

the feedback capacitance. Zero-pole transformation is able to reduce noise without a

109

110 Chapter 8: Conclusion

substantial increase in chip area or introducing significant complexity into the design.

The proposed method reduces noise by boosting and de-boosting the signal. The

boosting function has a zero in the frequency domain, whereas the de-boosting

function has a pole in the frequency domain. The signal passes through the system

unaffected by the combination of the boosting and de-boosting functions. However,

the noise is filtered by the de-boosting function.

An experimental zero-pole transformed charge amplifier has been designed and

tested. The experimental results correlate well with the theory of the proposed

method. The experimental chip shows a noise reduction of 40% compared to a

traditional charge amplifier and has an input-referred noise of 102ENC.

Approximately half of charge amplifiers reported in the literature can achieve a noise

reduction of 30% or more using the zero-pole transformation method.

8.2 Suggestions for Future Research

As discussed in Chapter 5, the amount of noise reduction achieved through zero-pole

transformation is dependent on the ratio of Cin and Cf.. The smaller Cin is compared to

Cf, the more noise reduction is achieved through the proposed method. Since, Cf

should small in order to achieve high gain, the proposed method is best used in

applications in which Cin is small. Since, the largest component of Cin is the detector

capacitance, methods should be found that would decouple this capacitance from the

input of the charge amplifier.

The boosting and de-boosting implemented into the proposed system is based

on the cancellation of a zero and a pole function, which are implemented using

resistors and capacitors. Since integrated capacitors exhibit good matching in most

technologies, the matching of the zero and pole is limited by the MOS-bipolar

resistors. Thus, means of improving the matching of the resistors is another area of

future study.

8.2. Suggestions for Future Research 111

The topic of implementing high-resistance, low-are resistors merits further

study itself. In this work, MOS-bipolar resistors have been used for the resistors Rp

and Rz. An individual MOS-bipolar resistor provides high resistance while consuming

little area. However, combinations of these resistors must be used to mitigate their

variation with the voltage across them. In addition, MOS-bipolar resistors vary

significantly across process corners, and therefore digital calibration must be included

in each pixel to tune the resistors. Thus, in practice the implementation of MOS-

bipolar resistors consumes more area than desired. Although this area is sufficiently

small to fit within a pixel area, the usability of the proposed method would improve

with smaller area resistors. Moreover, such an improvement may be mandatory in

applications with smaller pixels.

Finally, in this work the zero-pole transformed charge amplifier was tested in

an isolated setting. Integrating the proposed charge amplifier with a detector and ADC

will allow for a complete study of the proposed method.

112 Chapter 8: Conclusion

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