The FVTX Technology

Gerd J. Kunde - LANL 1

The FVTX Technology

Outline• Overall Picture• Silicon Detector

– Geometry, Layout, Process• Readout Chip

– FNAL Chips, New Chip PHX• Detector Module

– Wedges, Lampshades• Data Path• FPGA Interface Board

– Concept, Potential Implementation• Overview on R&D Issues • Summary


FVTX Tracker Executive Summary

Four lampshade stations on each side

Mini-strips of 50 micron radial pitch: 2.2 -13 mm

Readout via new PHX chip from Fermi Nat’l Lab

Total strip count: ~ 2 * 860,000 strips (zero suppressed)

Total chip count: ~ 2 * 1680 chips

Total silicon area: ~ 2 *3350 cm2


78 cm

66 cm

45 cm

The Inner Volume of Phenix

Mechanical Design for VTX and FVTX by LANL & Hytec


Current VTX & FVTX Specifications

Barrel Section i-radius length strips/pixel

layer 1 2.5 cm 21.8 cm pixel

layer 2 5 cm 21.8 cm pixel

layer 3 10 cm 31.8 cm strip

layer 4 14 cm 38.2 cm strip

ministrip18 cm38 cmstation 4

ministrip18 cm32 cmstation 3

ministrip10.6cm26 cmstation 2

ministrip6.6 cm20 cmstation 1

tilt = 22 dego-radiusz-start(+-)Endcap (north and

south)

1.2%

2.0%

1 %

Rad.

Length


FVTX Part of VERTEX Spreadsheet


Silicon Detector Technical Overview

200 micron thickness 50 micron radial pitch (z reconstruction)

curved or straight strips ? (R&D) 1280,2048,2816 “mini-strips” 3.5 cm < r < 18 cm < 1.5 % occupancy (central AA)

48 “double towers” in phi mini-strips from 13.0 mm to 2.2 mm

readout via PHX 5,8,11 chip row

r = 3.5 cm

r = 18.0 cm

1

PHX derived from FNAL chips

2816

2048

1280


Only “2 ½” Silicon Detector types

Inside Detector (I)

Outside Detector (II)

Outside Detector (III)

5 chips= 1280 * 2 strips

706.2 mm^2


1698.5 mm^2


752.0 mm^2

50 micron strips (collaboration with Prague groups)


Two Silicon Wafer Layout Concepts

We assume 4 inch - 200 um wafers, the layout is matching the need of

inner and outer detectors:

Inner: 77 wafers + contingency

Outer: 96 wafers + contingency

n+ pixels on n substrate using “moderated p-spray”

as the n-isolation technology

Proven ATLAS/BTev technology with existing

qualified vendors


Silicon Sensor Schedule


Existing FNAL Chip: FPIX2.1 Features Advanced mixed analog/digital design

128 rows x 22 columns (2816 channels)

50 µm x 400 µm pixels

High speed readout intended for use in Level 1 trigger. Up to 840 Mbits/sec data output.

Very low noise, excellent threshold matching

DC coupled input

Fully programmable device

Output directly drives long cable (10 m, 30 feet)

90 mirco watt/pixel • (~0.25 watt/chip)

Rad hard to 50 Mrads

Change geometry for PHX-chip and

adjust analog front end to mini-strips capacity


FPIX 2.1 Pixel Circuit (50 x 400 µm)

Flash Latch to Binary

Encoder

Thermometer

Thresholds

Vff

Test

Sensor

Command Interpreter

00 -

01 -

10 -

11 -

idle

reset

output

listen

HFastOR

RFastOR Throttle4 pairs of

Command Lines

Kill

Inject

ADC

RowAddress

Read Clock

Read Reset

Token In

Token Reset

Token Out

ThresholdVref

Resets

Bus

Controller-

+

-

+

Vdda

3 bit

ADC

FPIX2: 60 e-rms measured noise @ c=0 pf

Signal/Noise ~ 50/1

Threshold/Noise ~ 10/1

for mini-strips on 200 um Si

PHX Simulation

PHX Simulation

2 mm to 10 mm strip length


FPIX 2 Module: “Real” Threshold and Noise

CHIP 4 CHIP 4

These are typical distribution curves for threshold and noise for a real chip on an 8 chip HDI.

(A mip gives 16,000 electrons in 200 micron)


Measured FPIX 2 Power Consumption

The power consumption of the 8 chip module is: for (VD=VA=2.5V)

1.86W Module idle.

2.26W Module collecting data.* 100 micro watt/channel

for (VD=VA=2.2V)

1.51W Module idle.

1.83W Module collecting data.* 80 micro watt/channel

* 8 chip module collecting data at 300Mbps.

The power consumption variation due temperature change (delta=100ºC) was less than 0.05 W.


Bump bonds

Programming interface

Discriminator

Pipeline

Digital interface

PHX Chip Layout:2 columns 256 channels/column3.8 mm x 13 mm = 49.4 mm2

Thinned to 150 to 200 umBump bonds on 200 um pitch50 µm dia solder bumps512 bumps plus inter-chip bumps ~ 15 wafers neededKeep all digital backend the same ! Adjust only input and geometry, optimize the row/column structure for readout speed and add pulser.

Bus on chip ? signals & power

signals & power FNAL Collaboration

Ray Yarema’s group


Kapton

PHX Bus R&D

FNAL Proposal: Power & Data Bus on Chip

200 um Silicon Detector

PHX PHXK

apton

Preliminary calculations by R.Yarema show that the I-R loss is acceptable, need optimize

number of signal lines per chip

R&D necessary …. fallback solution is

Flex Cable with Wire Bonding


FVTX Power

~3400 chips but only 80 Watts per Endcap

Numbers added for both sides !


PHX Chip Development Schedule


FVTX Wedge Assembly

3 mm carbon wedge for assembly and cooling

2 silicons in front

2 silicons in back C

arb

on F

iber

Sup

port

and

Cooling

Eliminate dead silicon areas by overlapping 1 mm along edges ….


X 24

Total strip count: ~ 2 * 860,000 stripsTotal chip count: ~ 2 * 1680 chipsTotal silicon area: ~ 2 * 3350 cm2

From Wedges to Lampshades


FVTX Connections Copper Flex (Fiber)

R&D Project: Flex Cables or Fiber to the ‘outside world’ ?

• Space Constraints (see W.Sondheim)

• Costs/Complexity/Reliability

• Serializer/Fiber Collaboration ?

6 x 512 channels

5 x 512 channels

Copper Cables

Copper Bus

LVDS 4

x 169.8 MBit Hit: 9 bit address ,3 bit adc, 4 bit chip-id, tag 8bit => 24 bits

5 x 512 channels

Fiber 4 Gbit/s

Slow Control ~100 Hz

Serializer

Optical Driver

5 x 512 channels

48 per station48 per station

61 LVDS Pairs


FVTX Copper Connection Wire Count

Per wedge: 6x2=12 wires• BCO clock• Shift In• Shift Out• Shift Control• Reset• MC

Per chip:• Data out (x1,2,4,6)• DLCLK

11 chips/wedge… assume we use DLCLK:• 1 serial pair/chip: 6 pairs+11x2 pairs = 28 pairs • 2 serial pairs/chip: 6 pairs + 11x3 pairs = 39 pairs• 4 serial pairs/chip: 6 pairs + 11x5 pairs = 61 pairs

Power and Bias

‘Round Cable’ ala CDF/D0

D.Christian Slide


FVTX Connections III

12 fibers per connector

Board(green) and fiber optic connector(orange)

R&D Project: Flex Cables or Fibers the ‘outside world’ ?

• Space Constraints (see W.Sondheim)

160 mm

30mm

24 Fiber MPO Connector (x8)

Samtech QSS-RA100 .635mm pitch Connector (7mmx54mm)


Electronics Readout Concept

Driver

Event Tag

(buffer)

FPGA

To Level 1 triggerprocessor

Copper~140 Mbits/s

PHX/FPIX2 is zero suppressed !!!

<1.5 % Occupancy in AA central

Level 1 possible

PHENIX DCM

Level 1 Accept

In Detector In Counting House

chip download

Data out

fibercopper

T&FC

Slowcontrols

Fvtx Interface Board


R&D on Data Acquisition (Number of Readout Lines, Clock Speed & FPGA Memory)

Layers Ganged

channels/chip

chips/ board

channels/ board

Occupancy

Interactions/ 64 clocks

Real Hits/ 64 Clocks

Real data size/64 clocks (kbits) Noise

Clocks

Noise Hits/ 64 Clocks

Noise data size/64 clocks (kbits)

Buffer needed for 64 clocks (kbits)

Number of Readout Lines

Readout Time/data word (nsec)

Readout Latency (beam clocks)

Noise Hits/chip needed to Fall Behind

Noise Rate/chip

Readout Clock Speed (Mbps)

1 512 11 5632 0.015 1 84.48 2.03 0.001 64 360.4 8.7 10.7 1 212.4 17.4 0.5 0.5 113

4 512 44 22528 0.015 1 337.92 8.11 0.001 64 1441.8 34.6 42.7 1 212.4 17.4 0.5 0.5 113

1 512 11 5632 0.015 1 84.48 2.03 0.001 64 360.4 8.7 10.7 2 106.2 8.7 0.9 0.5 113

4 512 44 22528 0.015 1 337.92 8.11 0.001 64 1441.8 34.6 42.7 2 106.2 8.7 0.9 0.5 113

1 512 11 5632 0.015 1 84.48 2.03 0.001 64 360.4 8.7 10.7 4 35.3 2.9 2.8 0.5 169.8

4 512 44 22528 0.015 1 337.92 8.11 0.001 64 1441.8 34.6 42.7 4 35.3 2.9 2.8 0.5 169.8

1 512 11 5632 0.015 1 84.48 2.03 0.001 64 360.4 8.7 10.7 6 35.4 2.9 2.8 0.5 113

4 512 44 22528 0.015 1 337.92 8.11 0.001 64 1441.8 34.6 42.7 6 35.4 2.9 2.8 0.5 113

R & D has started under LANL DR grant

First FVTX readout meeting (Columbia/ISU/LANL) held 12/5/2005 at BNL


FVTX DAQ INTERFACE BOARD

PHX

Conventional Copper

Cableor

Serializer/Optical Driver

Data Buffer, FPGA

Time to process=?

DCM

1,2,4,(6) lines/chip

Stream of 24-bit data words with:• Location (3 bit ADC) Beam Clock Counter

140Mbps readout lines can drive 10 m

Uses custom or commercial driver

• Buffers Data• Upon lvl1 grab relevant data • Build packet• DataDCM/Lvl1• Pass beam clock• Initialize chips

PHENIX Standard

On Silicon11?, 41?/FPGA Near Silicon Outside IR

T+FC

Trigger?

2.5 Gb/s

Arcnet (FPGA program., chip download)

• Serial download to chips • Pass beam clock• Initialize/Reset

New development of FIB and firmware (Columbia/LANL)

ISU Level 1 Board (SBIR)


The FIB Concept (FVTX Interface Board)

(with input from Chi,FNAL + Columbia)


FVTX Research & Development Silicon Detector

• Adapt/modify existing design– Straight or curved strips

PHX Chip• Low risk modification of existing design

– Analog input, row/column structure, pulser• New development

– Bus on chip

Interfacing• Flex copper cables or Fibers

– R&D

Transition Board• New development

– FVTX Interface Board (FIB) and firmware

DAQ/Slow Control

Mechanics/Cooling integrated in VTX solution• See W. Sondheim’s presentation


FVTX Summary

North and South: 4 Station Precision Silicon Tracker for the Muon Arms

BTeV (ATLAS) Technology for Detector and Readout Chip

R&D Schedule (needs to start now)

FVTX (DAQ) Interface Board with FPGA and Firmware• R &D started under LANL grant• Collaboration with Columbia/ISU

Mechanics covered in next talk

Detailed Schedule in Dave’s talk


BACKUP Slides on the FVTX


FNAL Chip Comparison

Chip

All 50 µm

spacing

Noise

Threshold σ

Ministrip Readout type

speed

Trigger possible

Power

per chan

Geometry r-phi

SVX4

128 ch

S/N -12/1 yes Pipeline

53 MHz

no 2mW yes

FSSR

128 ch

250 e

440 e

yes Data push

840 Mb

yes 3 mW Yes

FPIX3

2816 ch

220 e

125 e

no Data Push

840 Mb

yes 90 µW no

PHX

512 ch

220 e

125e

yes Data Push

840 Mb

yes 90 µW yes

Signal 24000 e for 300 µm Si Sensor, thinning desirable for small material budget


FPIX2.1 Pixel Cells 50 x 400 um

12 µm bump pads

Preamp 2nd stage+disc

ADC Kill/inject

ADCencoder

Digital interface

Flash Latch to Binary

Encoder

Thermometer

Thresholds

Vff

Test

Sensor

Command Interpreter

00 -

01 -

10 -

11 -

idle

reset

output

listen

HFastOR

RFastOR Throttle4 pairs of

Command Lines

Kill

Inject

ADC

RowAddress

Read Clock

Read Reset

Token In

Token Reset

Token Out

ThresholdVref

Resets

Bus

Controller-

+

-

+

Vdda

R.Yarema Slide


Power Considerations

Must minimize IR drops

Reduce number of chips on bus

Design full custom low power analog and digital sections

Maximize power bus size on chip

Use back side contact

Possibly use cooling structure for ground return

R.Yarema Slide


Voltage Drop Estimation

n identical units

• Units are connected as shown• Each unit consumes current• What is the IR drop at the output of the last unit?

unitunit IR

nnV

2

1

R.Yarema Slide


Runit Estimation(one chip is a unit)

mSquare

mR

Squares

mmWidth

mmmLength

unit 420670

66.52.2

8.12

2.2

8.1250256

R.Yarema Slide


Iunit Estimation

• FPIX2 uses 60mA of Analog Current and 60mA of Digital Current.• It is fairly accurate to use the FPIX2 Analog Current as an estimation of the Phoenix Mini Strip Analog Current.• It is conservative to use the FPIX2 Digital Current as an estimation of the Phoenix Mini Strip Digital Current

• Phenix Mini Strip will not read out at 840MBits/sec• Phenix Mini Strip will not have as many inputs and outputs

R.Yarema Slide


Iunit Estimation

Chip

mA6.25m 8.12m 8.12Current Total

8.12cells 51225Current Digital Phoenix""

cell253.21

cells 2816

60Current Digital FPIX2

8.12cells 512cell

25Current Analog Phoenix""

cell253.21

cell 2816

60Current Analog FPIX2

AA

mAuA

uAmA

mAuA

uAmA

R.Yarema Slide


ΔV Estimation

unitunit IR

nnV

2

1

mVmVmAmV 12052.1076.25*420

2

155

Inner Segment

Outer Segment

mVmVmAmV 17528.1616.25*4202

166

Full Tower

mVmVmAmV 60036.5916.25*702

11111

-OR-Split Tower

R.Yarema Slide


Noise Performance of FPIX2 at Higher Detector Capacitance

R.Yarema Slide


SimulatedFPIX2 first and second stage response for detector capacitancesfrom 0 to 2 pF in 0.25 pF steps

First stage

Second stage

Phenix Chip Analog Input SimulationsR.Yarema Slide


Simulated 1st and 2 nd stagerisetime (10-90%) with different detector capacitance First stage

Second stage

Phenix Chip Analog SimulationsR.Yarema Slide


Phenix Chip I/O Ideas

Separate analog and digital power buses

Should operate over wide power supply range (due to IR drops)

Common backside ground

Clocks• Input clock – 100 ns• Separate readout clock?

Serial programming interface input

Serial data output• Chip ID• Cell number?• Channel ID

Trigger input

Control line(s)

R.Yarema Slide


FPIX2 noise

at C = 0is about 60 erms

FPIX2Threshold Distribution@ Cin= 0 pfis 125 erms

FPIX2 on the Bench MeasurementsR.Yarema Slide


Pixel/Strip Sizes and Capacity

FPIX 50 x 400 um Cin = .25 pF

Phenix 50 x 2000 to 11000 um Cin = .2-1.1 pF

SVX 50 x 105 to 3x105 um Cin = 10-30 pF

Design for Phenix should be optimized for correct detector capacitance

R.Yarema Slide


First stage

Second stage

SimulatedFPIX2 first and second stage response for detector capacitancesfrom 0 to 2 pF in 0.25 pF steps

First Simulations for PHX Chip at FNALR.Yarema Slide


Possible Layout Diagram for PHX Chip

Bump bonds

Programming interface

1st and 2nd stage and discriminator

Pipeline

Digital interface

R.Yarema Slide


BACKUP Slides on the iFVTX


The Inclusive (Measurement ) FVTX aka iFVTX

sponsored by LANL-DR in FY ‘06-08

• Inclusive Heavy Quark Measurement in A-A

• 4 planes

• Existing Chips FPIX 2.1

• Existing 8 Chip Modules

• Prototype FPGA Readout


iFVTX

Aligned with Sweet Spot of Muon Half-Octant

• Constraints by barrel

• Same Volume as FVTX

• Enclosure

• Half-Octant


BTeV-Sensors at FNAL

Individual pixels are identical to ATLAS sensors.

Number of rows & columns and overall size customized for BTeV.

Each wafer contains:• 1 “4-chip” module• 3 “6-chip” modules• 3 “5-chip” modules• 2 “8-chip” modules• These are the modules used in the baseline design; number on wafer chosen to reflect usage.• 5 “1-chip” sensors

Oxygenated “moderated p-spray” n+-in-n sensors made by TESLA

G.Cardoso Slide


8 Chip Module

• Dimensions:Dimensions: 111.0mm x 11.1mm 111.0mm x 11.1mm + 2x 10.0mm x 11.1 mm tabs+ 2x 10.0mm x 11.1 mm tabs• Line width: Line width: 5050mm• Line to line clearance: Line to line clearance: 5050mm• Metal layer thickness: Metal layer thickness: 1212mm

• Number of layers: Number of layers: 4 4 • Via pad/hole: Via pad/hole: 150/70150/70mm• Lamination: Lamination: 2525m epoxym epoxy• Film thickness (polymide): Film thickness (polymide): 5050mm

HDI designed by Fermilab/CD made by Dyconex:HDI designed by Fermilab/CD made by Dyconex:

HDI CAD top layer.

HDI + 8 bare die chips.

HDI + 8 chips with detector.

(SINTEF PSPRAY)

G.Cardoso Slide


HDI TEST CARD

LANL R&D Collaboration with FNAL to get Multichip Modules in January 2006

1 Silicon with 8 readout chips on HDI Silicon from TESLA (Czech Republic)

This is a photograph !

G.Cardoso Slide


HDI to PIFC wire-bonding

…

11.1mm

8.53mm

200um

1.47mm 1mm

Data and control LV

HV pad

…

HV pad

DVDD&GNDAVDD&GND

Power PIFC

Data PIFC

Mezzanine Flex Circuit

HDI

Decoupling Capacitors and Termination Resistors

Wire Bonds Wire Bonds FPIX Chip

Sensor High Voltage

GND Data PIFC

Power PIFC

G.Cardoso Slide


Silicon Sensor

Adhesive

Layer 3

Layer 2

Bias Window

Gold Epoxy

Metal Layer 4

Metal Layer 3

Metal Layer 2

Metal Layer 1

Analog Digital

Digital lines

Ground High Voltage Fle

x C

ircu

it

Analog lines

Layer 1

Bias Pad (1mm2)

4 Layer Flex Circuit Cross Section4 Layer Flex Circuit Cross Section

BTeV Pixel - Flex Cross SectionG.Cardoso Slide


Pixel Multichip Module – Baseline Design

Readout Chip

Silicon Sensor

Flex Circuit

Support Structure

Wire bonds

G.Cardoso Slide


Prototype pixel module

FPIX2

Silicon Sensor

HDI

Support Structure

Wire bonds

HDI

Decoupling Capacitors and Termination Resistors

Wire Bonds Connector FPIX2 Chip

Sensor High Voltage

NO

T TO

SCA

LE

G.Cardoso Slide


MODULE UNDER TEST

G.Cardoso Slide


PCB

TPG

Cooling

VHDMSignals

Power

HV Bias

Pulser

iFVTX plane with Twelve 8-Chip Modules

FPIX on HDIWire Bonds

12/2005

Wire Bonded Flex Cable go to Pole Face Board


iFVTX

Two Type of Planes

8 8-chip modules

12 8-chip modules


iFVTX

3-d Layout (concept)


iFVTX Transition to the Outside WorldThe Pole Face Board

Pole Face Board• Printed Circuit Board• Feed through via multilayer

board• Flex Wire Bond Area • Outside connectors

N2

Cables come for iFVTX planes to inside connectors


Test Setup at LANLwe are working with a FNAL chip since July 2005

DVM

DAQLow Voltage

Test Board

LA Display

Logic Analyzer

Invisible: Clean Power and Scope and Pulser

Chip Response


BACKUP Slides on the FSSR Hybrid


Hybrid

Production• 4 layer BeO board, ~ 500um thick.• Gold traces, 10um thick.• 75um traces/spacing.

75mm

40mm

FSSR

DecouplingcapacitorsTermination resistors

Pigtail solder pads

Prototype• 4 layer FR4 board, ~ 1mm thick.• Copper traces, 17um thick.• 75um traces/spacing.

G.Cardoso Slide


Pigtail

Soldered to hybrid.

Connects hybrid to flex cable.

Avoids having a connector on hybrid.

2 layer, 100um traces/spacing, broadside coupled differential lines (LVDS).

ConnectorPigtail

3cm

PigtailHybrid

G.Cardoso Slide


Flex Cable

Connects pigtail to Junction Card.

Length depends on station position.

2 layer, 100um traces/spacing, broadside coupled differential lines (LVDS).

HV

HV GNDAGNDDGND

DVDD AVDD

...

...Differential pairs and sense wires

NOT TO SCALE

1cm 2.5cm 2.5cm 0.5cm

50cm

G.Cardoso Slide


Pitch AdapterG.Cardoso Slide

The FVTX Technology

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Transcript of The FVTX Technology