The Chicago Half of Champ Jean-François Genat, Eric Oberla, Herve Grabas 10/27/2015 1 3rd Chip...
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Transcript of The Chicago Half of Champ Jean-François Genat, Eric Oberla, Herve Grabas 10/27/2015 1 3rd Chip...
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The Chicago Half of Champ
Jean-François Genat, Eric Oberla, Herve Grabas
Jean-François Genat, Eric Oberla, Herve Grabas
04/20/23 13rd Chip Review
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Champ Psec Features•Psec – 3 is a test Asic. Will not provide
timing measurement. •Main features :
▫DLL (Delay Locked Loop).▫Free running delay line.▫DLL test structures.
•Test structures:▫Ring oscillator (with new D-Flip Flop).▫Transmission lines.▫Resistors.
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Overall presentation•The DLL will allow us to have a controlled
sampling rate.•Provide us a cleaner sampling window•No dead zone of sampling ( if the effective
delay free running delay line is less than the period of the input clock -> dead time)
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CMOS design
•Cell design Phase detectorCharge pumpDelay lineSome control logic
•SimulationComplicated: long locking time, small time
steps.The use of VerilogA language and mixed
signal simulation saves you.
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DLL simulation•Difficult because:
DLL function with 40ps delays.Locking take up to 100us.
• Therefore, there is more than 7 orders of magnitude of difference between the smallest time step and the biggest one.
• Solution : not simulating the internal function of the delay line.
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Delay line simulation model (1)•Delay line structure: chain of small
delays.
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Generates a sampling frequency equals to Delay
1
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Delay line simulation model (2)• From its input and output the delay line is however
nothing else than a big delay adjustable by to voltages : VCN and VCP.
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Delay line simulation (3)•VerilogAMS description of the VCDL:
Allow us to describea variable delay.
Description uses postlayout results from Eric
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DLL simulation success04/20/233rd Chip Review
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Delay Locked Loop principle1. VCN and VCP are set to their max value (1.2 & 0
resp.). The propagation delay in the DLL is then the smallest -
> 11ns.2. The delay is increased until it reaches the delay of
one clock cycle.3. The phase comparator locks then the delay of the
delay line at one clock cycle
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Delay locked loop control logic• In a delay locked loop the generated delay of the delay line
cannot reach 0. It is always minored by the smallest delay of the line. Here 11ns.
• Therefore, the DLL can never lock on the first edge of the clock. (See Fig.)
• However the phase comparator work at ±180° around a clock edge. And in some case this can result in the DLL trying to lock on the first edge of the clock (See Fig.)
• This has to be taken care of. Some simple logic is sufficient.
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DLL control logic (2)
• The control logic outputs 1 if VDLL is in the wrong pull-in range.
• After having being active the pull-out logic is inactivated. (The DLL can only be in the wrong pull-in range once).
• The control logic operates directly on the phase comparator to preserve its speed.
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Dynamic phase comparator04/20/233rd Chip Review
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• It is a dynamic phase comparator so it is extremely fast. Therefore it gives us very accurate jitter correction.
• Adjusted to give us directly the right control signal for the charge pump. (No extra inverted needed).
• Shift logic integrated.
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Charge pump
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• High performance charge pump.
• 1uA external current source.
• Cascode current mirror to increase output resistance, so that charging and discharging current are not disturbed by the state of the output. (Better current matching).
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Results
•Successful simulation and locking pre and post layout.
•Lock time ~ 10 us.•Simulation time ~10 min.•Measured jitter 300fs in post-layout
simulation with the behavioral model of the DLL (will probably increase in the physical design).
•DLL system is stable and precise.
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Chip layout
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•Submitted to CERN May 31st.
•30 units ordered.
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Backup slides
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Delay locked loop04/20/233rd Chip Review
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•Whole schematic circuit with the control logic.
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Layout: Charge pump & Phase detector
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•Layout of the charge pump and phase detector done together for better matching and smallest wiring capacitances.
•16um x 18um
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Layout Control logic
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Results (2): The pull-out
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Pull-out control signal
Decrease in VCN -> Increase in delay.
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Results (3) : The locking
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Small UP and DOWN control signal. Locking almost complete.
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Results (4) : The jitter
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Very low delay variations at the output of the delay line