Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Systems Lecture # 6...
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Transcript of Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Systems Lecture # 6...
Introduction to VLSI Design – Lec01.
Chapter 1Introduction to VLSI Systems
Lecture # 6 Computer-Aided Design Technology for VLSI
Introduction to VLSI Design – Lec01.
Example 1VHDL Digital Half ADDER Logic Program
• VHDL program for “Half Adder” behavioral design in Xilinx integrated software environment-
-- Company: Wilberforce University
-- reference: http://vhdlprograms.blogspot.com/2012/04/vhdl-digital-half-adder-logic-program.html
-- Design Name: Half Adder Design
-- Module Name:HalfAdder1 - Behavioral
-- Project Name: VHDL Program for "Half Adder”
-- Tool versions: XST(VHDL/Verilog)
--------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Introduction to VLSI Design – Lec01.
entity HalfAdder1 is
Port ( X : in std_logic;
Y : in std_logic;
SUM : out std_logic;
CARRY : out std_logic);
end HalfAdder1;
architecture Behavioral of HalfAdder1 is
begin
Process (X,Y)
begin
SUM <= X XOR Y;
CARRY<=X AND Y;
end process;
end Behavioral;
Introduction to VLSI Design – Lec01.
VHDL program for “Half Adder” architectural design in Xilinx integrated software environment-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Introduction to VLSI Design – Lec01.
entity HalfAdder2 is
Port ( X : in std_logic;
Y : in std_logic;
SUM : out std_logic;
CARRY: out std_logic);
end HalfAdder2;
architecture HalfAdder2_arch of HalfAdder2 is
begin
process(X,Y)
begin
if(X/=Y) then
SUM<='1';
else
SUM<='0';
end if;
end process;
Introduction to VLSI Design – Lec01.
process(X,Y)
begin
if((X='1') and (Y='1')) then
CARRY<='1';
else
CARRY<='0';
end if;
end process;
end HalfAdder2_arch;
Introduction to VLSI Design – Lec01.
Alternative way _ Half Adder -- Author : http://www.teahlab.com/
-- Circuit: Half Adder
-- Note : This VHDL program is a structural description of -- the interactive Half Adder on teahlab.com. The
-- program shows every gate in the circuit and the
-- wires linking the gates. It is very important to
-- learn structural design (RTL) strategies because
-- as your assignments become larger and larger,
-- knowledge of register transfer level (RTL) design
-- strategies become indispensable.
-- Here we define the AND gate that we need for
-- the Half Adder
Introduction to VLSI Design – Lec01.
Alternative way _ Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B;
end func;
Introduction to VLSI Design – Lec01.
--*=======================================
-- Here we define the XOR gate that we need for
-- the Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity xorGate is
port( A, B : in std_logic;
F : out std_logic);
end xorGate;
architecture func of xorGate is
begin
F <= A xor B;
end func;
Introduction to VLSI Design – Lec01.
--*===========================================
-- At this point we construct the half adder using
-- the AND and XOR gates
library ieee;
use ieee.std_logic_1164.all;
entity halfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end halfAdder;
architecture halfAdder of halfAdder is
component andGate is -- import AND Gate
port( A, B : in std_logic;
F : out std_logic);
end component;
Introduction to VLSI Design – Lec01.
component xorGate is -- import XOR Gate
port( A, B : in std_logic;
F : out std_logic);
end component;
begin
G1 : xorGate
port map(A, B, sum);
G2 : andGate
port map(A, B, Cout);
end halfAdder;
Introduction to VLSI Design – Lec01.
Test Bench:------------------------------------------------------------- --
-- Author : http://www.teahlab.com/
-- Program: Half Adder Testbench
-- -- Note : A testbench is a program that defines a series
-- of tests to verify the operation of a circuit:
-- in this case, the Half Adder.
-- -- Two important notes about this test bench:
-- 1] The testbench takes no inputs and returns
-- no outputs. As such the ENTITY declaration -- is empty. –
-- 2] The circuit under verification, here the
-- Half Adder, is imported into the testbench
-- ARCHITECTURE as a component. --------------------------
Introduction to VLSI Design – Lec01.
--import std_logic from the IEEE library library ieee; use ieee.std_logic_1164.all; entity halfAdder_tb is end halfAdder_tb; architecture tb of halfAdder_tb is component halfAdder is port( A, B : in std_logic;
sum, Cout : out std_logic); end component; signal A, B, sum, Cout: std_logic; begin mapping: halfAdder
port map(A, B, sum, Cout); process variable errCnt : integer := 0;
begin --TEST 1 A <= '0'; B <= '1';
wait for 10 ns;assert(sum = '1') report "sum error 1" severity error; assert(Cout = '0') report "Cout error 1" severity error;
Introduction to VLSI Design – Lec01.
if(sum /= '1' or Cout /= '0') then errCnt := errCnt + 1;
end if;
--TEST 2
A <= '1'; B <= '1';
wait for 10 ns;
assert(sum = '0') report "sum error 2" severity error;
assert(Cout = '1') report "Cout error 2" severity error;
if(sum /= '0' or Cout /= '1') then errCnt := errCnt + 1;
end if; --TEST 3 A <= '1'; B <= '0';
wait for 10 ns;
assert(sum = '1') report "sum error 3" severity error;
assert(Cout = '0') report "Cout error 3" severity error;
if(sum /= '1' or Cout /= '0') then errCnt := errCnt + 1;
end if;
Introduction to VLSI Design – Lec01.
---- SUMMARY
---- if(errCnt = 0) then
assert false report "Success!" severity note;
else assert false report "Faillure!" severity note;
end if;
end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of halfAdder_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END ----------------------------------------------------------------END
Introduction to VLSI Design – Lec01.
Behavior Examplearchitecture behav of reg4 isbegin
storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
beginif en = '1' and clk = '1' then
stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;
end if;q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;
wait on d0, d1, d2, d3, en, clk;end process storage;
end architecture behav;
Introduction to VLSI Design – Lec01.
VHDL-87
• Omit architecture at end of architecture body
• Omit is in process statement header
architecture behav of reg4 isbegin
storage : process...
begin...
end process storage;end behav;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 18
Structure Example
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
d_latch
d
clk
q
bit1
d_latch
d
clk
q
bit2
d_latch
d
clk
q
bit3
d_latch
d
clk
q
gate
and2
a
b
y
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 19
Structure Example
• First declare D-latch and and-gate entities and architectures
entity d_latch isport ( d, clk : in bit; q : out bit );
end entity d_latch;
architecture basic of d_latch isbegin
latch_behavior : process isbegin
if clk = ‘1’ thenq <= d after 2 ns;
end if;wait on clk, d;
end process latch_behavior;
end architecture basic;
entity and2 isport ( a, b : in bit; y : out bit );
end entity and2;
architecture basic of and2 isbegin
and2_behavior : process isbegin
y <= a and b after 2 ns;wait on a, b;
end process and2_behavior;
end architecture basic;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 20
Structure Example
• Now use them to implement a register
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 );
bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 );
bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 );
bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 );
gate : entity work.and2(basic)port map ( en, clk, int_clk );
end architecture struct;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 21
VHDL-87
• Can’t directly instantiate entity/architecture pair• Instead
– include component declarations in structural architecture body
• templates for entity declarations
– instantiate components– write a configuration declaration
• binds entity/architecture pair to each instantiated component
Introduction to VLSI Design – Lec01.
Structure Example in VHDL-87
• First declare D-latch and and-gate entities and architectures
entity d_latch isport ( d, clk : in bit; q : out bit );
end d_latch;
architecture basic of d_latch isbegin
latch_behavior : processbegin
if clk = ‘1’ thenq <= d after 2 ns;
end if;wait on clk, d;
end process latch_behavior;
end basic;
entity and2 isport ( a, b : in bit; y : out bit );
end and2;
architecture basic of and2 isbegin
and2_behavior : processbegin
y <= a and b after 2 ns;wait on a, b;
end process and2_behavior;
end basic;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 23
Structure Example in VHDL-87
• Declare corresponding components in register architecture body
architecture struct of reg4 is
component d_latchport ( d, clk : in bit; q : out bit );
end component;
component and2port ( a, b : in bit; y : out bit );
end component;
signal int_clk : bit;
...
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 24
Structure Example in VHDL-87
• Now use them to implement the register
...
begin
bit0 : d_latchport map ( d0, int_clk, q0 );
bit1 : d_latchport map ( d1, int_clk, q1 );
bit2 : d_latchport map ( d2, int_clk, q2 );
bit3 : d_latchport map ( d3, int_clk, q3 );
gate : and2port map ( en, clk, int_clk );
end struct;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 25
Structure Example in VHDL-87
• Configure the register model
configuration basic_level of reg4 is
for struct
for all : d_latchuse entity work.d_latch(basic);
end for;
for all : and2use entity work.and2(basic)
end for;
end for;
end basic_level;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 26
Mixed Behavior and Structure
• An architecture can contain both behavioral and structural parts– process statements and component instances
• collectively called concurrent statements
– processes can read and assign to signals
• Example: register-transfer-level model– data path described structurally– control section described behaviorally
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 27
Mixed Example
shift_reg
reg
shift_adder
control_section
multiplier multiplicand
product
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 28
Mixed Example
entity multiplier isport ( clk, reset : in bit;
multiplicand, multiplier : in integer;product : out integer );
end entity multiplier;
architecture mixed of mulitplier is
signal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;
begin
arith_unit : entity work.shift_adder(behavior)port map ( addend => multiplicand, augend => full_product,
sum => partial_product,add_control => arith_control );
result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,
en => result_en, reset => reset );
...
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 29
Mixed Example
…
multiplier_sr : entity work.shift_reg(behavior)port map ( d => multiplier, q => mult_bit,
load => mult_load, clk => clk );
product <= full_product;
control_section : process is-- variable declarations for control_section-- …
begin-- sequential statements to assign values to control signals-- …wait on clk, reset;
end process control_section;
end architecture mixed;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 30
Test Benches
• Testing a design by simulation
• Use a test bench model– an architecture body that includes an instance of
the design under test– applies sequences of test values to inputs– monitors values on output signals
• either using simulator
• or with a process that verifies correct operation
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 31
Test Bench Example
entity test_bench isend entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process isbegin
d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns;en <= ’1’; wait for 20 ns;clk <= ’1’; wait for 20 ns;d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns;en <= ’0’; wait for 20 ns;…wait;
end process stimulus;
end architecture test_reg4;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 32
Regression Testing
• Test that a refinement of a design is correct– that lower-level structural model does the same as a
behavioral model
• Test bench includes two instances of design under test– behavioral and lower-level structural– stimulates both with same inputs– compares outputs for equality
• Need to take account of timing differences
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 33
Regression Test Example
architecture regression of test_bench is
signal d0, d1, d2, d3, en, clk : bit;signal q0a, q1a, q2a, q3a, q0b, q1b, q2b, q3b : bit;
begin
dut_a : entity work.reg4(struct)port map ( d0, d1, d2, d3, en, clk, q0a, q1a, q2a, q3a );
dut_b : entity work.reg4(behav)port map ( d0, d1, d2, d3, en, clk, q0b, q1b, q2b, q3b );
stimulus : process isbegin
d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns;en <= ’1’; wait for 20 ns;clk <= ’1’; wait for 20 ns;…wait;
end process stimulus;
...
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 34
Regression Test Example
…
verify : process isbegin
wait for 10 ns;assert q0a = q0b and q1a = q1b and q2a = q2b and q3a = q3b
report ”implementations have different outputs”severity error;
wait on d0, d1, d2, d3, en, clk;end process verify;
end architecture regression;
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 35
Design Processing
• Analysis
• Elaboration
• Simulation
• Synthesis
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 36
Analysis
• Check for syntax and semantic errors– syntax: grammar of the language– semantics: the meaning of the model
• Analyze each design unit separately– entity declaration– architecture body– …– best if each design unit is in a separate file
• Analyzed design units are placed in a library– in an implementation dependent internal form– current library is called work
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 37
Elaboration
• “Flattening” the design hierarchy– create ports– create signals and processes within architecture body– for each component instance, copy instantiated
entity and architecture body– repeat recursively
• bottom out at purely behavioral architecture bodies
• Final result of elaboration– flat collection of signal nets and processes
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 38
Elaboration Example
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
d_latch
d
clk
q
bit1
d_latch
d
clk
q
bit2
d_latch
d
clk
q
bit3
d_latch
d
clk
q
gate
and2
a
b
y
reg4(struct)
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 39
Elaboration Example
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
bit1
bit2
bit3
gate
reg4(struct)d_latch(basic)
d
clk
q
d_latch(basic)
d
clk
q
d_latch(basic)
d
clk
q
d_latch(basic)
d
clk
q
and2(basic)
a
b
yprocess with variables
and statements
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 40
Simulation
• Execution of the processes in the elaborated model
• Discrete event simulation– time advances in discrete steps– when signal values change—events
• A processes is sensitive to events on input signals– specified in wait statements– resumes and schedules new values on output signals
• schedules transactions
• event on a signal if new value different from old value
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 41
Simulation Algorithm
• Initialization phase– each signal is given its initial value– simulation time set to 0– for each process
• activate
• execute until a wait statement, then suspend– execution usually involves scheduling transactions on signals
for later times
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 42
Simulation Algorithm
• Simulation cycle– advance simulation time to time of next transaction– for each transaction at this time
• update signal value– event if new value is different from old value
– for each process sensitive to any of these events, or whose “wait for …” time-out has expired
• resume• execute until a wait statement, then suspend
• Simulation finishes when there are no further scheduled transactions
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 43
Synthesis
• Translates register-transfer-level (RTL) design into gate-level netlist
• Restrictions on coding style for RTL model
• Tool dependent– see lab notes
Introduction to VLSI Design – Lec01.
© 1998, Peter J. Ashenden
VHDL Quick Start 44
Basic Design Methodology
Requirements
SimulateRTL Model
Gate-levelModel
Synthesize
Simulate Test Bench
ASIC or FPGA Place & Route
TimingModel Simulate