Feb 4, 2008 E0-286@SERC 1

VLSI Testing ATPG Algorithms

VLSI Testing ATPG Algorithms

Virendra SinghIndian Institute of Science (IISc)

Bangalorevirendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture - 8

Feb 4, 2008 E0-286@SERC 2

ATPGATPG

Path Sensitization Method Fault Sensitization Fault Propagation Line Justification

Path Sensitization Algorithms D- Algorithm (Roth) PODEM (P. Goel) FAN (Fujiwara) SOCRATES (Schultz) SPIRIT (Emil & Fujiwara)

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Path Sensitization Path Sensitization

General Structure of TG Algorithm

beginset all values to xJustify (l, v)if (v = 0) then Propagate (l, D)else Propagate (l, D)

end

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Path SensitizationPath SensitizationJustify( l, val)begin

set l to valif l is a PI then return/* l is a gate output */c = controlling value of li = inversion of linval = val

iif (inval = c)

then for every input j of lJustify (j, inval)

else select one input ( j ) of lJustify (j, inval)

end

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Path SensitizationPath SensitizationPropagate (l, err)/* err is D or D */begin

set l to errif l is PO then RETURNk = fanout of lc = controlling value of ki = inversion of kfor every input of j of k other than l

Justify ( j, c )Propagate ( k, err i )

end

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Path SensitizationPath Sensitization

DD

Justify (a, 1)

Justify (b, 1)

1

1

Propagate (d, D)

Propagate (f, D)

Justify (e, 0)Justify (c, 1)

D0

1

SA0

Justify (d, 1)

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Common Concept Common Concept Fault Activation problem a LJ Problem The Fault Propagation problem

1. Select a FP path to PO Decision2. Once the path is selected a set of LJ

problems The LJ Problems Decisions or Implications

To justify c = 1 a = 1, b = 1 (Implication)To justify c = 0 a = 0 or b = 0 (Decision)

Incorrect decision Backtrack Another decision

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D-Algorithm Roth IBM

(1966)

D-Algorithm Roth IBM

(1966) Fundamental concepts invented:

First complete ATPG algorithm D-Calculus (5 valued logic) Implications forward and backward Implication stack Backtrack Test Search Space

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Decisions during FPDecisions during FP

D111

0

10

0

10

D

D

D frontier: The set of all gates whose output value is currently x but have one or more fault signals on their inputs

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Decisions during LJ Decisions during LJ

D

0

111

0

00

111

1

00

J Frontier : A set of all gates whose output value is known but not implied by its input value

11 D

1

1

D

111

D

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Implications (Forward) Implications (Forward)

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Thank YouThank You

VLSI Testing ATPG AlgorithmsATPGPath Sensitization Path SensitizationPath SensitizationPath SensitizationCommon Concept D-Algorithm Roth IBM(1966)Decisions during FPDecisions during LJ Implications (Forward) Thank You