Feb 15, 2008 E0-286@SERC 1

VLSI Testing Testability Analysis

VLSI Testing Testability Analysis

Virendra SinghIndian Institute of Science (IISc)

Bangalorevirendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture - 11

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Controllability ExamplesControllability Examples

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Controllability ExamplesControllability Examples

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Observability ExamplesObservability ExamplesTo observe a gate input:Observe output and make other input values non-controlling

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Observability ExamplesObservability ExamplesTo observe a fanout stem:Observe it through branch with best observability

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Levelization Algorithm Levelization Algorithm Label each gate with max # of logic levels from primary inputs or with max # of logic levels from primary outputAssign level # 0 to all primary inputs (PIs)For each PI fanout:

Label that line with the PI level number, &Queue logic gate driven by that fanout

While queue is not empty:Dequeue next logic gateIf all gate inputs have level #’s, label the gate with the maximum of them + 1;Else, requeue the gate

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Controllability - Level 0Controllability - Level 0

Circled numbers give level number. (CC0, CC1)

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Controllability - Level 2Controllability - Level 2

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Combinational ControllabilityCombinational Controllability

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Observability for Level 1Observability for Level 1

Number in square box is level from primary outputs (POs).(CC0, CC1) CO

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Observabilities - Level 2Observabilities - Level 2

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Select path s – Y for fault propagation

sa1

Example (PODEM) Example (PODEM)

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Initial objective: Set r to 1 to sensitize fault

1

sa1

Example -- Step 2 s sa1Example -- Step 2 s sa1

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Example -- Step 3 s sa1Example -- Step 3 s sa1Backtrace from r

1

sa1

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Example -- Step 4 s sa1Example -- Step 4 s sa1Set A = 0 in implication stack

10

sa1

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Example -- Step 5 s sa1Example -- Step 5 s sa1Forward implications: d = 0, X = 1

1

sa1

00

1

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Example -- Step 6 s sa1Example -- Step 6 s sa1Initial objective: set r to 1

1

sa1

00

1

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Example -- Step 7 s sa1Example -- Step 7 s sa1Backtrace from r again

1

sa1

00

1

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Example -- Step 8 s sa1Example -- Step 8 s sa1Set B to 1. Implications in stack: A = 0, B = 1

1

sa1

00

1

1

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D

Example -- Step 9 s sa1Example -- Step 9 s sa1Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1

1

sa1

1

0

11

DD

1

0

10

1

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Backtrack -- Step 10 s sa1Backtrack -- Step 10 s sa1X-PATH-CHECK shows paths s – Y and s – u – v –Z blocked (D-frontier disappeared)

1

sa1

00

1

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Step 11 -- s sa1Step 11 -- s sa1Set B = 0 (alternate assignment)

1

sa1

0

0

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Backtrack -- s sa1Backtrack -- s sa1

1sa1

00

1

0 1

0

1

01

0 1

Forward implications: d = 0, X = 1, m = 1, r = 0,s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.

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Step 13 -- s sa1Step 13 -- s sa1Set A = 1 (alternate assignment)

1

sa1

1

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Step 14 -- s sa1Step 14 -- s sa1Backtrace from r again

1

sa1

1

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Step 15 -- s sa1Step 15 -- s sa1Set B = 0. Implications in stack: A = 1, B = 0

1

sa1

1

0

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Backtrack -- s sa1Backtrack -- s sa1Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack

sa1

1

0

0

0

1

1

1

11

0

01

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Step 17 -- s sa1Step 17 -- s sa1Set B = 1 (alternate assignment)

1

sa1

1

1

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Fault Tested - Step 18Fault Tested - Step 18Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D

1

sa1

1

11

1

0

D

0

D

D

XD

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Example (D-Algo)Example (D-Algo)Primitive D-cube of Failure

1

Dsa1

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Example – Step 2Example – Step 2Propagation D-cube for v

1

0sa1 D

D

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Example – Step 2Example – Step 2Forward & Backward Implications

1

Dsa1

0D

D

1 1

0

11

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Example – Step 3 s sa1Example – Step 3 s sa1Propagation D-cube for Z – test found!

1

Dsa1

0D

D

1 1

0

11

1D

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Thank YouThank You