T1.3: Annual workshop on application specific ... · D1.4 R&D ACCESS FP7-2009-246633 Page 1 Project...

D1.4 R&D ACCESS

FP7-2009-246633

Project acronym: R&D ACCESS

Project title Access to research results on semiconductor design

Project funded by the EC within the Seventh Framework

Project number: ICT-2009-24663

Project duration: 01.10.2009 through 31.10.2012

Project partners: Technoconsult ApS, DK (coordinator) Design And Reuse S.A., FR COREP, IT edacentrum GmbH, DE CEA-LETI, FR

Task: T1.3: Annual workshop on application specific nanoelectronics platforms

Deliverable Number D1.4

Deliverable Title Proceedings from annual workshop

Nature: Report

Dissemination level Public

Delivery date: 30.07.2012

Covered period: 01.10.2009 – 30.07.2012

Authors: Ivan Ring Nielsen (TC)

Lead beneficiary number: 1

Lead beneficiary: Technoconsult

Contact: Ivan Ring Nielsen Tel: +45 2212 5244 Fax: +45 4576 5708 email: [email protected]

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Work Plan Time Deadline Task Partner Deliverable /

Results T1.3: Annual workshop on

application specific nanoelectronics platforms

TC, COREP

14.03.2012 Presentation and discussion of workshop concept with hands-on demos (during DATE, Dresden)

TC Draft contents and setup

02.04.2012 Arrange workshop venue at Minatec CEA

30.05.2012 Promotion material (update of posters plus lay-out of new supporting poster)

TC Posters, etc.

18.06.2012 Stand preparation (posters, PC, screen, flyers, etc.)

CEA Stand

21.06.2012 Workshop organization CEA

30.06.2012 Draft D1.4 TC Report rev. 2

10.08.2012 Final D1.4 COREP, TC

Final Report

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Table of Contents 1. Introduction ....................................................................................................................... 4 2. Workshop objectives ......................................................................................................... 4 3. Workshop follow-up ........................................................................................................... 6 4. Conclusions ....................................................................................................................... 7 Annex 1: Workshop posters ..................................................................................................... 8 Annex 2: List of participants ................................................................................................... 11 Annex 3: Programme for European Nanoelectronics Design Technology Conference ......... 13 Annex 4: List of FP7/ARTEMIS/ENIAC projects invited to join R&D ACCESS ...................... 15 Annex 5: Presentation slides from the workshop ................................................................... 18

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1. Introduction An annual workshop disseminating knowledge on the services of the R&D ACCESS platform will be organised in different places in Europe. The workshop will stimulate the adaptation and introduction of new design flows supporting the advanced nanoelectronics processes. In order to attract more participants to these workshops it will be sought organised as part of similar events like the European Workshop for Microelectronics Education (EWME), European Association for Education in Electrical and Information Engineering (EAEEIE) or Design, Automation & Test in Europe (DATE). A first R&D ACCESS workshop was successfully organized on 30 June, 2011 in Grenoble. The presentations provided the project partners with fruit for sought in the organization and set-up of the R&D ACCESS services. The direct and immediate input included:

The startups identified by EDXACT and Satin Technologies were invited to join R&D ACCESS

Magillem’s work on new design methodologies was included in R&D ACCESS platform

Inclusion of IP embedded software to be considered by R&D ACCESS Inclusion of smart multicore platforms in the design methodologies section New training courses arising from the Swiss Nano-Tera programme were included in

the training platform The second workshop was organized on 21-22 June 2012 in Grenoble.

2. Workshop objectives The workshop was organized as a parallel event to the European Nanoelectronics Design Technology Conference (DTC). The R&D ACCESS event was organized as a workshop, i.e. offering the participants of DTC hands-on access to exploit the R&D ACCESS service. Additionally, a workshop on Memories was organized at the same premises on the first day. All in all these technical sessions provided an audience of nearly 150 persons from the user communities of R&D ACCESS (the list of participants for the DTC event is presented in Annex 2). The R&D ACCESS presentations and exercises were organized in six time slots, i.e.: Thursday, 21 June 10:30 – 11.00 12:30 – 14.00 15:30 – 16.00 Friday, 22 June 10:30 – 11.00 12:30 – 14.00 Most of the participants in the DTC conference and in the Memories workshop were considered to include the R&D ACCESS content providers, i.e. R&D project managers.

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Therefore the focus of the R&D ACCESS presentations was on the benefits offered to the content providers. The two promotion posters developed for the purpose of the DATE conference were used for general introduction to R&D ACCESS. A new poster was developed specifically for the workshop (see posters in Annex 1). The intention of the third poster is to show that more than 70 FP7, ENIAC and ARTEMIS partners have already taken advantage of utilizing R&D ACCESS for the dissemination of more than 2.000 R&D results by means of IP, training, tools and methodologies. 56% of the contributors are from industry (see below figure).

Figure 1: Number of R&D ACCESS content providers from various states

The workshop participants were introduced to the problems that R&D ACCESS aims to solve, i.e. R&D results are scattered among several 100s of EU projects, most projects have a life time of 3 years, after completion project websites tend to dry out and several project results are IPR protected. The objective of the R&D ACCESS project is to identify R&D results on semiconductor design from FP7 projects and to provide these results to partners from outside the consortia. The solution proposed by R&D ACCESS is to make use of existing knowledge platforms like EDA Tools, EuroTraining, Design & Reuse. The R&D ACCESS project provides a dissemination platform facilitating the access to project results generated in huge numbers of IP, NoE, STREP and CSA projects. The key advantage of the R&D ACCESS consortium is that the partners are already leading their respective area of dissemination. This means that the dissemination platform is build on existing infrastructures that have proven their commercial as well as academic vitality. Combining these four platforms under a common ACCESS infrastructure with state-of-the-art web features like the use of taxonomy provide a unique results dissemination forum for FP7 project results. As a result of this integrating approach the initial service include information on more than 500 annual nanoelectronics training courses, 15.000 updated IP/SoC products and information on more than 140 design tools developed within European projects. Another benefit from joining existing knowledge providers is the access to a common user database of nearly 40.000 subscribers.

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Figure 2: The booth lay-out (lap-top not shown)

A new feature established by R&D ACCESS is the design methodology catalogue. A design methodology is the process and the set of techniques of using specific tools and IP to design, validate and test systems. However, design methodologies are generally strongly related to the environment where they are defined or used (applicative domain, target implementation, special characteristics, etc.). The database proposes a structure to organize the relevant results on design methodologies. The slides presented during the workshop are amended in Annex 5.

3. Workshop follow-up In order to make a follow-up from the workshop a mail-out was organized on 27 June. The mail was targeting the coordinators of ongoing FP7, ARTEMIS and ENIAC projects (see the list of projects in Annex 4). The mail text is shown below

Dear FP7 coordinator,

We have been asked by the Nanoelectronics Unit of the European Commission to set up a service offering access to FP7 research results on semiconductor design. The web service already contains information from more than 70 FP7, ENIAC and ARTEMIS partners who have taken advantage of utilizing the R&D ACCESS platform for the dissemination of R&D results by means of IP, training, design tools and design methodologies. This service has been established on top of already existing knowledge providers like Design & Reuse (for IP), edacentrum (for EDA tools) and EuroTraining (for training). All together this combined service offers access to more than 20.000 training courses, IP blocks, EDA tools and design methodologies.

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We kindly ask you to consider using the R&D ACCESS service available at www.rd-access.eu in order for you to make your R&D results visible to the whole European semiconductor design community. The appearance on R&D ACCESS will also ensure that your R&D results are kept alive after project completion. SUBMIT YOUR RESULTS NOW – GO TO WWW.RD-ACCESS.EU Yours sincerely Ivan Ring Nielsen R&D ACCESS Coordinator The R&D ACCESS members are: Design And Reuse SA, Grenoble, France edacentrum GmbH, Hannover, Germany COREP, Torino, Italy CEA-LETI, Grenoble, France Technoconsult ApS, Copenhagen, Denmark

The feed-back from the mail shot is currently being analyzed. A mail-out to the list of nearly 40.000 R&D ACCESS users is planned in September.

4. Conclusions The second R&D ACCESS workshop was successfully organized on 21 – 22 June, 2012 in Grenoble. Nearly 150 persons from the content provider community had a chance to experience and discuss the R&D ACCESS services. Following the workshop an invitation mail has been send to the 134 FP7/ARTEMIS and ENIAC project coordinators. An dissemination mail will be send out in September to nearly 40.000 potential R&D ACCESS users.

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Annex 1: Workshop posters

ICT‐2009‐246633

R&D ACCESSAccess to Research Results on Semiconductor Design

Partners:Technoconsult ApS, Denmark, Ivan Ring NielsenDesign And Reuse S.A., France, Gabriele SaucierConsorzio per la Ricerca e l’Educazione Permanente, Italy, Danilo Demarchiedacentrum GmbH, Germany, Andreas VörgCommissariat à l’énergie atomique, France, Diego Puschini

Contact:info@rd‐access.eu

EUREKA

JTI EPoSSJTI ARTEMIS

JTI ENIAC

FP6

ACCESS

Training

Promotion

FP7

National programme n

National programme 3



Large Industry(Mature design flow, application oriented)

Methods

EDA IP

Promotion

Promotio

nPromotion

KNOWLEDGEPROVIDERS

KNOWLEDGEUSERS

SMEs(Open Sourcedesign flow)

Academia(Open source,

Immature methods)

• More than 400 training courses per year• Provided by 71 professional training providers • More than 200.000 montlhy hits• Nearly 10.000 European training subscribers.

• More than 70 EDA members• Information on 450 different EDA projects• Nearly 12.500 EDA experts• Over 6.800 EDA publications

• Covering SoC, MPSoC, NoC, SiP and FPGA• Identification of new design methodologies • Benchmarking of design methodologies• Classification of advanced and mature methods

• Intellectual Properties public web portal• 15.000 updated IP/SoC product descriptions• 150 companies with partnership agreement • Weekly IP/SoC News reaches 25.000 subscribers

ACCESS

Training: EDA tools:

IP: Methods:

w w w . r d – a c c e s s . e u

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ICT‐2009‐246633


The objective of R&D ACCESS is to identify R&D results on semiconductor design from FP7 projects and to providethese results to partners from outside the consortia.The R&D results are divided into four categories:‐ Training and Education‐ Intellectual Properties‐ Design Methodologies‐ EDA Tools

What are the benefits for the user? • ACCESS to European R&D knowledge infrastructure with initially more than 20.000items on training, IPs, tools and methodologies

• ACCESS to one‐stop‐shop with single sign‐on forsemiconductor design knowledge

• ACCESS to annual workshops on applicationspecific nanoelectronics platforms supporting thedesign in advanced processes

What are the benefits for the provider? • A pan European dissemination platform• Mailing lists reaching >40.000 semiconductordesigners

• Support for design flow integration including training, IP, EDA tools and design methodologies

w w w . r d – a c c e s s . e u

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Call for contributions

ICT‐2009‐246633




Submit your results now – go to www.rd‐access.eu

More than 70 FP7, ENIAC and ARTEMIS partners have already taken advantage of utilising R&D ACCESS for the disseminationof more than 2.000 R&D results by meansof IP, training, tools and methodologies. 56% of the contributors are from industry. 0

5

10

15

AT BE CH DE DK ES FR IE IT NL NO SE UK

Originof contributors

Your advantages:

‐ Searchability ‐ your training, IP, tools and methodologiescan be searched from a database with more than 20.000R&D results originating from FP7, ARTEMIS, ENIAC, etc.

‐ Visibility ‐ your R&D results are presented in astructured database with training, IP, tools andmethodologies

‐ One‐stop‐shop for semiconductor design knowledge,i.e. a single “CORDIS like” service with technical content

• Make your R&D results visible

• Make use of a pan Europeandissemination platform

• Keep your R&D results aliveafter project completion

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Annex 2: List of participants

JOSE LUIS Conesa ZARAGOZA Spain [email protected]

COPPOLA Marcello Grenoble cedex France [email protected]

JANTSCH Axel Kista Sweden [email protected]

DESVOIVRES Latifa meylan France [email protected]

MERKUS Paul Eindhoven Netherlands [email protected]

VEELENTURF Kees Nijmegen Netherlands [email protected]

DE FOUCAULD Emeric GRENOBLE France [email protected]

SCANNELL Mark Grenoble France [email protected]

PROUVEE Jerome Grenoble France [email protected]

BERNARD Serge HERAULT France [email protected]

DIETRICH Manfred Dresden Germany [email protected]

LE GALL Herve GRENOBLE France [email protected]

HAASE Juergen Hannover Germany [email protected]

PETSCHACHER Reinhard Villach Austria [email protected]

KOCH Heinz Peter Paris France [email protected]

AZIMANE Mohamed Eindhoven Netherlands [email protected]

RAHIM Fahim Grenoble cedex 9 France [email protected]

PAUTOU Nazila Bernin France [email protected]

BOULAS Christophe Grenoble France [email protected]

DELCARRI Jean-Luc Saint Martin France [email protected]

EINWICH Karsten Dresden Germany [email protected]

DEBES Eric Palaiseau France [email protected]

MARTIN François Grenoble France [email protected]

SCHROPFER Gerold Villebon France [email protected]

KIMMICH Georg Grenoble France [email protected]

LENGRAND Fabrice Grenoble France [email protected]

DRUILHE François Grenoble France [email protected]

ROUSSELOT Florent Grenoble France [email protected]

CASTILLEJO Armand Grenoble France [email protected]

ERRACHIDI Abdellah Grenoble France [email protected]

VIATTE Bruno Grenoble France [email protected]

GUERIN Vincent Grenoble France [email protected]

LECOMTE Stéphane Grenoble France [email protected]

LABAN Philippe Grenoble France [email protected]

SERRAZ Philippe Grenoble France [email protected]

FARRUGIA Ruth Grenoble France [email protected]

DECROUEZ Christelle Grenoble France [email protected]

ROUSSET Denis Grenoble France [email protected]

BLOUET Patrick Grenoble France [email protected]

BOULAS Christophe Grenoble France [email protected]

PHEULPIN Sylvie Crolles France [email protected]

CENNI Fabio Crolles France [email protected]

THOMAS Dominque Crolles France [email protected]

HIRT Peter Grenoble France [email protected]

SOULIE Michael Grenoble France [email protected]

DUBOIS Florentine Grenoble France [email protected]

BADAROGLU Mustafa Leuven Belgium [email protected]

LEBOWSKY Fritz Grenoble France [email protected]

IMBERT Michel Grenoble France [email protected]

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BERTHET Christian Grenoble France [email protected]

LEGALL Herve Grenoble France [email protected]

GOGEZ Patrick Crolles France [email protected]

GARCIN Philippe Crolles France [email protected]

QUINIO Philippe Crolles France [email protected]

MAS Gerard Crolles France [email protected]

PONT Jean-Christophe Grenoble France [email protected]

DIAZNAVA Mario Grenoble France [email protected]

SCOTTI Serge Grenoble France [email protected]

BARTHES Guilhem Grenoble France [email protected]

FLAMAND Eric Grenoble France [email protected]

COPPOLA Marcello Grenoble France [email protected]

GUARESCHI Carlo Genève France [email protected]

CHÂTEAU Jean-Marc Grenoble France [email protected]

MARRON Dominique Grenoble France [email protected]

LE PAILLEUR Laurent Grenoble France [email protected]

RAVATIN Jean Grenoble France [email protected]

BRACKEN Sarah Grenoble France [email protected]

HELAL Didier Grenoble France [email protected]

GAUDILLAT Philippe Grenoble France [email protected]

HEMBERT Serge Grenoble France [email protected]

COTTIN Denis Grenoble France [email protected]

FONTBONNE Alain Grenoble France [email protected]

LE SAINT Erwan Grenoble France [email protected]

NONIER Pascal Grenoble France [email protected]

PICCO André Grenoble France [email protected]

GOULAHSEN Abdelaziz Grenoble France [email protected]

AYZAT Gilles Grenoble France [email protected]

ARTIERI Alain Grenoble France [email protected]

MONNIER Philippe Grenoble France [email protected]

PICHON Jérôme Grenoble France [email protected]

HULOUX Joël Grenoble France [email protected]

BIANIC Stéphane Grenoble France [email protected]

DUMAS Sophie Grenoble France [email protected]

SAURY Luc Grenoble France [email protected]

FREUND Christian Grenoble France [email protected]

NIMSGERN Fabien Grenoble France [email protected]

MENUT Patrick Grenoble France [email protected]

AGAESSE Jean-François Grenoble France [email protected]

QUALIZZA Gianni Grenoble France [email protected]

MEDARD Cyrille Grenoble France [email protected]

COTTE Régis Grenoble France [email protected]

DETOUT Sylvain Grenoble France [email protected]

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Annex 3: Programme for European Nanoelectronics Design Technology Conference

21-22 June 2012, Grenoble, France Thursday June 21 st 08:45 Welcome Opening

Laurent Malier, CEA/LETI 09:00 Keynote: HPC-cloud computing

John Goodacre, ARM 09:45 Keynote: Challenges for Embedded SW Integration : Challenges in embedded

Software for industrial applications Eric Debes, Thales

10:30 Break Technical Session 1 : Multiphysics design flow Chair: Mario Diaz-Nava, STM 11:00 Tutorial: Virtual Prototyping and Power Profiling of Distributed, Multi-Physical

Systems Christoph Grimm, Vienna University of Technology

11:45 Multi Domain Virtual Prototyping : challenges for composability

Serge Scotti, STM, François Pecheux, UPMC/LIP6 12:05 Novel system level design approaches for automotive applications

Martin Barnasconi, NXP, Karsten Einwich, Fraunhofer-IIS/EAS 12:30 Lunch Technical Session 2 : Test Innovation Chair: Kees Veelenturf, NXP 14:00 Tutorial: Reducing Test Cost for Mixed Signal Circuits From TOETS to ELESIS

Mohamed Azimane, NXP-NL 14:45 PLL Jitter BIST approach on SOC’s

Hervé Legall, STM 15:05 Testing SiP and SoC Wirelessly : an utopia?

Serge Bernard, LIRMM 15:30 Break Technical Session 3 : Embedded MPSoC Architecture Chair: Marcello Coppola, STM 16:00 Memory architectures in heterogeneous multicore SoCs

Axel Jantsch, KTH

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16:45 Platform 2012 : Challenges and opportunities for a many core accelerator in the embedded space in deep sub micro manufacturing process Éric Flamand, STM

17:05 A shared-memory MPSoC

Nam Nguyen, BULL 17.30 Panel Session: FDSOI vs Finfet : Impact on design automation and perspectives for

applications (semi) Chair: Denis Rousset, STE

Panelist: Xavier Cauchy SOITEC, Laurent Le-Pailleur ST-Ericsson , Olivier Faynot CEA-Leti 19:00 End 19:30 Social Event: dinner Friday June 22nd 09:00 Keynote: Increasing importance of power-devices

R. Petschacher, Infineon Technologies AG semiconductors 09:45 More than Moore, Market outlook Analyst

Jean-Marc Yannou, Yole 10:30 Break Technical Session 4 : Smart Energy Chair : J.L Conesa, 11:00 Present and future of the smart grid

Jesus Teijeiro, Atmel 11:45 Broadband PLC for AMI

Jose Calero, Marwell 12:05 Energy reduction through LED lighting, Paul Merkus, Phillips Lighting 12:30 Lunch 14.00 Panel Session: SME Key contributors in Design flow

Chair: Frédéric Pétrot, TIMA Lab Panelists : Franck C. Schenkel, MunEDA, Harald Bothe/Reimund Wittmann, IPGEN Microelectronics GmbH, Sylvain Kaiser, Docea Power, Cyril Spasevski, Magillem Design Services, Firas Mohamed, Infiniscale 15:30 Closing

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Annex 4: List of FP7/ARTEMIS/ENIAC projects invited to join R&D ACCESS

FP7 3.1 WADIMOS Wavelength division multiplexed photonic layer on CMOS

FP7 3.1 NANOPACK Nano packaging technology for interconnect and heat dissipation

FP7 3.1 S‐PULSE Shrink‐Path of ultra‐low power super‐conducting electronics

FP7 3.1 ELITE Extended large (3D) integration technology

FP7 3.1 REALITY Reliable and variability tolerant system‐on‐a‐chip design in more‐moore technologies

FP7 3.1 EUROTRAINING Provision of a European training infrastructure

FP7 3.1 COPPER Copper interconnects for advanced performance and reliability

FP7 3.1 MAGIC Mask less lithography for IC manufacturing

FP7 3.1 DOTFIVE Towards 0.5 Terahertz Silicon/Germanium Hetero‐junction Bipolar Technology

FP7 3.1 ICESTARS Integrated circuit/EM simulation and design technologies for advanced radio systems‐on‐chip

FP7 3.1 MD3 Material development for double exposure and double patterning

FP7 3.1 GOSSAMER Giga‐scale oriented solid state flash memory for Europe

FP7 3.1 EUROSOI+ European platform for low‐power applications on silicon‐on‐insulator technology

FP7 3.1 MOCHA Modelling and Characterization for SiP signal and power integrity analysis

FP7 3.1 IDESA Implementation of widespread IC design skills in advanced deep submicron technologies at European Academia

FP7 3.1 EUROPRACTICE IC4 EUROPRACTICE CAD and IC service for European universities and research institutes

FP7 3.1 SIDAM Investigation of Si wafer damage in manufacturing processes

FP7 3.1 ATHENIS Automotive tested high‐voltage embedded non‐volatile memory integrated SoC

FP7 3.1 DUALLOGIC Dual‐channel CMOS for (sub)‐22 nm high performance logic

FP7 3.1 NANOSIL Silicon‐based nanostructures and nanodevices for long term nanoelectronics applications

FP7 3.3 ACTORS Adaptivity and control of resources in embedded systems

FP7 3.3 PREDATOR Design for predictability and efficiency

FP7 3.3 COSINE2 Coordinating strategies for embedded systems in the European research area follow‐up project

FP7 3.3 SATURN SysML based modelling, architecture exploration, simulation and synthesis for complex embedded systems

FP7 3.3 GALAXY GALS interface for complex digital system integration

FP7 3.3 QUASIMODO Quantitative system properties in model‐driven design of embedded systems (QUASIMODO

FP7 3.3 MOGENTES Model‐based generation of tests for dependable embedded systems

FP7 3.3 MEDEIA Model‐driven embedded system design environment for the industrial automation sector

FP7 3.3 INTERESTED Interoperable embedded systems Tool‐chain for enhanced rapid design, prototyping and code generation

FP7 3.3 MNEMEE Memory management technology for adaptive and efficient design of embedded systems

FP7 3.3 COMBEST Component‐based embedded systems design techniques

FP7 3.3 MULTICUBE Multi‐objective design space exploration of multi‐processor soc architectures for embedded multimedia applications

FP7 3.3 COCONUT A correct‐by‐construction workbench for design and verification of embedded systems

FP7 3.3 ArtistDesign Design for embedded systems

FP7 3.3 ALL‐TIMES Integrating European timing analysis technology

FP7 3.4 JEOPARD Java environment for parallel realtime development

FP7 3.4 MERASA Multi‐core execution of hard‐real‐time applications supporting analysability

FP7 3.4 APPLE‐CORE Architecture paradigms and programming languages for efficient programming of multiple CORES

FP7 3.4 CRISP Cutting edge reconfigurable ics for stream processing

FP7 3.4 ICT‐EMUCO Embedded multi‐core processing for mobile communication systems

FP7 3.4 MOSART Mapping optimisation for scalable multi‐core architecture

FP7 3.4 VELOX Velox: an integrated approach to transactional memory on multi‐ and many‐core computers

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FP7 3.4 HIPEAC High performance and embedded architecture and compilation

FP7 3.4 GENESYS Generic embedded system platform

FP7 3.5 BOOM Terabit‐on‐chip: micro and nano‐scale silicon photonic integrated components and sub‐systems enabling Tb/s‐capacity, scalable and fully integrated photonic routers

FP7 3.5 HISTORIC Heterogeneous InP on silicon technology for optical routing and logic

FP7 3.5 ICU Infrared imaging components for use in automotive safety applications

FP7 3.5 PHOTONFAB Silicon photonic IC fabless access broker

FP7 3.5 FAST‐DOT Compact ultrafast laser sources based on novel quantum dot structures

FP7 3.5 PHOTONICROADSME Development of advanced technology roadmaps in photonics and industrial adaption to SMEs

FP7 3.5 DOTSENSE Group III‐nitride quantum dots as optical transducers for chemical sensors

FP7 3.5 POF‐PLUS Plastic optical fibre for pervasive low‐cost ultra‐high capacity systems

FP7 3.5 OPTHER Optically driven terahertz amplifiers

FP7 3.5 MARISE Materials for avalanche receiver for ultimate sensitivity

FP7 3.5 PHORCE21 Photonics research coordination Europe ‐ Photonics21

FP7 3.5 PHOTONIC4LIFE Network of excellence for biophotonics

FP7 3.5 MIRSURG Mid‐infrared solid‐state laser systems for minimally invasive surgery

FP7 3.5 OLED100.EU Organic LED lighting in European dimensions

FP7 3.5 INTOPSENS A highly integrated optical sensor for point of care label free identification of pathogenic bacteria strains and their antibiotic resistance

FP7 3.5 PHASORS Phase sensitive amplifier systems and optical regenerators and their applications

FP7 3.5 APACHE Agile photonic integrated systems‐on‐chip enabling WDM Terabit networks

FP7 3.5 HELIOS Photonics Electronics functional Integration on CMOS

FP7 3.5 MUTIVIS Multispectal terahertz, infrared, visible imaging and spectroscopy

FP7 3.5 SUBTUNE Widely Tunable VCSEL using sub wavelength gratings

FP7 3.5 GIGAWAM Giga bit access passive optical network using wavelength division multiplexing

FP7 3.5 VISIT VISIT ‐ vertically integrated systems for information transfer

FP7 3.5 EURO‐FOS Pan‐European photonics task force: integrating Europe's Expertise on photonic subsystems

FP7 3.5 MINIGAS Miniaturised photoacoustic gas sensor based on patented interferometric readout and novel photonic integration technologies

FP7 3.5 PHOSFOS Photonic skins for optical sensing

FP7 3.5 DELIGHT Development of low‐cost technologies for the fabrication of high‐performance telecommunication lasers

FP7 3.5 SENSHY Photonic sensing of hydrocarbons based on innovative mid infrared lasers

ARTEMIS 2008 CAMMI Cognitive Adaptive Man‐Machine Interface

ARTEMIS 2008 CESAR Cost‐efficient methods and processes for safety relevant embedded systems

ARTEMIS 2008 CHARTER Critical and High Assurance Requirements Transformed through Engineering Rigour

ARTEMIS 2008 CHESS Composition with guarantees for high‐integrity embedded software components assembly

ARTEMIS 2008 eDIANA Embedded Systems for Energy Efficient Buildings

ARTEMIS 2008 EMMON EMbedded MONitoring

ARTEMIS 2008 iLAND mIddLewAre for deterministic dynamically reconfigurable NetworkeD embedded systems

ARTEMIS 2008 INDEXYS INDustrial EXploitation of the genesYS cross‐domain architecture

ARTEMIS 2008 SCALOPES SCalable LOw Power Embedded platformS

ARTEMIS 2008 SMART Secure, mobile visual sensor networks architecture

ARTEMIS 2008 SOFIA Smart Objects For Intelligent Applications

ARTEMIS 2008 SYSMODEL System level modelling for SMEs

ARTEMIS 2009 ACROSS ARTEMIS CROSS‐Domain Architecture

ARTEMIS 2009 ASAM Automatic Architecture Synthesis and Application Maping

ARTEMIS 2009 CHIRON Cyclic and person‐centric Health management Integrated appRoach for hOme, mobile and clinical eNvironments

ARTEMIS 2009 eSONIA Embedded Service Oriented Monitoring, Diagnostics and Control: Towards the Asset‐Aware and Self‐Recovery Factory

ARTEMIS 2009 iFEST Industrial framework for embedded systems tools

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ARTEMIS 2009 ME3GAS Smart Gas Meters & Middleware for Energy Efficient Embedded Services

ARTEMIS 2009 POLLUX A common multi‐domain architecture and design platform for advanced multi‐core hardware and middleware solutions for electrical vehicles

ARTEMIS 2009 R3‐COP advanced robust and safe cognitive, reasoning autonomous and co‐operative robotic systems

ARTEMIS 2009 RECOMP Reduced Certification Costs Using Trusted Multi‐core Platforms

ARTEMIS 2009 p.S.HI.E.L.D Pilot embedded systems architecture for multi‐layer dependable solutions

ARTEMIS 2009 SIMPLE Intelligent, self‐organizing embedded middleware platform

ARTEMIS 2009 SMARCOS Smart composite human‐computer interfaces

ARTEMIS 2009 SMECY Smart multicore embedded systems

ARTEMIS 2010 ASTUTE Pro‐active decision support for data‐intensive environments

ARTEMIS 2010 D3COS Designing Dynamic Distributed Cooperative Human‐Machine Systems

ARTEMIS 2010 ENCOURAGE Embedded iNtelligent COntrols for bUildings with Renewable generAtion and storaGE

ARTEMIS 2010 High Profile High Profile

ARTEMIS 2010 IoE INTERNET OF ENERGY for ELECTRIC MOBILITY

ARTEMIS 2010 MBAT Combined Model‐based Analysis and Testing of Embedded Systems

ARTEMIS 2010 nSHIELD SHIELD Architectural Framework for Security, Privacy and Dependability

ARTEMIS 2010 PRESTO ImProvements of industrial Real Time Embedded SysTems develOpment process

ARTEMIS 2010 pSafeCer Safety Certification of Software‐Intensive Systems with Reusable Components

ARTEMIS 2010 WSN DPCM Wireless Sensor Network for Development, Planning, Commissioning, and Maintenance

ENIAC 2008 E3Car Energy efiicient electric car

ENIAC 2008 MODERN Modeling and design of reliable, proces variation‐aware nanoelectronic devices, circuits and systems

ENIAC 2008 IMPROVE Implementing Manufacturing science solutions to increase equiPment pROductiVity and fab pErformance

ENIAC 2008 SmartPM Smart power management

ENIAC 2008 SE2A Nanoelectronics for Safe, Fuel Efficient and Environment Friendly Automotive Solutions

ENIAC 2008 LENS Lithography process for beyond 32nm manufacturing

ENIAC 2008 JEMSiP_3D Joint equipment and materials for system‐in‐package and 3D integration

ENIAC 2009 CSSL Consumerizing Solid State Lighting

ENIAC 2009 MERCURE Micro and Nano Technologies Based on Wide Band Gap Materials for Future Transmitting Receiving and Sensing Systems

ENIAC 2009 CSI Central nervous system imaging

ENIAC 2009 ESiP Efficient silicon multi‐chip system‐in‐package integration – reliability, failure analysis and test

ENIAC 2009 EEMI450 European 450mm Equipment & Materials Initiative

ENIAC 2009 MAS Nanoelectronics for Mobile Ambient Assisted Living (AAL) Systems

ENIAC 2009 CAJAL4EU Nanoelectronics‐based biosensor technology platforms

ENIAC 2009 MIRANDELA Millimeter‐wave integration in Nanoelectronics for Modern Wireless 5 A Communications

ENIAC 2009 SMART Secure Memories and Applications Related Technologies

ENIAC 2009 END Models, Solutions, Methods and Tools for Energy‐Aware Design

ENIAC 2009 LAST POWER Large area silicon carbide substrates and the teroepitaxial GaN for power device applications

ENIAC 2010 ARTEMOS Agile RF Transceivers and Front‐Ends for Future Smart Multi‐Standard Communications ApplicationS

ENIAC 2010 ENLIGHT Energy efficient and intelligent lighting systems

ENIAC 2010 EPAMO Energy‐efficient Piezo‐MEMS tunable RF front‐end Antenna systems for MObile devices

ENIAC 2010 ERG Energy for a Green Sociaty

ENIAC 2010 HEECS High efficiency electronic cooking systems

ENIAC 2010 MotorBrain Nanoelectronics for electric vehicle intelligent failsafe powertrain

ENIAC 2010 NanoCom Reconfigurable microsystem based on wide band gap materials, miniaturised and nano‐structured RF‐MEMS

ENIAC 2010 NanoTEG Nanostructured thermoelectric systems for green transport and energy efficient applications

ENIAC 2010 PARSIMO Partitioning and modelling of system‐in‐package

ENIAC 2010 TOISE Trusted computing for European embedded systems

D1.4 R&D ACCESS

FP7-2009-246633

Annex 5: Presentation slides from the workshop

10-08-2012

1

TechnoconsultDesign & ReuseCOREPEdacentrumCEA‐LETI

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iconductor Design

R&D project results

Problems:

• Result are scattered among several 100s of EU projects

• Most projects have a life time of 3 years

ICT‐2009‐246633

Access to Research Results on

• After completion project websites tend to dry out

• Several project results are IPR protected

Solution:

• Make use of existing knowledge platforms


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Access to semiconductordesign knowledge

CAE tools from edacentrumIP blocks from Design-ReuseCourses from EuroTrainingMethods from CEA-LETI

ICT‐2009‐246633



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Access to semiconductordesign knowledge

ICT‐2009‐246633



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FP6

P ti

FP7Large Industry

(Mature design flow, application oriented)

Integrated knowledge platform

ICT‐2009‐246633


EUREKAJTI EPoSS

JTI ARTEMIS

JTI ENIACACCESS

Training

Promotion





Methods

ED

A

IP

Promotion

Pro

mo

tion

Pro

mo

tio

n

KNOWLEDGEPROVIDERS

KNOWLEDGEUSERS



Immature methods)

ACCESS


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• More than 400 training courses/year• Provided by 72 professional trainingproviders

• More than 200.000 monthy hits• Nearly 12.000 European trainingsubscribers.

• More than 70 EDA members• Information on 450 different EDAprojects

• Nearly 12.500 EDA experts• Over 6.800 EDA publications

Training: EDA tools:

Integrated knowledge platform

FP6

FP7Large Industry

(Mature design flow, application oriented)

ICT‐2009‐246633


• Covering SoC, MPSoC, NoC, SiPand FPGA

• Identification of new design methodologies • Benchmarking of design methodologies• Classification of advanced/mature methods

• Intellectual Properties public web portal• 15.000 updated IP/SoC product descriptions• 150 companies with partnership agreement • Weekly IP/SoC News reaches 25.000 subscribers

IP: Methods:

EUREKAJTI EPoSS

JTI ARTEMIS

JTI ENIACACCESS

Training

Promotion





Methods

ED

A

IP

Promotion

Pro

mo

tionP

rom

oti

on

KNOWLEDGEPROVIDERS

KNOWLEDGEUSERS



Immature methods)

ACCESS


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‐ Validation check‐ QL service‐ e‐bay style evaluation of material

Training provider

ICT‐2009‐246633


European Training Infrastructure: ‐Web service‐ 500 courses/year‐Maximizes the visibility‐ Training roadmaps

Promotion:‐Monthly news‐Mailing list 12.000‐ Promotional material

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Outside-in ProcessIntegrating external

Inside-out Process

Company specific development

Innovation models

ICT‐2009‐246633

Access to Research Results on Integrating external

Knowledge, customers

and suppliers -Client/supplier

integration-External technology

sourcing

-licensing IP-multiplication

of technologies

-Cross industry

innovation

Development Product


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Benefits

What are the benefits for the provider? • A pan European dissemination platform • Mailing lists reaching >40.000 semiconductor designers • Support for design flow integration including training, IP, EDA toolsand design methodologies

What are the benefits for the user?

ICT‐2009‐246633

Access to Research Results on What are the benefits for the user?

• ACCESS to European R&D knowledge infrastructure with initiallymore than 20.000 items

• ACCESS to one-stop-shop with single sign-on for semiconductordesign knowledge

• ACCESS to annual workshops on application specific nanoelectronicsplatforms supporting the design in advanced processes


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Searching

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Search results

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ICT‐2009‐246633


T1.3: Annual workshop on application specific ... · D1.4 R&D ACCESS FP7-2009-246633 Page 1 Project...

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