SystemC and Levels of SystemC and Levels of System Abstraction: Part ISystem Abstraction: Part I

Levels of System AbstractionLevels of System Abstraction Executable specificationExecutable specification

Translation of design specification into SystemCTranslation of design specification into SystemC Independent of the proposed implementationIndependent of the proposed implementation Time delays if present denote timing constraintsTime delays if present denote timing constraints

Untimed functional model (CP)Untimed functional model (CP) Separation of the specification into modulesSeparation of the specification into modules Communication between modules is point to pointCommunication between modules is point to point Communication usually via bounded FIFOCommunication usually via bounded FIFO

• blocking read, blocking writeblocking read, blocking write No time delays present in the modelNo time delays present in the model

Levels of System AbstractionLevels of System Abstraction

Timed functional model (CP + T)Timed functional model (CP + T) Processes communicate via point-to-point linksProcesses communicate via point-to-point links Timing delays added to processes to reflectTiming delays added to processes to reflect

• Timing constraintsTiming constraints• Latency of a particular implementationLatency of a particular implementation

Timing delays added to FIFOs to model communication Timing delays added to FIFOs to model communication latencieslatencies

Initial model for hardware/software trade-off analysisInitial model for hardware/software trade-off analysis

Levels of System AbstractionLevels of System Abstraction Transaction level model or Programmers view (PV)Transaction level model or Programmers view (PV)

Communication modeled by function callsCommunication modeled by function calls• Similar to transport level specificationSimilar to transport level specification• Bus burst mode of read/write Bus burst mode of read/write • FIFOs replaced by actual communication protocolFIFOs replaced by actual communication protocol• Bus contention modeled but not with realistic timingBus contention modeled but not with realistic timing

Instruction set simulator for SW code (HW in timed process)Instruction set simulator for SW code (HW in timed process)• Register accurateRegister accurate

Memory map is definedMemory map is defined Timing defined in terms of instruction set cyclesTiming defined in terms of instruction set cycles

Platform transaction model (or PV + T)Platform transaction model (or PV + T) Interconnection architecture fully definedInterconnection architecture fully defined

• Multiple clock cycles for bus communicationMultiple clock cycles for bus communication• Can model bus arbitration overheadCan model bus arbitration overhead

SW on ISS, HW in timed process SW on ISS, HW in timed process Model is not pin accurateModel is not pin accurate

Levels of System AbstractionLevels of System Abstraction Behavioral hardware model (mainly for ASIC cores)Behavioral hardware model (mainly for ASIC cores)

Pin accurate and functionally accurate at its boundariesPin accurate and functionally accurate at its boundaries Not clock accurateNot clock accurate No internal structureNo internal structure Input to behavioral synthesis toolInput to behavioral synthesis tool

Pin accurate cycle accurate model (CA)Pin accurate cycle accurate model (CA) In addition to pin accurate it is also cycle accurateIn addition to pin accurate it is also cycle accurate Does not necessarily have the internal structureDoes not necessarily have the internal structure SW ISS replaced by model that includes cacheSW ISS replaced by model that includes cache

Levels of System AbstractionLevels of System Abstraction

Register transfer level modelRegister transfer level model Pin accuratePin accurate Cycle accurateCycle accurate Internal structure is definedInternal structure is defined

System Design StylesSystem Design Styles Application specific standard product (ASSP)Application specific standard product (ASSP)

Intel IXP series network processorsIntel IXP series network processors TI OMAP platformTI OMAP platform

System Design StylesSystem Design Styles Programming for application specific standard Programming for application specific standard

product (ASSP)product (ASSP) Architecture is fixedArchitecture is fixed

• Multiple programmable unitsMultiple programmable units• Multiple application specific coresMultiple application specific cores• Multiple memory interfacesMultiple memory interfaces

Objective : Map application on target platformObjective : Map application on target platform• Maximize performanceMaximize performance

Design proceeds from CP, CP+T, PV to final Design proceeds from CP, CP+T, PV to final implementationimplementation

System Design StylesSystem Design Styles Structured ASIC: IP based design styleStructured ASIC: IP based design style

Xilinx platform FPGAXilinx platform FPGA• PowerPC hardcoresPowerPC hardcores• Microblaze softcoresMicroblaze softcores• 18 bit Multipliers18 bit Multipliers• Block RAMSBlock RAMS• Rocket I/O transceiversRocket I/O transceivers

System Design StylesSystem Design Styles Structured ASIC: IP based design styleStructured ASIC: IP based design style

Architecture is fixed to a large extentArchitecture is fixed to a large extent• Flexibility in introducing HW coresFlexibility in introducing HW cores

IP blocks provided by vendorIP blocks provided by vendor Designer generates new coresDesigner generates new cores

• Programmable units are fixedProgrammable units are fixed• Memory interfaces are fixedMemory interfaces are fixed

Objective : Refine micro-architecture with an objective ofObjective : Refine micro-architecture with an objective of• Maximize: performanceMaximize: performance• Minimize: cost, powerMinimize: cost, power

Design proceeds from CP, CP+T, PV, PV+T, CA to final Design proceeds from CP, CP+T, PV, PV+T, CA to final implementationimplementation

System Design StylesSystem Design Styles Generic multiprocessor SoC designGeneric multiprocessor SoC design

Architecture is yet to be definedArchitecture is yet to be defined• HW cores can consist ofHW cores can consist of

IP blocks provided by vendorIP blocks provided by vendor Designer generates new coresDesigner generates new cores

• Multiple programmable unitsMultiple programmable units• Multiple memory interfacesMultiple memory interfaces

Objective : Design micro-architecture with an objective ofObjective : Design micro-architecture with an objective of• Maximize: performanceMaximize: performance• Minimize: cost, powerMinimize: cost, power

Design proceeds from CP, CP+T, PV, PV+T, CA to final Design proceeds from CP, CP+T, PV, PV+T, CA to final implementationimplementation

Executable SpecificationExecutable Specification

Any code in C or C++ can act as the executable Any code in C or C++ can act as the executable specificationspecification

The code is implementation agnosticThe code is implementation agnostic The code acts a functional benchmark for The code acts a functional benchmark for

verification verification Timing specified at input/output boundariesTiming specified at input/output boundaries

Specified as design directiveSpecified as design directive Code might be specified as one SystemC process Code might be specified as one SystemC process

with timingwith timing

Untimed Functional ModelUntimed Functional Model

Design is specified in terms of its functional Design is specified in terms of its functional componentscomponents

Functional components specify possible Functional components specify possible structural boundaries of final implementationstructural boundaries of final implementation

Some functional components might be Some functional components might be merged while other might become discrete merged while other might become discrete cores cores

Untimed Functional ModelUntimed Functional Model Dataflow MoC is the most common form of Dataflow MoC is the most common form of

specificationspecification Alternatively Kahn process networks, Multi-rate dataflow Alternatively Kahn process networks, Multi-rate dataflow

Communication between components is through Communication between components is through directed point-to-point FIFOdirected point-to-point FIFO

FIFO are boundedFIFO are bounded Blocking read, blocking writeBlocking read, blocking write

Time delays might exist in the model at the Time delays might exist in the model at the boundariesboundaries Processes in which the model interacts with the Processes in which the model interacts with the

environmentenvironment Time delays denote constraints for the systemTime delays denote constraints for the system

SystemC Untimed Functional ModelSystemC Untimed Functional Model

Modules contain SC_THREAD processModules contain SC_THREAD process Modules communicate through sc_fifo channelsModules communicate through sc_fifo channels

Initial values in FIFOs should be specifiedInitial values in FIFOs should be specified Stop simulation whenStop simulation when

Finite time has elapsedFinite time has elapsed• Requires atleast one module with time delayRequires atleast one module with time delay

Terminate processes through data backlogTerminate processes through data backlog• Thread returns when input FIFO is emptyThread returns when input FIFO is empty

Call sc_stop() when termination condition is reachedCall sc_stop() when termination condition is reached• Easiest to implementEasiest to implement• For example, consumption of finite set of input stimuliFor example, consumption of finite set of input stimuli

SystemC Untimed Functional ModelSystemC Untimed Functional Model

constant adder fork printer

Z-1

template <class T> SC_MODULE(DF_Const){sc_fifo_out<T> output;T constant_;

void process() { while(1) output.write(constant_); }

SC_HAS_PROCESS(DF_Const);

DF_Const(sc_module_name N, const T& C):sc_module(N), constant_(C) { SC_THREAD(process); }

};

SystemC Untimed Functional ModelSystemC Untimed Functional Model

template <class T> SC_MODULE(DF_Fork){sc_fifo_in<T> input;sc_fifo_out<T> output1; sc_fifo_out<T> output2;

void process() { while(1) {

T value = input.read();output1.write(value);output2.write(value);

}}SC_CTOR(DF_Fork) { SC_THREAD(process); }

};

template <class T> SC_MODULE(DF_Adder){sc_fifo_in<T> input1, input2;sc_fifo_out<T> output; sc_fifo_out<T> output2;

void process() { while(1) { output.write(input1.read() + input2.read()); } }SC_CTOR(DF_Fork) { SC_THREAD(process); }

};

SystemC Untimed Functional ModelSystemC Untimed Functional Modeltemplate <class T> SC_MODULE(DF_Printer){

sc_fifo_in<T> input;unsigned n_iterations_;bool done_;

void process() { while(1) {

For (unsigned i = 0; i < n_iterations_; i++) {T value = input.read();cout << name() << “ “ << value << endl;

}done = true;return;

}

SC_HAS_PROCESS(DF_printer);

DF_Printer(sc_module_name NAME, unsigned N_ITER) :sc_module(NAME), n_interations_(N_ITER), done_(false);{ SC_THREAD(process); }

~DF_Printer() {If (!done_) cout << name() << “ not done yet “ << endl;

}};

SystemC Untimed Functional ModelSystemC Untimed Functional Modelint sc_main(int argc, char** argv){ DF_Const<int> constant(“constant”,1); DF_Adder<int> adder(“adder”); DF_Fork<int> fork(“fork”); DF_Printer<int> printer(“printer”, 10);

sc_fifo<int> const_out(“const_out”, 5); sc_fifo<int> adder_out(“adder_out”,1); sc_fifo<int> feedback(“feedback”, 1); sc_fifo<int> to_printer(“to_printer”, 1);

feedback.write(42);

constant.output(const_out); adder.input1(feedback); adder.input2(const_out); fork.input(adder_out); fork.outpu1(feedback); fork.outpu2(to_printer); printer.input(to_printer);

sc_start(-1); return(0);}

• Start simulation without time limit. • Simulation stops when no more events.• When printer thread exits simulation will stop.

•All FIFOs will become full

SystemC Timed Functional ModelSystemC Timed Functional Modeltemplate <class T> SC_MODULE(DF_Const){

sc_fifo_out<T> output;T constant_;

void process() { while(1) { wait(200, SC_NS); output.write(constant_);} }

SC_HAS_PROCESS(DF_Const);

DF_Const(sc_module_name N, const T& C):sc_module(N), constant_(C) { SC_THREAD(process); }

};

template <class T> SC_MODULE(DF_Adder){sc_fifo_in<T> input1, input2;sc_fifo_out<T> output; sc_fifo_out<T> output2;

void process() { while(1) { output.write(input1.read() + input2.read()); wait(200, SC_NS);} }

SC_CTOR(DF_Fork) { SC_THREAD(process); }};

Stopping Dataflow SimulationStopping Dataflow Simulation

Simulate with fixed number of input stimuli Simulate with fixed number of input stimuli and returnand return If a method thread is blocked due to a bug If a method thread is blocked due to a bug

then simulation will not stopthen simulation will not stop Each process consumes a fixed amount of Each process consumes a fixed amount of

stimuli and sets a “done” signalstimuli and sets a “done” signal A “terminator” process issues “sc_stop()” A “terminator” process issues “sc_stop()”

when all processes have issued “done”when all processes have issued “done”

Levels of System AbstractionLevels of System Abstraction

To be continuedTo be continued Detour intoDetour into

Hardware performance estimationHardware performance estimation System-level performance estimationSystem-level performance estimation