Abstraction Levels in the Digital System Modeling

Contents Handling complexity – Abstraction levels Design flow of digital systems Additional readings

Budapest University of Technology and Economics

Abstraction Levels in the Digital System Modeling

Péter Horváth

Department of Electron Devices

September 25, 2014

Péter Horváth Abstraction Levels in the Digital System Modeling 1 / 24


Contents

Contents

handling complexity – abstraction levels in digital system modelingthe Gajski-Kuhn Y-diagram – function representations, modelingmeans, structural elementsa detailed discussion of the different abstraction levels and theiroptimization goals

design flow of digital systemstop-down and bottom-up design approachestop-down and bottom-up methods in digital designa detailed discussion of the digital system design flow – from theviewpoint of the system designer

additional readings



Handling complexity –Abstraction levels



The Gajski-Kuhn Y-diagram

The Gajski-Kuhn Y-diagram

The GK diagram is an expressive representation of the abstractionlevels.The circles represent the abstraction levels and the arrows representthe aspects they are examined from.

register transfers



Abstraction levels

Design objectives on the different abstraction levels

System – defining design partitions and their interfacesAlgorithm – behavioral modeling with high-level programminglanguagesRTL (register-transfer level) – defining "microarchitecture",separating control and datapathGate – defining the behavior of RTL components with Boole-equationsCircuit – implementing the behavior of the logic gates withtransistor-based structuresDevice – constructing small, fast, and low-power transistorsTechnology – optimizing the technology parameters that influencethe device construction



Abstraction levels

System-level

The main objective is to define the partitions of the system and thecommunication methods and interfaces between the partitions andthe outside world.The object-oriented paradigm is widely used in system-level design.design entity examples: GPCPU1, GPGPU2, DSP3, memory (cache,operative memory, mass storage), I/O subsystem, peripheralcontrollerconsiderations on system-level

number of the microprocessorstopology of the memory subsystem in multiprocessor systemsmemory hierarchy (cache levels and sizes)communication models (hand-shake, mailbox, FIFO etc.)

1general-purpose central processing unit2general-purpose graphics processing unit3digital signal processor



Abstraction levels

Algorithm-level

High-level programming language representation of thesubsystems’ behavior.Once the algorithm-level implementations of the subsystems arecreated, the system can be simulated.The simulation requires high computation capacity, therefore theefficiencies of the algorithmic models are critical. The most widelyused tools for algorithmic modeling are native C and C++,supplemented by a set of hardware-oriented class libraries.

algorithm-level (C++) model of a simple RC filter



Abstraction levels

RTL – register-transfer level

The objective of RTL is to describe the data transfers and theirtiming between simple functional units with (registers, register files,arithmetic-logic units etc.)Separating datapath and control; the datapath includes thefunctional units and their interconnections. The control unitgenerates control signals with appropriate timing.

considerations on RTLcontrol: single-cycle, multicycle,pipelineinternal data-storage structures(registers, register files)clocking scheme: frequency, phasesignals

controlI/O

controlsignals

statussignal

controlunit

datainputs



Abstraction levels

Gate-level

All digital functions – even those containing data storage – can berepresented by a set of interconnected logic gates. Although theelementary data-storage elements (flip-flops) can be described withgates, they are considered basic building blocks of gate-level models,because they have a unique physical realization primitive (they arenot implemented as interconnected logic gates).considerations on gate-level

handling logical hazardstwo-level or multilevel logic realizationgate-level architecture optimization of functional units (e.g. adder:ripple-carry vs. carry lookahead)



Abstraction levels

Circuit-level

The functionality of a logic gate can be realized by interconnectedtransistors. This circuit-level model is a "standard cell".representations of a standard cell

schematic: a logical network of transistorslayout: a physical realization of the schematic

To simulate a circuit-levelmodel, the mathematicalmodels of the transistors (e.g.Ebers-Moll, Gummel-Poon,EKV, BSIM3) are required.considerations on circuit-level

circuit family (ECL, SCL,static/dynamic CMOS)topology (e.g. dominoCMOS: alternate/pipeline)



Abstraction levels

Device-level

To improve the computation capacity, power consumption, anddevice density of the digital circuits, we need small, fast, andefficient transistors. The aim of device-level is to optimize thetransistor parameters.

considerations on device-levelthreshold voltage, switchingfrequency, powerconsumption, size etc.scaling: short-channel andstrait-channel effects,hot-electron effect,gate-depletion, latch-up,preventing or exploitingquantum-effects (HKMG,EEPROM)



Abstraction levels

Technology-level

The aim of technology-level optimization is to analyze the effect oftechnological parameters on the physical indices influencing thedevice characteristics.Technological parameters: temperature and duration of diffusion,energy of implantation, etc.Physical indices: oxide thickness, conductivity, carrier lifetime andmobility, dopant density and distribution, etc.



Design flow of digital systems



Top-down and bottom-up design approaches

Top-down design method

In the top-down approach the design process starts with a high-levelrepresentation of the system. The high-level model includespartitions (subsystems) with a specific task. During the designprocess the implementations of the subsystems are elaborated; theyare split into components with more specific sub-tasks and moredetailed implementations. The process stops when the componentsof the refined design are simple enough to substitute them with anexisting model (practically with an RTL functional unit).




Bottom-up design method

In the bottom-up approach the designer creates basic functionalunits with very simple tasks. Once a sufficient set of elementaryfunctionalities is constructed, a more complex model can beprepared with the combination of the simple ones. The designprocess stops when the increasingly complex model is able toimplement the desired functionality defined in the specification.




Top-down and bottom-up methods in digital design

In the digital design the top-down and the bottom-up methodsare both applied. The system designer creates RTL models fromthe high-level specification with top-down method but the standardcells are constructed from circuit-level by the component librarydesigner with bottom-up approach.



Digital system design flow – from the viewpoint of the system designer

Step #1. Design partitioning (manual)

concept: The subsystems, their relations and interfaces have to beoutlined. The subsystems are represented as "black boxes".tools: UML, SystemC TLM4, MATLAB

specification

4transaction-level modeling; a C++ class library for system-level modelingPéter Horváth Abstraction Levels in the Digital System Modeling 17 / 24



Step #2. Functional modeling (manual)

concept: The behavior of the subsystems have to be formulated.tools: high-level programming languages (C, C++, SystemC)

functional model (C++)




Step #3. RTL design (manual/automated)

concept: A microarchitecture consisting of simple functional units(registers, register files, arithmetic units, etc.) has to be constructed.tools: hardware description languages (VHDL, Verilog, SystemC)

functional model




Step #4. RTL optimization (manual/automated)

concept: There are many microarchitectures implementing the samefunctionality. We have to choose one with parameters optimal forthe application.tools: hardware description languages (VHDL, Verilog, SystemC)




Step #5. Logic synthesis (automated)

concept: The RTL description is automatically transformed into atechnology and vendor-independent gate-level model.tools: ISE, Quartus II, LeonardoSpectrum, Precision, EncounterRTL Compiler




Step #6. Mapping (automated)

concept: The mapping assigns a specific component libraryprimitive to the generic resources of the gate-level model. Theselibrary primitives are the basic elements of an ASIC technology (e.g.AMS 0.35) or an FPGA device family (e.g. Xilinx Spartan3E).tools: ISE, Quartus II, LeonardoSpectrum, Precision, Virtuoso,Calibre InRoute




Step #7. Place & route (automated)

concept: Place: The mapped primitives are assigned to a specificresource in a device (FPGA) or they are placed into a specificposition of the chip layout (ASIC). Route: The interconnections ofthe placed primitives are constructed. The output of the design flowis a GDSII file (ASIC) including the information required formanufacturing or a bitstream file (FPGA) including theconfiguration memory content of the FPGA device.tools: ISE, Quartus II, Virtuoso, Calibre InRoute



Additional readings

Additional readings

David Money Harris, Sarah L. Harris – Digital Design and ComputerArchitecturePeter J. Ashenden – Digital Design – An Embedded SystemApproach Using VHDLM. Moris Mano, Charles R. Kime – Logic and Computer DesignFundamentalsPong P. Chu – RTL Hardware Design Using VHDLThorsten Grötker, Stan Liao, Grant Martin, Stuart Swan – SystemDesign with SystemC


Abstraction Levels in the Digital System Modeling

Documents

Transcript of Abstraction Levels in the Digital System Modeling