System On Chip modeling with SystemC/TLM

Diapositive 1

System On Chip modeling with SystemC/TLM

L. Maillet-Contoz, STMicroelectronics

Workshop - November 2011 - Toulouse

STMicroelectronics

System Platforms Group

10 years experience in SoC modeling

Definition of ESL methods and tools

Deployment in ST & ST-Ericsson product groups since 2003

Contributions to projects of the various products groups

Drive standards

Corporate Member, OSCI and Accellera

Represents ST at both Boards of Directors

Several donations to the Technical Working Groups

TLM1 & TLM2, CCI

IP-Xact

Former Chair of OSCI board & TLM WG, current Chair of OSCI Verification WG

Current chair of Accellera IP-Xact TSC

Vice Chair of IEEE 1666-2011 Technical Committee

Workshop - November 2011

2

STMicroelectronics

Agenda

Motivations for SoC TLM modeling

Languages and abstractions for System Level Design

Current standards for interoperability

ST TLM Framework

Discussion and conclusion

3

STMicroelectronics

Objectives: face SoC increasing complexity

A camera-telephone?

Version 1998

Version 2008

4

STMicroelectronics

HDL simulation

- Too late

- Too slow

+ Accurate

FPGA prototype

- Too late

- Too costly

+ Accurate

Motivations for Virtual Prototyping

Pre-silicon software development

Functional validation environment

SoC architecture exploration

Soc Virtual Prototype

5

STMicroelectronics

SoC Virtual Prototyping

Input devices

SW

SW

SW

SW

Transaction Level

Models(HW blocks)

H.M.P. SoC

Output devices

6

STMicroelectronics

Agenda



SystemC and IP-Xact

Loosely and Approximately Timed modeling styles

Impact on modeling effort and simulation speed


ST TLM Framework


7

STMicroelectronics

Different platforms for different use models

All activities do not require cycle accuracy

Engineering effort to be balanced with benefits

Fast / precise trade-off

8

STMicroelectronics

Languages for System Level Design

General Purpose Languages

C, C++, Java,

Well known

Standard

Not appropriate for hardware modeling

Dedicated Languages

SpecC, HardwareC,

Well defined semantics

Proprietary

Lack of support

No model exchange

Hardware Description Languages

VHDL, Verilog,

Nice for hardware modeling

Not appropriate for high level modeling

Slow

9

STMicroelectronics

Different abstraction levels

prior to HW/SW partition

Level of Abstraction

RTL

Register Transfer Level

PVT Approximately Timed

Programmers View + Timing

PV Loosely Timed

Programmers View

CA

Cycle Accurate Level

AL

Algorithmic Model

post HW/SW partition

models bit-true behavior, register bank, data transfer, system synchronization

PV plus timing annotation

timed IP models

refined communication models

models state at each clock edge

ASIC flow entry point

synthesizable model

TLM supported abstraction levels

10

STMicroelectronics

Transaction Level Models (LT)

Model IPs/subsystems at the transaction level

Bit true behavior

Bit true communication

System synchronization points

No clock/cycle, but functional timing (e.g. timer)

Fast to implement and simulate

Details of interconnect are abstracted

TAC router

TLM models often built using

C reference model

TLM wrapper

Model registers

serve read/write accesses

11

STMicroelectronics

Transaction Level Models (AT)

Targetting performance evaluation

Hardware architecture

Software

Captures micro-architecture information/timing

Several technical options

LT Model refinement -> rewriting

LT Model annotation

Intrusive

Lightweight effort

Composition of LT and T models

12

STMicroelectronics

Comparing abstraction levels

TLM LT

TLM AT

RTL

Same functional behavior

Same timedbehavior

Same functional behavior

13

STMicroelectronics

Options for processor models (1/2)

Native compilation

Compile the embedded software on the workstation

No model of the core micro-architecture/Instruction set

No assembly code for target processor, nor binary code

Source code level compatibility

Sometimes requires to use a HAL

Advantages & drawbacks

Fast execution

No dependency on low level processor dependent features

Can not be used for performance evaluation

14

STMicroelectronics

Instruction Set Simulator

Instruction Accurate

Captures the Instruction Set

Suitable for LT modeling style

Cycle Accurate

Represents the micro-architecture of the core

Suitable for AT modeling style

Various simulation technologies

Instruction interpretation

Dynamic translation

Advantages and drawbacks

Uses the target tool chain

Binary code compatibility

Slow for interpreted ISS

15

Options for processor models (2/2)

STMicroelectronics

1st dimension: precision

TIME OF PROJECT

TIMING PRECISION

TLM / LTbit-true

RTL

PAPERSPEC

EXEC.SPEC

DESIGNING RTL

RTL EVOLVES UNTIL PG

FIRST COMPLETE RTL

TLM-Timed / AT

CA

16

STMicroelectronics

16

RTL

CA

2nd dimension: effort

Time of project

Effort

PAPERSPEC

EXEC.SPEC

DESIGNING RTL

RTL EVOLVES UNTIL PG

FIRST COMPLETE RTL

TLM/LT

AT

PVT optional

AT

Optional

17

STMicroelectronics

17

CA

3rd dimension: speed

RTL

TLM / LT

AT

AT+

X10-x100

x100

SoC Speed

Chip reference speed

x10

Speed-ups are very design-dependentto be used as rule of thumb !!!

18

STMicroelectronics

18

Agenda




Supporting and adopting ESL standards

SystemC/TLM

IP-Xact

ST TLM Framework


19

STMicroelectronics

Motivations

Complex Virtual Platform integration requires

Model to model interoperability

Model to tool interoperability

A certain level of interoperability is achieved by standards

But full interoperability is not reached though

And user layers are required to have operational solution taking concrete benefits from bare standards

20

STMicroelectronics

Rationale to support standards

Model-to-model interoperability

Integrate models coming from different IP suppliers

Deliver subsystems and/or virtual platforms to customers

Model-to-tool interoperability

Benefit from CAD tools support

Benefit from best-in-class tools from various providers without migration campaigns

SystemC and IP-XACT standards are required and complementary

21

STMicroelectronics

Adopting standards

OSCI/SystemC

A single language for modeling hardware/software systems

Support multiple abstraction levels

An object-oriented approach built on top of C++ as a set of classes

SPIRIT/IP-Xact

Covers HW IP interfaces, register banks and configurations

Support RTL and TLM abstractions

Based on XML

Benefits of standards

Enable competition between suppliers

Avoid dependency to proprietary format of suppliers

Enable adoption of new approaches inside the company

22

STMicroelectronics

IEEE 1666-2005

SystemC standards evolution

2005

2008

2011

IEEE 1666-2011

OSCI TLM1

PV, PVT

Core TLM I/F

transport

put, get

Payload

REQ, RESP

OSCI TLM2

LT, AT

TLM I/F

b_transport

nb_transport

Payload

tlm_transaction

Extension

Complements

Incl TLM1 and TLM2

23

STMicroelectronics

SystemC TLM: Just add water?

Models and tools

Must be compatible

But not dependent

ESL tool selection

Depending on added value perceived by users

No need to validate a model against all tools

No-tool / minimal tool option to be considered as baseline?

Model-to-model interfaces

TLM2

Mem map, interrupt, etc tbd

Model-to-tools interfaces

CCI (on going)

Other to be defined

Progress still to be done in standards arena

MemoryMap

TLM2

Interrupt

TLM2

TLM2

TLM2

TLM2

TLM2

CCI

24

STMicroelectronics

IP-Xact objectives

Ensure delivery of compatible component descriptions from multiple component vendors,

Enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments),

Describe configurable components using metadata

Enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators)

25

STMicroelectronics

A standardized XML description

Component/Protocol identification and versioning mechanisms

Component interface descriptions

Bus interfaces (ports)

Model parameters (to provide at instantiation)

Software interface: IP register bank descriptions

Hierarchy description

Enable component instantiation and interconnection in standard compliant Design Environments

Enables interconnect description

26

STMicroelectronics

A standardized XML description

Verification

Defines the possibility to plug monitors in the design

Design Automation

XML IP descriptions can include references to IP specific executable configurators/generators

Example: bus matrix interconnect generator

The standard also includes a language agnostic communication interface between CAD tools and the generators

Since IPXACT 1.4, the interface is based on Web Services technologies that enables inter-application remote procedure calls

27

STMicroelectronics

IP-Xact roadmap

December 2004: first release of the schema

Made for RTL descriptions

1.2 : added verification information, but still RTL specific

1.4:

Added ESL (TLM) description capabilities

Defined new tool/generator communication interface: TGI

1.5: basis for the IEEE standard

Evolutions mainly concern register bank descriptions

December 2009: IEEE P1685 standard

Now: the Spirit consortium has merged with Accellera

A new technical committee has been created (chaired by ST)

Progress on recognized limitations and possible new evolutions

28

STMicroelectronics

Agenda




ST TLM Framework

Brief history

Use models

TLM Toolbox with SystemC and IP-Xact


29

STMicroelectronics

Where do we come from?

TransactionalLevel Modeling@ST

TAC v1TLMmodels

2001

TLM Development

2003

Proposal of TLM 1.0 Standard to OSCI

2008

OSCI TLM 2.0 Standard

TAC v3 TLMmodels

2010

Alignment to OSCI TLM 2.0 Standard

TAC v2TLMmodels

2005

OSCI TLM 1.0 Standard

2005

Alignment to OSCI TLM 1.0 Standard

co-verification platforms:RTL models

Performance/temporal models

cycle accurate models

1998 2000

Various Experiments

30

STMicroelectronics

Virtual Prototypes with TLM

Applied in the industry for complex SoCs

System architecture exploration

Anticipation of RTL functional verification

Pre-silicon software development

LT Models

AT Models

Functional Embedded Software

Functional Verification

TLM/RTL Co-simulation

Architecture Analysis

Embedded Software Optimization

LT: Loosely Timed

AT: Approximately Timed

31

IPTG

STMicroelectronics

Functional verification

IP Verification

TLM IPs

In-system Verif.

TBMaster

Memory

Abstract interconnect

C/C++

Input

expected

Testbench

Adapter

Adapter

RTL DUT

TLM DUT

32

STMicroelectronics

TLM for functional verification

Home Video Ips

(by IPs Verification Manager)

About 10 chips have now benefited from the TLM approach, resulting in about 4 times less bugs in our designs. Our improved efficiency relies on faster simulations, reuse of test vectors during the whole verification process (TLM, RTL, co-emulation, emulation), and the ability to quickly develop system-oriented functional tests.

33

STMicroelectronics

Pre-Silicon software development

Enable early development of functional embedded software

Same model is used for verification activities and software development

Hardware blocks modeled with bit true behaviour and communication

Processor models wrapped in SystemC

Native compilation

Instruction accurate

Cycle accurate

Debugger connection

34

STMicroelectronics

Advantages of virtual prototypes for software development

Full control on simulation execution

Full observability

Non regression tests

Easy deployment over large software development teams

Easy evolutions

35

STMicroelectronics

TLM for firmware development

Mobile Video Accelerator

(by Video Subsystem Verification Manager)

For 2nd generation subsystem, we saved 30% of our verification time (in months) by anticipating the firmware verification on TLM platform before any RTL platform, and by concentrating our verification effort only on pure HW

36

STMicroelectronics

TLM Modeling Framework

TLM modeling kit

Infrastructure kit

TLM modeling methodology

TLM model portfolio

TransactionMonitoring

Build environment

Repository

Ip-Xact flow

VSoC STudio

Messaging and configuration

Platform automation kit

37

STMicroelectronics

TLM key technology items

TLMModel

TLM communication protocols

Build infrastructure

(tlm_infra)

Monitoringcapabilities

Configuration capabilities

Register bank support

TLM modeling methodology

SystemC IEEE 1666

SCV

OSCI TLM 2

IPXact IEEE 1685

TLM platformassembly

OSCI CCI

38

STMicroelectronics

SystemC Add-ons : modeling layers and IP models libraries

SystemC

SystemC Channels

OSCI TLM Standard

OCB Models

TAC Protocol

CPU models

ST Cores (STxP70, ST40, etc)

External Cores(ARM, etc)

TLM IP Library

ST IPs

External IPs

39

STMicroelectronics

40

VSoCSTudio

udio

VSoC

Platform assembly

Platform compilation

Configuration editor

Resource browser

Process Activation Chart

STMicroelectronics

What is TAC Protocol?

A useful protocol for functional verification and embedded software development through transaction-accurate communications

Characteristics:

Dedicated to memory mapped bus communication

point-to-point with no broadcast

requires address and data

supports single and block transfers

supports byte-enable for single and block transfers

provide control operations

routers are often used in conjunction with TAC models

TAC stands for Transaction Accurate Communication

41

STMicroelectronics

Register map support

Increase model developer productivity

No standard available yet for simulations

Register map is constructed

From IP-Xact description

Manually

Main features

Register decoding

Register and bitfield access control, setters & getters

Register meta data (synchronization points)

Unified reporting mechanism (using tlm_message)

Interactions with

bus interface

Model

Tools

42

STMicroelectronics

TLM Model/tool interactions

Model

Register bank

Bus Interface

Bus model

CAD

Tool

Transactiondatabase

SystemCKernel

Trans.Monitoring

Configuration

Register introspection

Upcoming OSCI CCI standard

43

STMicroelectronics

TLM SoC Analysis and Debugging Tools

Software Analysis

Hardware Analysis

Statistics

Platform assembly

44

STMicroelectronics

Using IP-Xact description as the reference

IP-Xact descriptions

SoC Top Arch

IP Functional Spec

Datasheet export

IP verification testcase (.h & .c)

Netlist RTL Design

Validation (.h)

Software (.h)

TLM model skeleton (.h & .cpp)

Board spec package

45

STMicroelectronics

TLM model generation and platform assembly

IP FunctionalSpecification

IP-Xact Description

TLM Model

Skeleton

Behavior

TLM model generation

TLM/RTL platform assembly

Register Description

ExistingModel

Other inputs

Header files

Register

tests

SW development

Validation

Other output

RTL

HLS

46

STMicroelectronics

Questions related to IP-Xact and HDS

Consistency of descriptions?

Specification

IP-Xact

TLM model & software

Level of modularity

Separate deliveries?

Expressivity of the description

E.g. Side effects for registers

Connection to higher level information?

E.g. end user scenarios, non functional properties

Software Driver

TLM

Model

IP-Xact

IP/SoC

Description

IP/SoC

FunctionalSpecification

47

STMicroelectronics

Agenda




ST TLM Framework


ESL Ecosystem

TLM value chain

Conclusions

48

STMicroelectronics

ESL ecosystem

Standards and Tools for

Model developers

Virtual Platform integrators

Virtual Platform users

ESL doesnt mean only EDA!

Standards & Examples

CAD Tools

CAD Tools

SW Tools

SW Tools

# of users

License cost

HW

SW

Open Source tools

OSS

49

STMicroelectronics

From enablers to mass market

Enablers:

- Early adoption

- Assess migration effortfrom in house solutions

Mass market:

Functional

Affordable

Experts:

Very focused needs

Sensitive setup

Niche market

License cost

# of users

Architectureexploration

Demontrators

HW/SW integration

VP profiler

New flowsNew standards

1st success story

eSW Debug

HLS

50

STMicroelectronics

Transaction Level Model Value Chain

IEEE 1666-2005

C++ class library

TLM1.0, TLM 2.0 incl.in IEEE 1666-2011

revision

TLM

Modeling

Methodology

SystemC

TLM

Communication

APIs

Modeling

Engineers

Expertise

IPSpecification

TLM Model

Bit accurate

Register accurate

Functionally correct

Communicates through transactions

Variable timing accuracy

SOCSpecification

Interconnect TLM model

IP

IP

IP

IP

IP

High

added value

on top of standards

SoC Virtual Prototype

51

STMicroelectronics

Conclusion

Virtual platforms are key for

pre-silicon software development

Functional verification

Automation of the IP-Xact based flow

Generation of TLM model skeleton

Generation of software header files

Connection to other sources of high-level information still to be done

52

STMicroelectronics

More about it

Read the book:

Ghenassia, F. (ed.): 2005, Transaction-Level Modeling with SystemC. TLM Concepts and Applications for Embedded Systems. Springer. ISBN 0-387-26232-6

Several publications in international conferences and PhD thesis (Moy 2005, Fiandino 2007, Helmstetter 2007, Cornet 2008, Revol 2008, Funchal 2011)

STMicroelectronics

Thank you

Questions?

54

(C) STMicroelectronics, 2010

Workshop - November 2011 - Toulouse

STMicroelectronics

System On Chip modeling with SystemC/TLM

Documents

Transcript of System On Chip modeling with SystemC/TLM