System-on-Chip Design with SystemCece734/SystemC/SystemC...Joachim Gerlach System-on-Chip Design...
Transcript of System-on-Chip Design with SystemCece734/SystemC/SystemC...Joachim Gerlach System-on-Chip Design...
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
System-on-Chip Designwith SystemC
System-on-Chip Designwith SystemC
Joachim Gerlach <[email protected]>
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
1
q Background & Basicsm System-on-Chip Designm C/C++ Based System Designm The SystemC Approachm SystemC Licensing Modelm Open SystemC Community
q Introduction to SystemC 1.0m Modules & Hierarchiem Processesm Ports & Signalsm Data Types & Fixed Point Data Types
q Design Example Am Simple 2-Process Scenario
Contents
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
2
q Design Example Bm JPEG Compression / Decompression Stream
q Design Activitiesm Modelingm Simulationm Debugging
q Tool Supportm Synopsys: SystemC Compilerm CoWare: N2Cm C-Level Design: System Compilerm Frontier Design: AxRT Builder
q Outlook to SystemC 1.1
Contents
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
Background & BasicsBackground & Basics
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
4
Productivity Gap
1970 1980 20001990
1G
100K
1K
1M
100M
10M
10K1K
8008 (source: ICE)
4K
256K
64K
16K
256M
64M
16M
4M
1M
8080
8088
386DX
486DXPentium
Pentium II
memoryprocessors
(0,35 µm)(0,8 µm)
higherabstractionlevel
IP re-use
hardwaresoftwareco-design
designautomation
productivitygap
gates / chip
gates / day
complexity[gates]
(source: MEDEA Design Automation Roadmap 1999)1980 1990 2000
timeWolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
5
System Level Design
q System-on-Chips (SoC) designs
q SoC designs contain
m Multiple design domains: hardware, software, analog, ...
m Multiple source components: DSPs, ASICs, IP-Cores, ...
m Hard constraints: realtime, low power, ...
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
6
System Level Design Flow
soft
war
e ar
chite
ctur
e
hard
war
e ar
chite
ctur
e
hw/swco-simulationco-verification
softwareimplementation
hardwareimplementation
applicationspecific
co-processor
processor &peripherals
memorymap
usersoftware
RTOS
devicedriver
specification
algorithmicmodels
architecturalmodels
functionalvalidation
co-design architecturalvalidation
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
7
Benefits of a C/C++ Based Design Flow
q Productivity aspect
m Specification between architect and implementer is executable
m High speed and high level simulation and prototyping
m Refinement, no translation into hardware (no “semantic gap”)
SoCDesign
SoftwareDesigner
C/C++
HardwareDesigner
HDL
SystemArchitect
C/C++
Marketing& Sales
q System level aspect
m Tomorrow’s systems designers will be designingmostly software and less hardware !
m Co-design, co-simulation, co-verification, co-debugging, ...
q Re-use aspect
m Optimum re-use support by object-oriented techniques
m Efficient testbench re-use
q Especially C/C++ is widespread and commonly used !WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
8
Drawbacks of a C/C++ Based Design Flow
q C/C++ is not created to design hardware !
q C/C++ does not support
m Hardware style communicationl Signals, protocols
m Notion of timel Clocks, time sequenced operations
m Concurrencyl Hardware is inherently concurrent, operates in parallel
m Reactivityl Hardware is inherently reactive, responds to stimuli,
interacts with its environment (→ requires handling of exceptions)
m Hardware data typesl Bit type, bit-vector type, multi-valued logic types,
signed and unsigned integer types, fixed-point typesWolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
9
How to Get “Synthesizable C/C++” ?
q Step-2:
extension by hardware-related components
m new language constructs(HardwareC, C*)
m library based approach(SystemC, Cynlib)
synthesizablesubset
hardware typecommunication
notion of time
concurrency
reactivity
hardwaredata types
C
C++
C
C++
Csynthesizablesubset of C
C++
C
synthesizablesubset of C++
synthesizablesubset of C
q Step-1:
restriction to synthesizable subset
q Step-1 and step-2 can be swapped !
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
10
q The Gap
m Tomorrow’s systems designers will be designingmostly software and little hardware
m A software language is not capable of describingconcurrency, clocks, hardware data types, reactivity
q Requirements
m Allow hardware/software co-design and co-verificationm Fast simulation for validation and optimizationm Smooth path to hardware and softwarem Support of design and architectural re-use
Why SystemC for System Design ?
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
11
q A library of C++ classesm Processes (for concurrency)m Clocks (for time)m Modules, ports, signals (for hierarchy)m Waiting, watching (for reactivity)m Hardware data types
q A modeling stylem ... for modeling systems consisting of multiple
design domains, abstraction levels, architecturalcomponents, real-life constraints
q A light-weight simulation kernelm ... for high-speed cycle-accurate simulation
What is SystemC ?
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
12
How Does it Work ?
JoachimGerlach
StandardC++ Compiler
SystemC
C/C++ HardwareComponent
System
C/C++ TestbenchC/C++ Software
Component
Executable = Simulator
ModelingConstructs
DSP
InterfaceASIC
IP-Core
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
13
4. hand over specification document
1. conceptualize2. simulate in C/C++3. write specification3. document
6. (re)implement in HDL7. (re)validate HDL7. implementation
8. synthesize from HDL
Benefits of a SystemC-Based Design Flow
q Classical HDL based design methodology
hardwaredesigner
HDL
systemarchitect
C/C++
4. hand over specification document
1. conceptualize2. simulate in C/C++3. write specification3. document
6. (re)implement in HDL7. (re)validate HDL7. implementation
8. synthesize from HDL
hardwaredesigner
HDL
systemarchitect
C/C++
4. hand over specification document
1. conceptualize2. simulate in C/C++3. write specification3. document
6. (re)implement in HDL7. (re)validate HDL7. implementation
8. synthesize from HDL
hardwaredesigner
HDL
systemarchitect
C/C++
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
14
Benefits of a SystemC-Based Design Flow
q C/C++ based design methodology
hardwaredesigner
C/C++
systemarchitect
C/C++
1. conceptualize2. simulate in C/C++3. write specification document
4. hand over • executable specification • testbenches • written specification
5. understand specification6. refine in C/C++7. validate re-using testbenches 8. synthesize from C/C++
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
15
The SystemC Approach
q The requirements...
m Fast system modeling containing multiple source components
m Model once for multiple abstraction level, multiple users,multiple purposes
q The problem...
m No common format for describing components
q The approach...
m Promote a standard C/C++ based modeling platform... to model and exchange system level components and IP... to build interoperable tools infrastructure
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
16
The SystemC Approach
q Why C/C++ based ?
m Specification between architect and implementer is executable
m High simulation speed at higher level of abstraction
m Refinement, no translation into HDL (no “semantic gap”)
m Efficient testbench re-use
SoCDesign
SoftwareDesigner
C/C++
HardwareDesigner
HDL
SystemArchitect
C/C++
Marketing& Sales
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
17
S Y S T E M C TM
SystemC Modeling Platform
is...
... a methodology for modeling SoC designs consisting of... DSPs, ASICs, IP-Cores, Interfaces, ...
... a C++ library extending C/C++ by concurrency, timing,... reactivity, communication, signal / data types, ...
... a cycle-accurate high-speed simulation
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
18
SystemC Design Methodology
class libraryand
simulation kernel
your standardC/C++ development
environment
compiler
linker
debugger
libraries
header files
„executable
specification “
......
..
....
executable = simulation
a.out
„make“
source filesfor system and
testbenches
DSPASIC
IP-Core
Interface
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
19
SystemC Key Features
q Concurrency (Sync. and async. processes)
q Notion of time (Multiple clocks with arbitrary phase relation)
q Data types (Bit vectors, arbitrary precision integers, ...) v1.0: arbitrary precision fixed point data types
q Communication (Signals, channels) v1.0: advanced communication protocols
q Reactivity (Watching for events)
q Debug support (Waveform tracing)
q Simulation support
q Support of multiple abstraction levels and iterative refinement
q Support of functional model creation
q ....WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
20
Open Community Licensing
SystemC v0.9including:• Modeling specification • Source code (reference implementation)• Reference manual
click-through web-basedlicense agreement
download
www.SystemC.org
User
Steering Group
q How to get SystemC ?
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
21
Open SystemC Steering Group
q ARM
q Cadence
q CoWare
q Ericsson
q Fujitsu Microelectronics
q Infineon Technologies
q Lucent Technologies
q Motorola
q NEC
q Sony Corporation
q STMicroelectronics
q Synopsys
q Texas InstrumentsWolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
22
Community Charter Members
Actel
Alcatel
Altera Corporation
American Applied Research
Aptix
Arcadia Design Systems
ARC Cores
Aristo Technology
ARM
Billions of Operations Per Second
CAE Plus
Chameleon Systems
Co-Design Automation
CoWare
CSELT
Denali
Ericsson
Frequency Technology
Frontier Design
Fujitsu Microelectronics
Genedax
IKOS Systems
I-Logix
Infineon Technologies
Integrated Silicon Systems
Intellectual Property
Internet CAD
JTA Research
LogicVision
Lucent Technologies
Magma Design Automation
MIPS Technologies
Monterey Design Systems
Motorola
Red Hat
Seva Technologies (Intrinsix)
Sican Microelectronics
Snaketech
Sony Corporation
Stellar Semiconductor
STMicroelectronics
Summit Design
Sun Microsystems
SynaptiCAD
Synchronicity
Synopsys
Tensilica
Texas Instruments
TransModeling
Ultima
Verplex
Viewlogic
Virtio
Virtual Silicon Technologies
Willamette HDL
Wind River Systems
Xilinx
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
23
Open Community Licensing
q Community members
m No licensing fees, anybody / any company is free and welcometo join the community
m Right and responsability to contribute enhancements
m Designers can create and share models with other companies,EDA vendors can build SystemC based tools
q Steering Group
m Drives convergence and interoperability
m Ensures open evolution and structured innovation
q Goal:
m Make SystemC a de-facto-standard for system-level design
m Provide a foundation to build a market uponWolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
24
1997 1998
SceneryV0.9 launches
9/27/1999
1997 DAC Paper
HDL constructs
V1.0 release3/28/2000
1999 2000
fixed point datatypes
q Short History of SystemC
SystemC
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
25
SystemC
q European SystemC Users Group
m Communication platform for SystemC users
m Information flow between SystemC users und Steering Group
m Acceleration of SystemC evolution and standardization
m Events:
take a look at:www-ti.informatik.uni-tuebingen.de/~systemc
January 312000
September 4-82000
March 12-162001
March 282000
2000
1st European SystemC™Users Group Meeting
European SystemC™Users Group Conference
(with DATE’2001)
2001
FDL’2000
2nd European SystemC™Users Group Meeting
3rd European SystemC™Users Group Meeting
SystemC™Release 1.0
June 302000
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
SystemC 1.0SystemC 1.0
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
27
q Modules are basic building blocks of a SystemC designq A module contains processes (Õ functionality)
and/or sub-modules (Õ hierarchical structure)
Modules
JoachimGerlach
SC_MODULE( module_name ) { // Declaration of module ports // Declaration of module signals // Declaration of processes // Declaration of sub-modules SC_CTOR( module_name ) { // Module constructor
// Specification of process type and sensitivity // Sub-module instantiation and port mapping
} // Initialization of module signals
};
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
28
q A module correspond to a C++ class
class data members Ö portsclass member functions Ö processesclass constructor Ö process generation
.....
Modules
JoachimGerlach
SC_MODULE( module_name ) { .....
};
struct module_name : sc_module { .....
};
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
29
q External interface of a moduleq Passing data from and to processes / sub-modulesq Triggering of actions within the moduleq A ports has a mode (direction) and a type
mode: in, out, inouttype: C++ type, SystemC type, user-defined type
q Vector port / port array:
Ports
JoachimGerlach sc_out< int > result [32];
// input port declarationsc_in< type > in_port_name;
// output port declarationsc_out< type > out_port_name;
// bidirectional port declarationsc_inout< type > inout_port_name;
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
30
q Connects a port of one module to the port of another moduleq Local to a moduleq Signal semantics is the same as VHDL and Verilog
deferred assignment semanticsq A signal has a type
type: C++ type, SystemC type, user-defined type
q Vector signal / signal array:
q Internal data storage not by signals but by local variablesLocal variable types: C++ types, SystemC types, user-defined types
Signals
JoachimGerlach
sc_signal< double > a[4];
// signal declarationsc_signal< type > signal_name;
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
31
q Port and Signal Binding
m Ports and signals to be bound need to have the same typem A signal connects two portsm A port is bound to one signal (port-to-signal)
or to one sub-module port (port-to-port)
q Resolutionm SystemC supports resolved ports and signalsm Resolved ports/signals have 4-valued logic type (0,1,Z,X)m Resolved ports/signals allow multiple driversm Resolved vector ports/vector signals
Ports & Signals
JoachimGerlach
sc_in_rv< n > x; // n bits wide resolved input portsc_signal_rv< n> y; // n bits wide resolved signal
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
32
q SystemC provides a special object sc_clockq Clocks generate timing signals to synchronize eventsq Multiple clocks with arbitrary phase relations are supported
q Clock generation:
q Clock binding:
Clocks
JoachimGerlach
sc_clock clock_name (“label”, period, duty_ratio, offset, start_value);
Example: sc_clock my_clk (“CLK”, 20, 0.5, 5, true); true
false
0 5 15 25 35 45 55
5 20
Example: my_module.clk( my_clk.signal() );
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
33
q SystemC supportsm Native C/C++ typesm SystemC typesm User-defined types
q SystemC typesm 2-value (‘0’, ‘1’) logic / logic vectorm 4-value (‘0’, ‘1’, ‘Z’, ‘X’) logic / logic vectorm Arbitrary sized integer (signed/unsigned)m Fixed point types (signed/unsigned, templated/untemplated)
Data Types
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
34
q Integer types:m charm unsigned charm shortm unsigned shortm intm unsigned intm longm unsigned long
q Floating point typesm floatm doublem long double
Native C/C++ Data Types
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
35
SystemC Data Types
JoachimGerlach
Type Description
sc_bit 2-value single bit
sc_logic 4-value single bit
sc_int 1 to 64 bit signed integer
sc_uint 1 to 64 bit unsigned integer
sc_bigint arbitrary sized signed integer
sc_biguint arbitrary sized unsigned integer
sc_bv arbitrary length 2-value vector
sc_lv arbitrary length 4-value vector
sc_fixed templated signed fixed point
sc_ufixed templated unsigned fixed point
sc_fix untemplated signed fixed point
sc_ufix untemplated unsigned fixed point
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
36
q 2-value single bit type: sc_bitm ‘0’=false, ‘1’=true
q 4-value single bit type: sc_logicm ‘0’=false, ‘1’=true, ‘X’=unknown/indeterminate value,
‘Z’=high-impedance/floating value
q Features:m Mixed use of operand types sc_bit and sc_logicm Use of character literals for constant assignments
q
sc_bit / sc_logic
JoachimGerlach
sc_bit / sc_logic operators
Bitwise & (and) | (or) ^ (xor) ~ (not)
Assignment = &= |= ^=
Equality == !=
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
37
q Fixed precision integer typesm Signed: tsc_int<n> (n: word length, 1 ≤ n ≤ 64)m Unsigned: sc_uint<n> (n: word length, 1 ≤ n ≤ 64)
q Arbitrary precision integer typesm Signed: tsc_bigint<n> (n: word length, n > 64)m Unsigned: sc_biguint<n> (n: word length, n > 64)
q Features:m Mixed use of operand types sc_int, sc_uint, sc_bigint,
sc_biguint and C++ integer typesm Truncation and/or sign extension if requiredm 2’s complement representation
sc_int / sc_uint / sc_bigint / sc_biguint
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
38
q
sc_int / sc_uint / sc_bigint / sc_biguint
JoachimGerlach
sc_int / sc_uint / sc_bigint / sc_biguint operators
Bitwise & | ^ ~ >> <<Arithmetic + - * / %Assignment = += -= *= /= %= &= |= ^=Equality == !=Relational < <= > >=Auto-Ink/Dek ++ --Bit/Part Select [] range()Concatenation (,)
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
39
q Arbitrary length bit vector: jsc_bv<n> (n: vector length)
q Arbitrary length logic vector: sc_lv<n> (n: vector length)
q Features:m Assignment between sc_bv and sc_lvm Use of string literals for vector constant assignmentsm Conversions between sc_bv/sc_lv and SystemC integer typesm No arithmetic operation available
q
sc_bv / sc_lv
JoachimGerlach
sc_bv / sc_lv
Bitwise & | ^ ~ >> <<Assignment = += -= *= /= %= &= |= ^=Equality == !=Bit/Part Select [] range()Concatenation (,)Reduction and_reduction() or_reduction() xor_reduction()Conversion to_string()
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
40
q Fixed point typesm sc_fixedm sc_ufixedm sc_fixm sc_ufix
q templated - static arguments (to be known at compile time)
untemplated - nonstatic arguments (to be configured during runtime)
q signed - 2’s complement representation unsigned
q Features:m Operations performed using arbitrary precisionm Multiple quantization and overflow modes
sc_fixed / sc_ufixed / sc_fix / sc_ufix
JoachimGerlach
signedunsigned
untemplated
templatedBackground
& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
41
q Templated signed fixed point type: sc_fixed
q Arguments:m wl - total number of bitsm iwl - number of integer bitsm q_mode - quantization mode (optional)m o_mode - overflow_mode (optional)m n_bits - number of bits for overflow mode (optional)
sc_fixed / sc_ufixed / sc_fix / sc_ufix
JoachimGerlach
sc_fixed< wl, iwl, q_mode, o_mode, n_bits > var_name (init_val);Background
& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
42
q Example:
( 1.75 )10 = ( 0001.1100 )2
1’s complement of ( 0001.1100 )2 = ( 1110.0011 )2
2’s complement of ( 0001.1100 )2 = ( 1110.0100 )2
my_var:
sc_fixed / sc_ufixed / sc_fix / sc_ufix
JoachimGerlach
sc_fixed< 8, 4 > my_var (-1.75);
48
sign bit
integer bits fractional bits
1 1 1 0 0 1 0 0
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
43
q Quantization and overflow modes
Quantization Mode Overflow Mode
Rounding to plus infinity Saturation
Rounding to zero Saturation to zero
Rounding to minus infinity Symmetrical saturation
Convergent rounding Wrap-around
Truncation Sign-magnitude wrap-around
Truncation to Zero
sc_fixed / sc_ufixed / sc_fix / sc_ufix
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
44
q User-defined data types can be used for ports and signals
sc_signal< complex > c;
where class complex { private:
double re; double im;
public: complex () {`re=0.0; im=0.0; } complex (double r, double i) {`re=r; im=i; } void set(double r, double i) { re=r; im=i; } double get_re() { return re; } double get_im() { return im; } int.....
};
User-Defined Data Types
JoachimGerlach
int operator== (const complex &c) const { if ( ( re == c.re ) && ( im == c.im() ) )
return 1; else return 0;
}};
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
45
q Modules may contain sub-modules (Õ hierarchical structure)
q In SC_MODULE:
q In the module constructor of SC_MODULE:
Modules & Hierarchie
JoachimGerlach
// sub-module declarationmodule_type *my_module;
// sub-module instantiation and port mapping SC_CTOR( module_name ) {
my_module = new module_type ( “label”); my_module -> in1 (sig1);
my_module -> in2 (sig2); my_module -> out1 (sig3);}
sig2
sig1sig3
in2
in1out1
my_module
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
46
ba
e
dc
alu
d = ( a + b ) - c
Modules & Hierarchie
JoachimGerlach
i2i1
o1
plus
i2i1
o1
minus
q Example:SC_MODULE( alu ) { sc_in<int> a; sc_in<int> b; sc_in<int> c; sc_out<int> d;
plus *p; minus *m;
sc_signal<int> e;
SC_CTOR( alu ) {
p = new plus ( "PLUS“ ); p->i1 (a); p->i2 (b); p->o1 (e);
m = new minus ( "MINUS“ ); (*m) (e,c,d); }};
SC_MODULE( plus ) { sc_in<int> i1; sc_in<int> i2; sc_out<int> o1; .....
};
SC_MODULE( minus ) { sc_in<int> i1; sc_in<int> i2; sc_out<int> o1; .....};
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
47
q Process Semanticsm Encapsulates functionalitym Basic unit of concurrent executionm Not hierarchical
q Process Activationm Processes have sensitivity listsm Pocesses are triggered by events on sensitive signals
q Process Typesm Method (SC_METHOD)
asynchronous block, like a sequential function
m Thread (SC_THREAD) asynchronous process
m Clocked Thread (SC_CTHREAD) synchronous process
Processes
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
48
Processes
JoachimGerlach
SC_CTHREAD(p,clock.pos());
SC_CTHREAD(p,clock.neg());
SC_METHOD SC_THREAD SC_CTHREAD
executionsuspend no yes yes
suspend& resume - wait() wait()
wait_until()
construct &sentisizemethod
SC_METHOD(p);
sensitive(s);sensitive_pos(s);sensitive_neg(s);
SC_THREAD(p);
sensitive(s);sensitive_pos(s);sensitive_neg(s);
triggered by signal events by signal events by clock edge
infiniteloop no yes yes
sequential logicat higher designlevels
modeling example (hardware)
combinationallogic
sequential logicat RT level(asynchronousreset, etc.)
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
49
q Declaration of member function (in SC_MODULE)
q Instantiation (in module constructor of SC_MODULE)
q Definition of member function(in SC_MODULE or somewhere else)
Processes
JoachimGerlach
// process declarationvoid my_process ();
// specification of process type and sensitivity SC_CTOR( module_name ) { SC_METHOD( my_process );
sensitive << sig1 << sig2;}
// process specificationvoid module_name::my_process () { .....}
i2
i1o1
plus
o1 = i1 + i2
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
50
q Example: SC_METHOD
Processes
JoachimGerlach
SC_MODULE( plus ) { sc_in<int> i1; sc_in<int> i2; sc_out<int> o1;
void do_plus();
SC_CTOR( plus ) { SC_METHOD( do_plus ); sensitive << i1 << i2; }};
void plus::do_plus() { int arg1; int arg2; int sum;
arg1 = i1.read(); arg2 = i2.read(); sum = arg1 + arg2; o1.write(sum);}
void plus::do_plus() { o1 = i1 + i2;}
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
51
q Example: SC_THREAD
Processes
JoachimGerlach
SC_MODULE( plus ) { sc_in<int> i1; sc_in<int> i2; sc_out<int> o1;
void do_plus();
SC_CTOR( plus ) { SC_THREAD( do_plus ); sensitive << i1 << i2; }};
void plus::do_plus() { int arg1; int arg2; int sum;
while ( true ) { arg1 = i1.read(); arg2 = i2.read(); sum = arg1 + arg2; o1.write(sum);
wait(); }}
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
52
q Example: SC_CTHREAD
Processes
JoachimGerlach
SC_MODULE( plus ) { sc_in_clk clk;
sc_in<int> i1; sc_in<int> i2; sc_out<int> o1;
void do_plus();
SC_CTOR( plus ) { SC_CTHREAD( do_plus, clk.pos() ); }};
void do_plus() { int arg1; int arg2; int sum;
while ( true ) { arg1 = i1.read(); arg2 = i2.read(); sum = arg1 + arg2; o1.write(sum);
wait(); }}
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
53
q Suspend / reactivate process execution (SC_THREAD, SC_CTHREAD)
m Suspension: wait()m Reactivation: event on a sensitive signal
q Halt process execution until an event occurs (SC_CTHREAD only)
m wait_until ( my_bool_sig.delayed() == true )
q Transfer control to a special code sequenze if a specified condition occursm watching ( reset.delayed() == true )m Typical example: watching for reset signal
m Global watching: (SC_THREAD, SC_CTHREAD)- watching condition specified in the module constructor- control is transfered to the beginning of the process (to be handled there)
m Local watching: (SC_CTHREAD only)- allows to specifiy the process region to be watched- using macros W_BEGIN, W_DO, W_ESCAPE, W_END- can be nested and combined with global watching
Waiting and Watching
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
54
Cycle-Accurate Simulation Scheduler
JoachimGerlach
All clock signals that change their valueat the current time areassigned their new value.
All SC_METHOD / SC_THREAD processes with inputs that havechanged are executed. The entire bodies of SC_METHODprocesses are executed. SC_THREAD processes are executeduntil the next wait() statement suspends execution.SC_METHOD / SC_THREAD processes are not executed in afixed order.
All SC_CTHREAD processes that are triggered have theiroutputs updated and are saved in a queue to be executed instep 5. All outputs of SC_METHOD / SC_THREAD processesthat were executed in step 1 are also updated.
Step 2 and step 3 are repeated until no signal changes ist value.
All SC_CTHREAD processes that were triggered and queued instep 3 are executed. There is no fixed execution order of theseprocesses. Their outputs are updated at the next active edge(when step 3 is executed), and therefore are saved internally.
Simulation time is advanced to the next clock edge and thescheduler goes back to step 1.
Step 1:
Step2:
Step3:
Step 4:
Step 5:
Step6:
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
Design Example ADesign Example A
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
56
int
bool
int
bool
SystemC: Example-1
Example
Two processes (process_1 and process_2)alternately incrementing an integer value
b
ready_b
a
ready_a
+3
process_2
a
ready_a
b
ready_b
+5
process_1
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
57
Source Code File Structure
systemc.h process_1.h process_2.h
process_1.cc process_2.cc main.cc
g++
a.out
executable = simulation
library
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
58
Module: process_1
// header file: process_1.h
SC_MODULE( process_1 ) {
// Ports sc_in_clk clk; sc_in<int> a; sc_in<bool> ready_a; sc_out<int> b; sc_out<bool> ready_b;
// Process functionality void do_process_1();
// Constructor SC_CTOR( process_1 ) { SC_CTHREAD( do_process_1 , clk.ps() ); }
};
// implementation file: process_1.cc
#include "systemc.h"#include "process_1.h"
void process_1::do_process_1(){ int v;
while ( true ) { wait_until( ready_a.delayed() == true ); v = a.read(); v += 5; cout << "P1: v = “ << v << endl; b.write( v );
ready_b.write( true ); wait(); ready_b.write( false ); }}
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
59
Module: process_2
// header file: process_2.h
SC_MODULE( process_2 ) {
// Ports sc_in_clk clk; sc_in<int> a; sc_in<bool> ready_a; sc_out<int> b; sc_out<bool> ready_b;
// Process functionality void do_process_2();
// Constructor SC_CTOR( process_2 ) { SC_CTHREAD( do_process_2 , clk.ps() ); }
};
// implementation file: process_2.cc
#include "systemc.h"#include "process_2.h"
void process_2::do_process_2(){ int v;
while ( true ) { wait_until( ready_a.delayed() == true ); v = a.read(); v += 3; cout << "P2: v = “ << v << endl; b.write( v );
ready_b.write( true ); wait(); ready_b.write( false ); }}
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
60
Top-Level Module: main
// implementation file: main.cc
#include "systemc.h"#include "process_1.h"#include "process_2.h"
int sc_main (int ac,char *av[]){ sc_signal<int> s1 ( “Signal-1“ ); sc_signal<int> s2 ( “Signal-2“ ); sc_signal<bool> ready_s1 ( “Ready-1“ ); sc_signal<bool> ready_s2 ( “Ready-2“ );
sc_clock clock( "Clock“ , 20 , 0.5 , 0.0 );
process_1 p1 ( “P1“ ); p1.clk( clock ); p1.a( s1 ); p1.ready_a( ready_s1 ); p1.b( s2 ); p1.ready_b( ready_s2 );
process_2 p2 ( “P2“ ); p2.clk( clock ); p2.a( s2 ); p2.ready_a( ready_s2 ); p2.b( s1 ); p2.ready_b( ready_s1 );
s1.write(0); s2.write(0); ready_s1.write(true); ready_s2.write(false);
sc_start(100000);
return 0;}
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
61
Simulation Results
q Simulation output
SystemC (TM) Version 1.0 --- Apr 4 2000 10:12:32ALL RIGHTS RESERVED
Copyright (c) 1988-2000 by Synopsys, Inc.
P1: v = 5P2: v = 8P1: v = 13P2: v = 16P1: v = 21P2: v = 24P1: v = 29P2: v = 32P1: v = 37P2: v = 40P1: v = 45P2: v = 48P1: v = 53P2: v = 56P1: v = 61P2: v = 64P1: v = 69P2: v = 72P1: v = 77P2: v = 80.....
simulation speed:
simulation of 100.000 cyclestakes about 0.08 seconds on a Sun Ultra Sparc 5
(384 MByte main memory)
(output skipped) comparison tosimulation speed of SystemC 0.9:
simulation of 100.000 cyclestakes about 0.31 seconds
on the same machineWolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
Design Example BDesign Example B
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
63
q Background:
SystemC Design Example
„bottom-up“
Transforming HDL into SystemCCreating new designs in SystemC
HDL„non-coded“
SystemC
„top-down“
SystemC
C / C++
Transforming C/C++ into SystemC • Many algorithms exist in C/C++ • Many standardization committees • (e.g., ISO) use C specifications
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
64
q Application: JPEG compression and decompression stream
q Reference implementation:m 16 modules, approx. 950 lines of C++ codem by T. Thissenhusen, TU Dresden, Germany
SystemC Design Example
Input Picture(pgm)
JPEGEncoderReader
Output Picture(pgm)
JPEGDecoder Writer
Compresseddata stream
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
65
IRLEH
IQuant
IZigZag
IDCT
DCT
ZigZag
Quant
RLEH
SystemC Design Example
Decoder
Encoder
Writer
output pgm-file
Reader
input pgm-file start
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
66
SystemC Design Example
struct Block { char data[8][8]; ....};
struct Matrix_64x12 { short data[64]; ....};
char data;
struct Coeff_8x8 { short data[8][8]; ....};
Encoder
ZigZag
DCT
ZigZag
Quant
RLEH
clk
boolCoeff_8x8
data_in start
bool
ready
boolMatrix_64x12
data_out data_out_ready
bool
data_ok
JoachimGerlach
bool
ready
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
67
IRLEH
IQuant
IZigZag
IDCT
DCT
ZigZag
Quant
RLEH
SystemC Design Example
Decoder
Encoder
Writer
output pgm-file
Reader
input pgm-file start
data dataready ready
dataready
data dataready ready
IRLEH
IQuant
IZigZag
IDCT
DCT
ZigZag
Quant
RLEH
Decoder
Encoder
Writer
output pgm-file
Reader
input pgm-file start
readydata
dataready
data
data
data
data
data
ready
ready
ready
ready
ready
dataready
dataready
dataready
dataready
DCT
ZigZag
Quant
RLEH
data
data
data
data
data
ready
ready
ready
ready
ready
dataready
dataready
dataready
dataready
dataready
IRLEH
IQuant
IZigZag
IDCT
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
Design ActivitiesDesign Activities
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
69
q Modeling
q Simulation
q Debugging
Design Activities
JoachimGerlach
m Module for “zigzag”computation
m Generation and run of an executable specification
m Techniques for checking the functionality of the system
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
70
Modeling
JoachimGerlach
#include <systemc.h>#include "global.h"
SC_MODULE(zigzag) {
sc_in_clk clk;
sc_in<Coeff_8x8> data_in; sc_in<bool> start; sc_in<bool> data_ok;
sc_out<Matrix_64x12> data_out; sc_out<bool> ready; sc_out<bool> data_out_ready;
void do_zigzag();
SC_CTOR(zigzag) { SC_CTHREAD(do_zigzag,clk.pos()); }};
zigzag.h
zigzag.ccvoid zigzag::do_zigzag() {
Coeff_8x8 fuv; Matrix_64x12 result; unsigned char u, v, a, dir;
while(true) {
ready.write(true); data_out_ready.write(false); wait_until(start.delayed()==true); ready.write(false);
fuv = data_in.read();
// zigzag u = 0; v = 0; dir = 1; // dir == 1: upwards, dir == 0: downwards
for ( a = 0; a < 64; a++ ) {
result.put ( a, (WORD) (fuv.get (v,u) ) );
if ( v == 0 ) if ( dir ) { u++; dir = 0; } else { u--; v++; } else if ( v == 7 ) if ( !dir ) { u++; dir = 1; } else { u++; v--; } else if ( u == 0 ) if ( !dir ) { v++; dir = 1; } else { u++; v--; } else if ( u == 7 ) if ( dir ) { v++; dir = 0; } else { u--; v++; } else if ( dir ) { u++; v--; } else { u--; v++; } }
data_out.write(result); data_out_ready.write(true); wait_until(data_ok.delayed()==true); }}
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
71
q Generation of an executable specification
Simulation
JoachimGerlach
executable = simulator
systemc.h reader.h writer.h
reader.cc writer.cc jpeg.cc
g++
run
library
......
......Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
72
q Simulation control
m Simulation start:sc_start() / sc_start(n) from the top-level function sc_main()
m Simulation stop:sc_stop() from within any process
q Advanced simulation control:“self-made” clock by sc_initialize() and sc_cycle(n)
Simulation
JoachimGerlach
true
false
0 10 20 30 40
sc_clock my_clock (“CLK”, 20, 0.5 );
sc_start(200); sc_initialize(); for (int i=0; i<=200; i++) { clock = 1; sc_cycle(10); clock = 0; sc_cycle(10); }
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
73
q Running the executable specification
Simulation
JoachimGerlach
> ./run motorbike.pgm motorbike2.pgm
SystemC (TM) Version 1.0 --- May 22 2000 14:21:01 ALL RIGHTS RESERVED Copyright (c) 1988-2000 by Synopsys, Inc.Comment: CREATOR: XV Version 3.10a Rev: 12/29/94SystemC: simulation stopped by user.>>
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
74
q Results of an executable run
Simulation
JoachimGerlach
JPEGEncoderReader
JPEGDecoder Writer
input picture(motorbike.pgm)
output picture(motorbike2.pgm)
compressiondecompression
stream
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
75
Debugging
JoachimGerlach
q Observation of simulation results
q Adding (C/C++) assertions/debug outputs to the source code
q Using SystemC debugging features
q Using standard debugging tools (gdb, Purify,...)
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
76
Debugging
JoachimGerlach
q Adding debug outputs to the source code
void zigzag::do_zigzag() {
.....
static int no_of_zigzags = 0;
while(true) {
.....
// zigzag computation .....
no_of_zigzags++; cout << „number of zigzags:“ << no_of_zigzags << endl;
..... }}
zigzag.ccBackground
& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
77
q Running the executable specification
Debugging
JoachimGerlach
> ./run motorbike.pgm motorbike2.pgm
SystemC (TM) Version 1.0 --- May 22 2000 14:21:01 ALL RIGHTS RESERVED Copyright (c) 1988-2000 by Synopsys, Inc.Comment: CREATOR: XV Version 3.10a Rev: 12/29/94number of zigzags: 1number of zigzags: 2number of zigzags: 3number of zigzags: 4.....number of zigzags: 1099number of zigzags: 1100number of zigzags: 1101number of zigzags: 1102SystemC: simulation stopped by user.>>
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
78
Debugging
JoachimGerlach
q Using SystemC debugging features: sc_time_stamp()
void zigzag::do_zigzag() {
.....
static int no_of_zigzags = 0;
while(true) {
.....
// zigzag computation .....
no_of_zigzags++; cout << „cycle: “ << sc_time_stamp(); cout << „ - number of zigzags:“ << no_of_zigzags << endl;
..... }}
zigzag.ccBackground& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
79
q Running the executable specification
Debugging
JoachimGerlach
> ./run motorbike.pgm motorbike2.pgm
SystemC (TM) Version 1.0 --- May 22 2000 14:21:01 ALL RIGHTS RESERVED Copyright (c) 1988-2000 by Synopsys, Inc.Comment: CREATOR: XV Version 3.10a Rev: 12/29/94cycle: 5 - number of zigzags: 1cycle: 8 - number of zigzags: 2cycle: 11 - number of zigzags: 3cycle: 14 - number of zigzags: 4.....cycle: 3299 - number of zigzags: 1099cycle: 3302 - number of zigzags: 1100cycle: 3305 - number of zigzags: 1101cycle: 3308 - number of zigzags: 1102SystemC: simulation stopped by user.>>
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
80
Debugging
JoachimGerlach
q Using SystemC debugging features: waveform tracing
jpeg.ccint sc_main( int argc, char *argv[] )
{ .....
// waveform tracing if ( (argc == 4) && (strcmp(argv[3],"w") == 0) ) {
sc_trace_file* tf = sc_create_wif_trace_file( „wave“ );
sc_trace( tf, clk.signal(), „clock“ ); sc_trace( tf, encoder_is_ready, „encoder_is_ready“ ); sc_trace( tf, orig_data_ready, „start_dct“ ); sc_trace( tf, e.data_out_ready_1, „start_quant“ ); sc_trace( tf, e.data_out_ready_2, „start_zigzag“ ); sc_trace( tf, e.data_out_ready_3, „start_rleh“ ); sc_trace( tf, decoder_is_ready, „decoder_is_ready“ ); sc_trace( tf, comp_data_ready, „start_idct“ ); sc_trace( tf, d.data_out_ready_1, „start_iquant“ ); sc_trace( tf, d.data_out_ready_2, „start_izigzag“ ); sc_trace( tf, d.data_out_ready_3, „start_irleh“ ); } .....}
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
81
> ./run motorbike.pgm motorbike2.pgm w
SystemC (TM) Version 1.0 --- May 22 2000 14:21:01 ALL RIGHTS RESERVED Copyright (c) 1988-2000 by Synopsys, Inc.WARNING: Default time step (1 s) is used for WIF tracing.Comment: CREATOR: XV Version 3.10a Rev: 12/29/94SystemC: simulation stopped by user.>>
q Running the executable specification (with “w” parameter)
Debugging
JoachimGerlach
> viewer wave.awif &>>
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
Tool SupportTool Support
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
83
Synopsys SystemC Compiler
q SystemC for system modeling
System
ModelingConstructs
C/C++ Hardware/System
StandardC++ Compiler
Executable = Simulator != Debugger
SystemC
C/C++ Testbench C/C++ Software
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
84
Synopsys SystemC Compiler
q SystemC Compiler C++ synthesis in the HW flow
SystemCTM Compiler
Behavioral synthesis RTL synthesis
db form(This flow is not supported currently)db or HDL
format
db form
Model using SystemC
Gate level netlist WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
85
Synopsys SystemC Compiler
q Refinement for implementation
System SpecificationSystem Specification
Refine StructureRefine Structure•• Partition into blocks that will be Partition into blocks that will be independently synthesized/refined independently synthesized/refined•• Refine interfaces for communication Refine interfaces for communication
Refine ControlRefine Control•• Specify I/O protocol Specify I/O protocol••Specify clock domainsSpecify clock domains•• Specify latency, throughput Specify latency, throughput•• Specify FSM & datapath for RTL Specify FSM & datapath for RTL
Refine DataRefine Data•• Use bit-true types Use bit-true types•• Select appropriate Select appropriate bit widths bit widths
System ImplementationSystem Implementation
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
86
Synopsys SystemC Compiler
q Behavioral Level Flow
Timed DB Generation
Gate Level Netlist
Latency/PipelineConstraints
Schedule
High-Level Synthesis
Compile
Timed DB File
Cycle-Accurate DB
HDLCo-Simulation
Cycle-AccurateHDL
RemoveDesign
Code?
SystemC ViewReportsOK?
yes
yes
no
no
Timed DB File
BehavioralCode
SystemC Compiler
Initial Constraints
Check Design
Time/Area Estimates
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
87
Synopsys SystemC Compiler
q Hardware Implementation Flow
FunctionalDesign
ArchitecturalDesign
RT LevelDesign
Gate LevelDesign
Refinement(communication,
timing, memories)
Refinement(resources, scheduling,allocation, FSM design)
SystemC CompilerBehavioral Flow
SystemC CompilerRTL Flow
IQ Block
Controller
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
88
Synopsys SystemC Compiler
q Benefits
m Rapid time to market
– fast refinement from functional model behavioral model
– accommodating late spec changes
m Graphical analysis of design
m High quality of results
– tight integration into Synopsys synthesis flow
– flexibility for datapath components
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
89
CoWare N2C
q Gaps in System Design
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
90
CoWare N2C
q System-Level Design with CoWare N2C
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
91
CoWare N2C
q N2C Workbench
m Hierarchical design browser (architecture, functionality)
m Source code editor (context sensitive)
m Project manager (partition management)
q CoWare Support
m CoWare N2C supports a top-down design flow for HW/SWco-design from UTF to RTL
m Co-simulation of different languages
m Fast design exploration and HW/SW partitioning
m Allows for efficient IP reuse and delivery
m Provides synthesis of communicationWolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
92
System Compiler (C Level Design)
Class-based C++(System C++)
nativeC/C++
RTLHDL
bit-accurate (fixed and floating)simulation libraries
native C/C++simulation
CSim/System C++simulation
System CompilerC/C++ synthesis
q System Compiler
m supports full ANSIC and C++
m provides complex datastructures, static pointeranalysis, abstraction,hierarchy
m output is RT level HDL(VHDL or Verilog)
q CSim
m executable specification
m discrete event simulation
m abstraction: temporal time,data values, functionality
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
93
A|RT Builder (Frontier Design)
ANSIC
HWResourceLibrary
HWResourceLibrary
hwresourcelibrary
FPGA ASIC
schedule operationsschedule operations
map to architecturemap to architecture
edit/compileedit/compile create architecturecreate architecture
build RTL codebuild RTL code
architectureoptimization
source codetuning
performance analysis
logic synthesis
vendor HDL
legacy HDL
system specificationembedded software
datapath resources(arithmetic, memory)
WolfgangRosenstiel
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
SystemC 1.1Outlook
SystemC 1.1Outlook
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
95
SystemC 1.1 Design Flow
JoachimGerlach
Matlab C++ SDL Esterel ......
software
RTOS
BCA
functionaldecomposition
Abstr.RTOS
RTL
UTF
TF
SystemC1.1
hardware
assign„execution time“
refinebehavior
targetRTOS/core
taskpartitioning
hw/sw partitioning refine communication
untimedfunctional
timedfunctional
cycleaccurate
design explorationperformance analysis
hw/sw partitioning
bus cycleaccurate
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
Joachim Gerlach System-on-Chip Design with SystemC
University ofTübingen
Department ofComputer
Engineering
96
q UTF: UnTimed Functionalm Functional decomposition of a systemm Architecture, timing, inter-block communication is abstractedm Maximally sequential form by RPC (Remote Procedure Call)m RPC: abstract (master/slave-)ports, multi-point link objects
q TF: Timed Functionalm RPC also, but processes may be assigned a run time
q BCA: Bus Cycle Accuratem Abstract ports refined to bus ports with data, adress, control
terminals and communication protocols
q CA: Cycle Accuratem SystemC 1.0 level
Design Levels in SystemC 1.1
JoachimGerlach
Background& Basics
SystemC 1.0
DesignExample A
DesignExample B
DesignActivities
ToolSupport
SystemC 1.1
University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
S Y S T E M C TM
Questions& AnswersQuestions
& Answers