MCEN5228-011/4228-011: Microsystems IntegrationHomework #9, Due Date: Monday, April 17

The Word file of the homework is posted on the class web site. Email your PDF or Word file with answers to leeyc@colorado.edu before the class on the 17th. There is a penalty, e.g. 5 to 25 points, for late submission.

Name: ________________________________, Email: ________________________________

1. (15 points) Estimate the total power dissipation levels of the driver optimum-designed for the 2cm interconnects. You should consider every CMOS device in the cascaded driver. Study the cases with 1.2 volts applied at a frequency of 2GHz.

2. (10 points) For a microstripe line shown below, line width (W) is 50 µm, the dielectric substrate’s thickness (h) is 25µm. The dielectric constant is r=4.0. What is the impedance? The calculation formula was provided in the first set of lecture slides on the electrical design. What is the capacitance of the line with a length of 1cm? If we change the W to be 10µm, what is the dielectric thickness in order to keep the impedance unchanged? What is the capacitance of this 10µm line with the same length of 1cm and the same impedance?

3. (8 points) AVP (Advanced VLSI Packaging) technology for multichip modules has been discussed several times in the class. Identify five features in the AVP structure that are critical to reduce the simultaneous switching noise. Note: Some suggestions for the noise reduction are to: a) improve IC design; b) use decoupling capacitors near devices; c) use P/G planes instead of P/G lines; d) increase number of P/G connections; and e) use short P/G connections.

MCEN5228-011/4228-011: Microsystems Integration

4. (7 points) Xilinx SSI technology shown below represents one of the best MCM configurations. Another figure illustrates typical single-chip packages interconnected on a printed circuit board (PCB). Using the PCB as a reference, please identify 3 major advantages and 3 major disadvantages of the SSI.

5. (10 points) Figures below illustrate two chips with area arrays of solder connections. The diameter of the solder pads is 100µm, and the pitch of the array is 200µm. One of the major challenges for the flip-chip assembly is the fan-out of interconnects on an MCM. As shown in the small chip, every solder connection is connected to outside of the chip through an interconnect line. Let’s assume the line width is the same as the line spacing. We have 100µm spacing available for the interconnects; as a result, we can fan out all the solder connections on a single layer with the line width/spacing up to 33 µm. A) Please estimate the line width/spacing required for the large chip if we want to fan out all the solder connections on a single layer. B) In the second case, we assign the yellow-colored pads to be power/ground connections to MCM’s power/ground planes. As a result, fan-out of these power/ground connections is not needed. What is the corresponding line width/spacing for a single-layer fan-out?

MCEN5228-011/4228-011: Microsystems Integration