SwitchLevel and Memories

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Switch Level Modeling

These Slides are just for reference, for the detailed study follow the text book.

You can Refer Verilog HDL by Samir Palnitkar (Chapter-11)



Switch Level Modeling

MOS Switches

MOS switch keywords

nmos

Pmos



Instantiation of NMOS and PMOS Switches

Instantiation with Instance Name

o nmos n1(out, data, control); //instantiate a nmos switcho pmos p1(out, data, control); //instantiate a pmos switch

Instantiation without Instance Nameo nmos (out, data, control); //instantiate an nmos switch; no

instance name

o pmos (out, data, control); //instantiate a pmos switch; no

instance name



Logic Tables for NMOS and PMOS

• nmos switch conducts when its control signal is 1. If

the control signal is 0, the output assumes a highimpedance value.

• Similarly, a pmos switch conducts if the control

signal is 0.



CMOS Switches

A cmos device can be modeled with a nmos and a pmosdevice.



Instantiation of CMOS Switch

Instantiation with Instance Name:

cmos c1(out, data, ncontrol, pcontrol);//instantiate cmos gate.

Instantiation without Instance Name:

cmos (out, data, ncontrol, pcontrol); //no instance name given.

OR



Power and Ground The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are

needed when transistor level circuits are designed. Power and ground sources are defined with keywords supply1

and supply0.

Supply1 are equivalent to Vdd in circuits and place a logical 1 on

a net.

Supply0 are equivalent to ground or Vss and place a logical 0 on a

net.

supply1 vdd;supply0 gnd;

assign a = vdd; //Connect a to vdd

assign b = gnd; //Connect b to gnd



Bidirectional Switches

Switches that conduct in both directions.

Signals on either side of the device can be the driver signal.

Three keywords are used to define bidirectional switches:



Resistive Switches

Higher source-to-drain impedance than regular switches.

Reduce the strength of signals passing through them.

rnmos rpmos //resistive nmos and pmos switches

rcmos //resistive cmos switch



CMOS Xor Gate



Delay Specification on Switches

.



Example:CMOS Nor Gate

.



Switch Level Verilog for Nor Gate

//Define our own nor gate, my_nor

module my_nor(out, a, b);output out;

input a, b;

//internal wires

wire c;

//set up power and ground linessupply1 pwr; //pwr is connected to Vdd (power supply)

supply0 gnd ; //gnd is connected to Vss(ground)

//instantiate pmos switches

pmos (c, pwr, b);

pmos (out, c, a);

//instantiate nmos switches

nmos (out, gnd, a);

nmos (out, gnd, b);

endmodule



2 to 1 Multiplexer using CMOS Switches .



Switch Level Verilog Description of 2 to 1 Multiplexer

//Define a 2-to-1 multiplexer using switches

module my_mux (out, s, i0, i1);output out;

input s, i0, i1;

//internal wire

wire sbar; //complement of s//create the complement of s

// use my_nor defined previously.

my_nor nt(sbar, s, s); //equivalent to a not gate

//instantiate cmos switchescmos (out, i0, sbar, s);

cmos (out, i1, s, sbar);

endmodule



CMOS flip-flop



Designs in AOI & OAI Form

And-Or-Invert Form Or-And-Invert Form

X= ((A.B)+(C.D))’ Y= ( ( a+e ).( b.f ) )’



Practice

Design 4:1 Mux using CMOS Switches.



Introduction

A memory unit is a device to which binary information

is transferred for storage and from which information is

retrieved when needed for processing.

There are two types of memories that are used in digitalsystems: random-access memory(RAM) and read-only

memory(ROM).

RAM can perform both Write and Read operations.

ROM can perform Read operation.



• Static RAM (SRAM) consists essentially of internal Latches

that store the binary information.

• Dynamic RAM (DRAM) stores the binary information in the

form of electric charges on capacitors provided inside the

chip by MOS transistors (require refreshing).



Read Only Memory

Electronics and Communication Engineering26

Read Only Memories (ROM) or Programmable ReadOnly Memories (PROM) have:

N input lines,

M output lines, and

2N decoded minterms.

Fixed AND array with 2N outputs implementing all N-

literal minterms.

Programmable OR Array with M outputs lines to formup to M sum of minterm expressions.



Read Only Memory


A program for a ROM or PROM is simply a multiple-output truth table

If a 1 entry, a connection is made to the corresponding minterm

for the corresponding output

If a 0, no connection is made

Can be viewed as a memory with the inputs as addresses of

data (output values), hence ROM or PROM names!



Representation of Array

.



Read Only Memory Example


Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a

“decoder” with 3 inputs and 8 outputs implementing min-terms.

The programmable "OR“ array uses a single line torepresent all inputs to anOR gate. An “X” in the array corresponds to attaching the

min-term to the OR

What are functions F3, F2 , F1 and F0 in terms of (A,B,C)?

D7 D6

D5 D4

D3 D2 D1 D0

A2

A1

A0

A

B

C

F0 F1 F2 F3

X XX

X

X

X

X

X

X

X



Solution


F3=ABC+AB’C+A’BC’

F2=ABC+A’B’C’

F1=A’B’C+AB’C’

F0=ABC+AB’C+A’B’C



Practice Problems:

Design Adders , Subtractor, Multiplexers etc.

E l



Example



6T SRAM C ll



6T SRAM Cell



Declaration of 2 Dimensional Array of Register Variables



How to initialize Memory



Contd..



Example



Example: Single Port Synchronous RAM

(Read/Write)

E l Si gl P t A h



Example: Single Port Asynchronous

RAM (Read/Write)

Verilog Code for ROM



Verilog Code for ROM

reg [7:0] data;

SwitchLevel and Memories

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