Sweep Generator
description
Transcript of Sweep Generator
Digital Sweep Generator
The digital sweep generator is based on the Dig_TX board. The DSP and its memory, as well as theaudio- and RF-ADCs remain unassembled. Signal synthesis is completely performed within the FPGA.A miniMAX-40 module with a little hand-made logic on a prototype board controls the sweep generator.The FPGA master clock frequency is 80 MHz.
A seventh order reconstruction filter is implemented at the RF-DAC output. With a 40 MHz Nyquistfrequency, the bandwidth design target for the sweep generator was 100 kHz ~ 30 MHz. The lowerfrequency is limited by a transformer between the DAC and the LP filter, while the upper frequency islimited by the filter roll-off.
The maximum usable frequency is that frequency below the Nyquist frequency (fn = fclk/2; fclk=masterclock frequency), at which the alias frequency fa = fclk-fo (fa=alias frequency, fo=desired outputfrequency) is still sufficiently attenuated. The term „sufficiently“ is application dependent and meansthat the alias signal and its intermodulation products must not disturb the desired signal. Generally it isa good idea to attenuate the alias signal to below the required signal-to-noise ratio of the DDS signalgenerator. For the digital sweep generator, which shall be used for measurement applications, aminimum SNR of 60 dB seems adequate. While that is not extremely good if compared tocommercially available sweep generators, it is sufficient for amateur measurements. In most cases,the SNR is actually better than 70 dB.
In order to keep the passband ripple flat, so that a wide frequency range can be covered withoutintroducing artifical ripple due to the anti-aliasing filter response, a seventh order Butterworth lowpassfilter was initially considered and implemented. Its attenuation at 30 MHz was below 1 dB, but theattenuation at the alias of 50 MHz was less than 30 dB. The filter has been designed for 50 input andoutput impedance. The following table shows the calculated and the really selected capacitances andinductivities. Also the number of windings on an Epcos (Siemens) double hole core type B62152 A8-X17 (AL=9nH/W2) for the inductivities are listed. Fractions are estimated values.
Seventh order Butterworth filter (-1dB at 30 MHz; -30dB at 58 MHz)
component ideal value real values turns
L1 300 nH 297 nH 5 3/4
L2 482 nH 410 nH 6 3/4
L3 300 nH 297 nH 5 3/4
C50 43 pF 44 pF -
C51 174 pF 165 pF -
C52 174 pF 165 pF -
C53 43 pF 44 pF -
Simulation results with real values:
10.0M 30.0M 100.0M-75.00
-55.00
-35.00
-15.00
5.00
AC AnalysisAplac 7.62 Student version FOR NON-COMMERCIAL USE ONLY
Mag
f/HzMagdB(Vac(Outp
It turned out, that the attenuation of the alias frequency was not satisfactory. Either a higher orderButterworth filter or a change of the filter topology to a much steeper Chebychev filter of the sameseventh order was required. A higher order Butterworth filter will be considered for a future redesign,but for the existing board, it was more convenient to implement a Chebychev filter.
The goal was to find a compromise between the passband ripple and a steep filter transition. Thefollowing table shows the calculated and the really chosen values for a 7th order Chebychev filter with0.5 dB passband ripple up to 30 MHz and almost 60 dB attenuation at 50 MHz.
Seventh order Chebychev filter (-0.5 dB at 30 MHz; -60 dB at 50 MHz)
component ideal value real values turns
L1 334 nH 350 nH 7
L2 357 nH 375 nH 7 1/4
L3 334 nH 350 nH 7
C50 184 pF 183 pF (150//33) -
C51 280 pF 288 pF (220//68) -
C52 280 pF 288 pF (220//68) -
C53 184 pF 183 pF (150//33) -(real value means calculated, not measured!)
Simulation results with real values:
Due to the unprecise realisation with the real values, the attenuation of 0.5 dB is already reached atabout 29 MHz.
The following diagram shows the passband ripple of the Chebychev filter.
10.0M 30.0M 100.0M-75.00
-55.00
-35.00
-15.00
5.00
AC AnalysisAplac 7.62 Student version FOR NON-COMMERCIAL USE ONLY
Mag
f/HzMagdB(Vac(Outp
1.0M 3.0M 10.0M 30.0M-1.00
-0.50
0.00
0.50
1.00
AC AnalysisAplac 7.62 Student version FOR NON-COMMERCIAL USE ONLY
Mag
f/HzMagdB(Vac(Outp
miniMAX-40 LCA Pinout
Pin Description XC3020
XC3030
XC3042
Signal connector
1 DOUT-I/O DOUT J1-59
2 CCLK CCLK J1-61
3 VCC VCC J1-1
4 GND GND 63,64
5 A0--I/O NIOWR J2-32
6 A1-CS2-I/O CSLCA -
7 I/O - -
8 A2-I/O NIORD J2-31
9 A3-I/O Taster U/D (In) J1-44
10 I/O Taster L/R (In) J1-43
11 I/O Drehgeber B (In) J1-41
12 A15-I/O A15 J2-18
13 A4-I/O IO24 J1-40
14 A14-I/O A14 J2-17
15 A5-I/O IO23 J1-39
16 GND GND 63,64
17 A13-I/O A13 J2-16
18 A6-I/O SER_SPARE J1-38
19 A12-I/O A12 J2-15
20 A7-I/O SERADR (Out) J1-37
21 I/O BS0 J2-52
22 I/O SERDATA (Out) J1-36
23 A11-I/O A11 J2-14
24 A8-I/O SERCLK (Out) J1-35
25 A10-I/O A10 J2-13
26 A9-I/O -5V clock (Out) J1-33
27 VCC VCC J1-1
28 GND GND 63,64
29 VCC J1-1
30 TCLKIN-I/O CLKOUT J2-47
31 I/O IO16 J1-32
32 I/O IO13 J1-29
33 I/O IO14 J1-30
34 I/O LCD_E (Out) J1-27
35 I/O IO12 J1-28
36 I/O LCD_RS (Out) J1-25
37 I/O LCD_R/W (Out) J1-26
38 I/O LCD_DB6 (I/O) J1-23
39 I/O LCD_DB7 (I/O) J1-24
40 I/O LCD_DB4 (I/O) J1-21
41 VCC VCC J1-1
42 I/O LCD_DB5 (I/O) J1-22
43 I/O LCD_DB2 (I/O) J1-19
44 I/O LCD_DB3 (I/O) J1-20
45 I/O LCD_DB0 (I/O) J1-17
46 I/O NMRD J2-29
47 I/O NMWR J2-30
48 I/O SELECT J1-58
49 I/O LCD_DB1 (I/O) J1-18
50 I/O TOUT1 J2-48
51 I/O STDP -
52 M1- GND 63,64
53 GND GND 63,64
54 M0-RT VCC J1-1
55 VCC VCC J1-1
56 M2-I/O VCC J1-1
57 HDC-I/O IO15 J1-31
58 I/O LCD Backlight PWM (Out) J1-34
59 -I/O SSN -
60 I/O A16PS0 -
61 I/O A17PS1 -
62 I/O A18PS2 -
63 I/O A19PS3 -
64 I/O Drehgeber A (In) J1-42
65 -I/O NINIT -
66 GND GND 63,64
67 I/O HLDAK J2-46
68 I/O HLDRQ J2-45
69 I/O INTP3 J2-58
70 I/O INTP2 J2-57
71 I/O INTP1 J2-56
72 I/O DMARQ0 J2-36
73 I/O NDMAAK0 J2-37
74 I/O DMARQ1 J2-38
75 I/O NDMAAK1 J2-39
76 XTAL2-I/O D6 (Wobbel-PA) J1-45
77 GND GND 63,64
78 NRESET J1-57
79 VCC VCC J1-1
80 DONE- DONEPG J1-62
81 D7-I/O AD7 J2-10
82 BCLKIN-XTAL1-I/O
BCLKIN J1-56
83 D6-I/O AD6 J2-9
84 I/O D12 (Wobbel-PA) J1-46
85 I/O D24 (Wobbel-PA) J1-47
86 I/O ASTB J2-28
87 D5-I/O AD5 J2-8
88 -I/O A8 J2-11
89 D4-I/O AD4 J2-7
90 I/O BUFRW J2-34
91 VCC VCC J1-1
92 D3-I/O AD3 J2-6
93 -I/O A9 J2-12
94 D2-I/O AD2 J2-5
95 I/O D48 (Wobbel-PA) J1-48
96 I/O BS1 J2-53
97 I/O BS2 J2-54
98 D1-I/O AD1 J2-4
99 -/RDY-I/O NBUSY -
100 D0-DIN-I/O AD0 J2-3
Folgende Register sind im XC3030 FPGA auf dem MiniMax-40 Board definiert und an der jeweilsangegebenen I/O-Adresse vom V40HL aus ansprechbar:
0x7000 LCD Data Register
7 6 5 4 3 2 1 0
LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0
R/W R/W R/W R/W R/W R/W R/W R/W
Data to be written to or read from LCD. The direction is switched by LCD Data Direction Register.
0x7001 LCD Control Register
7 6 5 4 3 2 1 0
- - - - - E R/W RS
- - - - - W W W
LCD control signals.
0x7002 LCD Backlight
7 6 5 4 3 2 1 0
- - - - B3 B2 B1 B0
- - - - W W W W
Brightness of LCD backlight. B[3..0] = 0000: Backlight off; B[3..0] = 1111: Backlight max
0x7003 Keyboard Input
7 6 5 4 3 2 1 0
- - - - Taste U/D Taste L/R Drehgbr B Drehgbr A
- - - - R R R R
Inputs the logical levels of the keys on the front panel. An interrupt is generated when these valueschange.
0x7004 LCD Data Direction Register
7 6 5 4 3 2 1 0
- - - - - - - DIR
- - - - - - - W
DIR=0: LCD port is input; DIR=1: LCD port is output;
0x7005 Serial Output Buffer
7 6 5 4 3 2 1 0
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
W W W W W W W W
Data to be sent via serial port
0x7006 Serial Control/Status Register
7 6 5 4 3 2 1 0
TXBE - - - - - SPARE SERADR
R - - - - - R/W R/W
Data may be written to the serial output buffer, when TXBE is high. SERADR outputs the serialaddress. The receiver latches the data when SERADR changes its level. SPARE is currently unused.
0x7007 Port4
7 6 5 4 3 2 1 0
- - - - D48 D24 D12 D6
- - - - W W W W
Port4 controls the attenuation of the resistor ladder inside the PA. This ladder consists of four resistorstages with 6, 12, 24 and 48dB attenuation. The attenuation is inserted by a relay, when the respectivebit in the Port4 output register is set.
WOBBELTX
1 TCK
2 CONF_DONE
3 nCEO
4 TDO
5 VCCINT
6
7
8
9
10 GNDINT
11 CLKUSR
12
13
14
15
16 VCCINT
17 WAITB
18 BSTBB
19 RDB
20 WRB
21
22 GNDINT
23 RDYnBSY
24
25
26 INIT_DONE
27 VCCINT
28
29
30
31
32 GNDINT
33 DSPCLK
34
35
36
37 VCCINT
38
39
40
41
42 GNDINT
43
44
45
46 SERCLK
47 VCCINT
48 SERDATA
49 SERADR
50 SER_SPARE
51 GPIO11
52 GNDINT
53 GPIO10
54 Trigger out
55 Marker out
56 GPIO7
57 VCCINT
58 TMS
59 TRST
60 nSTATUS
61 GPIO6
62 GPIO5
63 GPIO4
64 GPIO3
65 GPIO2
66 GPIO1
67 GPIO0
68 DAC_D0
69 GNDINT
70 DAC_D1
71 DAC_D2
72 DAC_D3
73 DAC_D4
74 DAC_D5
75 DAC_D6
76 DAC_D7
77 VCCINT
78 DAC_D8
79 DAC_D9
80 DAC_D10
81 DAC_D11
82 DAC_D12
83 DAC_D13
84 DAC_CLK
85 GNDINT
86
87 P2
88 P3
89 VCCINT
90 IN, RESETB
91 CLK, CLK_SPX
92 IN
93 GNDINT
94
95
96 VCCINT
97
98
99
100
101
102
103
104 GNDINT
105
106 ADC_CLK
107
108 ADC_D11
109 ADC_D10
110 ADC_D9
111 ADC_D8
112 VCCINT
113 ADC_D7
114 ADC_D6
115 ADC_D5
116 ADC_D4
117 ADC_D3
118 ADC_D2
119 ADC_D1
120 ADC_D0
WOBBELTX
121 nCONFIG
122 VCCINT
123 MSEL1
124 MSEL0
125 GNDINT
126
127
128
129
130 VCCINT
131
132
133
134
135 GNDINT
136
137 AUDCLK
138 FSY
139
140 VCCINT
141
142 SCK
143 AIDATA
144
145 GNDINT
146 D0
147 D1
148 D2
149 D3
150 VCCINT
151 D4
152 D5
153 D6
154 D7
155 GNDINT
156 D8
157 D9
158 D10
159 D11
160 VCCINT
161 D12
162 D13
163 D14
164 D15
165 GNDINT
166
167
168
169
170 VCCINT
171
172
173
174
175
176 GNDINT
177 TDI
178 nCE
179 DCLK
180 DATA0
181 DATA1
182 DATA2
183 DATA3
184
185 DATA4
186 DATA5
187
188 DATA6
189 VCCINT
190 DATA7
191 SPARE3
192 SPARE2
193 SPARE1
194 AA15
195 AA14
196 AA13
197 GNDINT
198 A0
199 A1
200 A2
201 A3
202 A4
203 A5
204 A6
205 VCCINT
206 A7
207 A8
208 A9
209 DEV_CLRn
210 IN, P0
211 CLK, CLK
212 IN, P1
213 DEV_OE
214 A10
215 A11
216 GNDINT
217 A12
218 A13
219 A14
220
221
222
223
224 VCCINT
225 INTB1
226 INTB2
227 INTB3
228 INTB4
229
230
231
232 GNDINT
233
234
235
236 nRS
237
238 nWS
239 CS
240 nCS
Schematics
WOBBELTX
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: January 1, 2002 Sheet 1 of 2
Size Document Number REV
A2 DIG_TX.SCH 1
Title
Digital Transmitter
GermanyD404229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
DAC_D[13..0]
ADC_D[11..0]
DAC_CLK
ADC_CLK
A[14..0]
D[15..0]
AA[15..13]
P[3..0]
CLK_SPX
FPGA
FPGA.SCH
A[14..0]
D[15..0]
AA[15..13]
P[3..0]
CLK_SPX
RDB
WRB
WAITB
INTB[4..1]
DAC_D[13..0]
DAC_CLK
ADC_D[11..0]
ADC_CLK
SPARE[3..1]
BSTBB
DSPCLK
RESETB
TMS
TDI
TCK
TICE
TDO
12345678910
J1
CON2X5
R174K7
R184K7
R194K7
VCC33
TMS3
TDI3
1
2 3
14
U6A
74LVC32
4
5 6
14
U6B
74LVC32VCC33
DA0 25
DA1 24
DA2 23
DA3 22
DA4 19
DA5 18
DA6 17
DA7 16
DA8 15
DA9 14
DA10 13
DA11 12
DA12 9
DA13 8
D0 47
D1 46
D2 45
D3 44
D4 41
D5 40
D6 39
D7 38
D8 35
D9 34
D10 33
D11 32
D12 29
D13 28
D14 27
D15 26
X/Y 7
WAIT100
BSTB 99
MRD 98
MWR 95
HOLDAK 94 HOLDRQ 93
HA0 82
HA1 81
HWR 80HRD 79HCS 78
HWE 67HRE 66
P0 65
P1 64
P2 63
P3 62
HD0 77
HD1 76
HD2 75
HD3 74
HD4 73
HD5 72
HD6 71
HD7 70
INT1 5
INT2 4
INT3 3
INT4 2
RESET 1
SI1 48
SIEN1 49
SCK1 50
SIAK1 51
SO1 52
SORQ1 53
SOEN1 54
SI2 61
SIEN2 60
SCK2 59
SO2 58
SOEN2 57
TMS 92
TDI 91
TCK 90
TICE 89
TDO 88
CLKOUT 87
GND 10
GND 20
GND 30
GND 36
GND 42
GND 55
GND 68
GND 83
GND 96VDD 11 VDD 21 VDD 31 VDD 37VDD 43 VDD 56 VDD 69 VDD 86 VDD 97
X1 85
X2 84
U1
UPD77019
A0A1A2A3A4A5A6A7A8A9A10A11A12
VCC33
A[13..0]
8 x 10K
Set BootMode
P0P1SPARE1SPARE2SPARE3
VCC33
OE 22 CE 3
A0 24
A1 25
A2 26
A3 27
A4 28
A5 29
A6 30
A7 31
A8 32
A9 35
A10 36
A11 37
A12 38
A13 39
A14 40
A15 41
D0 21
D1 20
D2 19
D3 18
D4 17
D5 16
D6 15
D7 14
GND 12
VCC 44
D8 11
D9 10
D10 9
D11 8
D12 7
D13 6
D14 5
D15 4
GND 34
WE 43
U2
AT29LV1024J
A0A1A2A3A4A5A6A7A8A9A10A11A12
AA13AA14AA15
A13
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
TCK3 9
10 8
14
U6C
74LVC32
12
13 11
14
U6D
74LVC32
SELB_BOOT
JTAG connectorfor debugging
DSP debug
1 2
14
U7A74LVC14
A14
INTB[4..1]
RDB
WRB
WAITB
SPARE[3..1]
DSPCLK
BSTBB
RESETB
3 4
14
U7B74LVC14
11 10
14
U7E74LVC14
13 12
14
U7F74LVC14
P2
5 6
14
U7C74LVC14
9 8
14
U7D74LVC14
CLK_SPXP1CLK_SPX
TICETDO
TMS3TDI3TCK3
INTB1INTB2INTB3INTB4
RESETB
P0P1
WAITBBSTBB
DSPCLK
A14
P3P2
RDBWRB
BOOT ROM
R9
10K
SELB_BOOT
VCC33
VCC33
RDB
DSP Boot mode
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10 9
S1
RESET200ms delayCPU
PB1
VCC33
VCC 2
PFI 4 RESET 8
MR 1
RESET 7
PFO 5
GND 3
U3
MAX708T
R1133K
R20
10KR10
33K
RESETB
WAITB
VCC33
loads program from Boot ROM.
P0 and P1 select the boot mode.
VCC33
P2 indicates that DSP
C1
0.1uF
C2
0.1uF
C3
0.1uF
VCC33
VCC50
P3PIN
P4PIN
P7
PIN
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
AVDD AVDD
C9
0.1uF
C10
0.1uF
P5PIN
P6PIN
ADC_D0ADC_D1ADC_D2
D0 25
D1 26
D2 27
D3 28
D4 29
D5 30
D6 31
D7 32
D8 33
D9 42
D10 43
D11 44
AIN 7
AIN 8
ENCODE 3
ENCODE 4
VREF 9
C1 10
GND 5
GND 6
GND 13
GND 14
GND 17
GND 18
GND 21
GND 22
GND 24
GND 34
GND 35
GND 38
GND 39
AVCC 11
AVCC 12
AVCC 15
AVCC 16
AVCC 19
AVCC 20
DVCC 1
DVCC 2
DVCC 36
DVCC 37
DVCC 40
DVCC 41
U5
AD6640
T3
DL-4
R16
270
A7-X1 (AL=140nH)Doppellochkern2 x 10:10 Wdg auf
C20
0.1uF
C22
0.1uF
C23
0.1uF
C21
0.1uF
P2 must be reset to 0V bysoftware in order to indicatethat the boot sequence hasfinished.
VCC33
C49
100uFT4
VCC50
C46
0.1uF
I 3 O 2
G
1
O 4
U17LT1117CST-3.3
D3ZY5.6
C47
10uFT6.3
C48
470uF10
GND
+5V
12
CON1
Power
F1
TR5-1.25AT
Place this textclose to connectorat the respectivepin.
VCC33VCC50
R41430
R42200
C18
0.1uF
C19
0.1uF
VCC50 AVDDDR1
DR_CC_10
R13
51
5:5:10 Wdg auf
A7-X1 (AL=140nH)Doppellochkern
L1
300nH
L2
482nH
5 3/4 Wdg 6 3/4 Wdg
L1~L3 auf Doppellochkern A8-X17(AL=9nH)
C17
0.1uF
R15
100
ADC_CLK
L3
300nH
5 3/4 Wdg
T2
DL-1
ADC_D3ADC_D4ADC_D5ADC_D6ADC_D7ADC_D8ADC_D9ADC_D10ADC_D11
AVDD
VCC33
C14
0.1uF
C15
10nF
C16
10nFC53
43p
C52
174p
R14
51
Grenzfrequenz: 36 MHz
C50
43p
C51
174p
C50 und C53: je 2x22pF parallelC51 und C52: je 2x330pF in Serie
AVDD
C11
0.1uF
C12
0.1uF
C13
0.1uF
R12
2K
JP1
JPCB2NC
T1
DL-CT-1
usually not populated.Note: R13 and R14 are
DB0 14
DB1 13
DB2 12
DB3 11
DB4 10
DB5 9
DB6 8
DB7 7
DB8 6
DB9 5
DB10 4
DB11 3
DB12 2
DB13 1
IOUTA 22
IOUTB 21
COMP1 19
COMP2 23
REFIO 17
FSADJ 18
SLEEP 15
REFLO 16ACOM 20
AVDD 24
DCOM 26 DVDD 27
CLOCK 28
U4
AD9764
DAC_D0DAC_D1DAC_D2DAC_D3DAC_D4DAC_D5DAC_D6DAC_D7DAC_D8DAC_D9DAC_D10DAC_D11DAC_D12DAC_D13
DAC_CLK
1
U13M3
1
U14M3
1
U15M3
1
U16M3
5V 3.3V
D1D2
VCC50
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: January 1, 2002 Sheet 2 of 2
Size Document Number REV
A2 PILOAUD1.SCH 1
Title
PILO Audio 1
GermanyD40472 DuesseldorfOberrather Strasse 4Michael Kraemer
NEC Electronics (Europe) GmbH
VCC33
DAC_D[13..0]
ADC_D[11..0]
DAC_D0DAC_D1DAC_D2DAC_D3DAC_D4DAC_D5DAC_D6DAC_D7DAC_D8DAC_D9DAC_D10DAC_D11DAC_D12
DAC_D[13..0]
ADC_D[11..0]A0198
A1199
A2200
A3201
A4202
A5203
A6204
A7206
A8207
A9208
A10214
A11215
A12217
A13218
A14219
D0146
D1147
D2148
D3149
D4151
D5152
D6153
D7154
D8156
D9157
D10158
D11159
D12161
D13162
D14163
D15164
RDB 19
WRB 20
BSTBB 18
WAITB 17
INTB1225
INTB2226
INTB3227
INTB4228
CLK_SPX 91
DSPCLK 33
RESETB 90
CEO 3
DATA0180
DCLK179
STATUS 60
CONF_DONE 2
CONFIG121
MSEL0124
MSEL1123
CE178
CLK211
TDI 177
TCK 1
TMS 58
TDO 4
TRST 59
DAC_D0 68
DAC_D1 70
DAC_D2 71
DAC_D3 72
DAC_D4 73
DAC_D5 74
DAC_D6 75
DAC_D7 76
DAC_D8 78
DAC_D9 79
DAC_D10 80
DAC_D11 81
DAC_D12 82
DAC_D13 83
DAC_CLK 84
ADC_D0 120
ADC_D1 119
ADC_D2 118
ADC_D3 117
ADC_D4 116
ADC_D5 115
ADC_D6 114
ADC_D7 113
ADC_D8 111
ADC_D9 110
ADC_D10 109
ADC_D11 108
ADC_CLK 106
AIDATA 143
SCK 142
FSY 138
AUDCLK 137
AA13 196
AA14 195
AA15 194
P0 210
P1 212
P2 87
P3 88
SPARE1 193
SPARE2 192
SPARE3 191
GPIO0 67
GPIO1 66
GPIO2 65
GPIO3 64
GPIO4 63
GPIO5 62
GPIO6 61
GPIO7 56
GPIO8 55
GPIO9 54
GPIO10 53
GPIO11 51
GPIO12 50
GPIO13 49
GPIO14 48
GPIO15 46
U12
DIGTX10K100
A0A1A2A3A4A5A6A7A8A9A10A11A12
A[14..0]
D[15..0] D[15..0]
A[14..0]
A13A14
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14
DAC_D13
ADC_D0ADC_D1ADC_D2ADC_D3ADC_D4ADC_D5ADC_D6ADC_D7ADC_D8ADC_D9ADC_D10ADC_D11
DAC_CLK
ADC_CLK
DAC_CLK
ADC_CLK
C24
0.1uF
AA[15..13] AA[15..13]
C25
0.1uF
C26
0.1uF
C27
0.1uF
C28
0.1uF
P[3..0]
SPARE[3..1]
P[3..0]
SPARE[3..1]
VCC50
1234567891011121314151617181920
J8
CON2X10
AA13AA14AA15
P0P1P2P3
SPARE1SPARE2SPARE3
RDBWRB
RESETB RESETB
BSTBBWAITB
INTB1INTB2INTB3INTB4
D15
CLK_SPX
DSPCLKC32
0.1uF
VCC50
P2
INTB[4..1] INTB[4..1]
VCC 4
GND 2 OUT 3OE 1
U8
80.000 MHz
VCC33
DATA 31
DCLK 2
OE 7
CS 10
VCC 27
CASC 15
GND 12
VCCSEL 3
TDI 13
INITC 16VPPSEL 17
VPP 23
TMS 25TDO 28
TCK 32
U11
EPC2
VCC33
FDAT0DCLKSTATUSBDONE
JP2
R3710K
CONFIGB
TCK
TDOTMS
TDI R38
R39R40
R341K
R351K
R361K
VCC33
VCC33
AUDCLKFSYSCKAIDATA
EPC2
Cable
13579
2468
10
J7
CON2X5
VCC33
ProgrammingFLEXDownloadCable
13579
2468
10
J6
CON2X5
VCC33
TCKTDOTMS
TDI
3 x 10k
DCLKDONE
STATUSBFDAT0
CONFIGB
AINL 8
AINR 5SDATA 1
SCLK 2
MCLK 4LRCK 3VA+ 7
AGND 6
U9
CS5331A
AUDCLKFSYSCK
AVDD
AIDATA
R32150
R33150
C40
10n
C41
10n
C420.47uF
C430.47uF
J5
R29
4K7
C39100p
R30
39K
12
1314
4
11
U10D
LM837
C45
4.7uFT10
C370.1uF
C380.1uF
10
9 8
4
11
U10C
LM837
R28
68K
R3127K
R22
10k
R25
220
R26
3K9
R27
68K
5
6 7
4
11
U10B
LM837
C36100p
C44
4.7uFT10
AVDD
Mikrofon
C34
0.1uF
C35
10uFT10
R23
1K8
R24
1K2
J4
C33
0.1uF
3
2 1
4
11
U10A
LM837R21
10k
SpareAnalog in
Schematics
Wobbel-FPGA
MAX+plus II 9.3 File: TOP.GDF Date: 01/01/2002 13:52:53 Page: 1
Slow Clock(currently CLK/16)
FREQUENCY=80MHz
CLKINPUT
RESETB INPUT
SERCLKINPUT
SERADDR INPUTSERDATA INPUT
DAC_CLKOUTPUTDAC_D[13..0]OUTPUT
TriggerOUTPUTBlankOUTPUT
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
VCC
DATA[31..0]PHASE[27..0]
MARK2MARK1SWINGSFRQ
BLANKTRIGGER
TPSSPCTDELTTIME
CLKSCLKSRESETSBSRESETBMTS
phase_accu
SERCLK
SERDATASERADDR
SRESETSB MARK1MARK2
DATA[31..0]
SWINGSFRQ
CLKSAMPLITUDE
SPCTDEL
TTIME
TPS
MTS
serial-in
PHASE[27..0]SIN_N[13..0]
SIN[13..0]CLK
DPHASE[17..0]
p_to_a
NOT
XOR XOR
AND2
SIN[13..0] AMPL[13..0]SIN_N[13..0]
CLKDPHASE[17..0]
DAC_CLK
SRESETB AMPLITUDEDATA[31..0]
CLKSSRESETSB
T
TFF
Q
CLRN
PRN
AND3
GLOBAL
DATA[31..0]
CLK
AMPLITUDECLKSSRESETSB
AMPLITUDEDATA[31..0]
SRESETSBSRESETB
CLKSCLK
CLKCLKS
SRESETSBSRESETB
SRESETSB
SRESETB
CLKS
MAX+plus II 9.3 File: SERIAL-IN.GDF Date: 01/01/2002 13:53:27 Page: 1
Adr=0: Start Frequency Register
Adr=1: Swing Frequency Register
Adr=2: Marker 1 Frequency Register
Adr=3: Marker 2 Frequency Register
Rising edge on SERCLK
Adr=4: Amplitude Register
Rising edge on SERADDR
Adr=5: Time Per Sample Register
Adr=6: Samples Per Cycle Register
Falling edge on SERADDR
Adr=7: Trigger Delay Register
Adr=8: Trigger Time Register
Adr=9: Marker Time Register
shiftinsset
1
enable
q[]
LPM_SHIFTREG
SERADDR INPUT
CLKS INPUTSERCLK INPUT
SRESETSB INPUT
SERDATA INPUT
MTSOUTPUT
TTIMEOUTPUT
TDELOUTPUT
SPCOUTPUT
TPSOUTPUT
AMPLITUDEOUTPUT
MARK2OUTPUT
MARK1OUTPUT
DATA[31..0]OUTPUT SWINGOUTPUT
SFRQOUTPUT
VCC
VCC VCC VCC
VCC VCC VCC
AND2AND2
AND2AND2
AND2AND2
NOT
NO
T
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
enable
data[]
sclr1
q[]
LPM_DFF
OR2
OR2
AND6
AND6
AND6
AND6
AND6
AND6
AND6
AND6
AND6
AND6
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
SFRQ
A[1]A[0]
A[2]
A[4]RXD
A[3]
SWINGDATA[31..0]
SRESETSB
MARK1
MARK2
AMPLITUDE
TPS
RXD
SPC
TDEL
DATA[7..0]
TTIME
A[7..0]
SRESETSB
MTS
MAX+plus II 9.3 File: PHASE_ACCU.GDF Date: 01/01/2002 13:53:59 Page: 1
Time Per Sample
Marker 1Samples Per Cycle
Marker 2Trigger Delay
Start FrequencyTrigger Time
Sweep Frequency
deadtime after cycleFreq. steps per cycleTriggertime78.125 kHz
tT = n * 12.8 usn = 2 ~ 256
tD = n * 12.8 usn = 2 ~ 256
tT = 25.4 ~ 3276.8 ustD = 25.4 ~ 3276.8 us
Time per freq.-stepAll frequencies assume an 80 MHz master clock
tM = 25.4 ~ 3276.8 us
n = 2 ~ 256tM = n * 12.8 us
CLKS assumed to be CLK/16
s = 2 ~ 4096
Marker Time
SRESETSB INPUT
MTSINPUT
SRESETBINPUT
SWING INPUT
CLKS INPUT
CLKINPUT
TTIME INPUT
SFRQ INPUT
TDEL INPUT MARK2 INPUT
SPC INPUT
DATA[31..0] INPUT
MARK1 INPUT
TPS INPUT
TriggerOUTPUT
PHASE[27..0]OUTPUT
BLANKOUTPUT
datab[]
result[]
dataa[]
LPM_ADD_SUB
datab[]
result[]
dataa[]
LPM_ADD_SUB
q[]
sclr1
data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enableq[]
sclr
data[]
LPM_FF
q[]data[]
LPM_FF
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
enable
sset
q[]data[]
LPM_FF
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
result[]datab[]
sel
dataa[]0
1
BUSMUX
LDNABCDEF
DNUP
CLK
QAQBQCQDQEQF
UP/DN COUNTER
8countLDNABCDEFGHGNDNUP
CLK
QAQBQCQDQEQFQGQH
UP/DN COUNTER
8countLDNABCDEFGHGNDNUP
CLK
QAQBQCQDQEQFQGQH
COUT1
UP/DN COUNTER
8countLDNABCDEFGHGNDNUP
CLK
QAQBQCQDQEQFQGQH
UP/DN COUNTER
8countLDNABCDEFGHGNDNUP
CLK
QAQBQCQDQEQFQGQH
UP/DN COUNTER
8count
LDNABCDEFGHGNDNUP
CLK
QAQBQCQDQEQFQGQH
UP/DN COUNTER
8count
VCC
VCC
VCC
VCC VCC
VCC
VCC
VCC
OR2
OR2
OR2
OR2
OR2
OR2OR2
OR2
OR2
OR2OR2
OR2
OR2
OR2
dataa[]datab[] ageb
LPM_COMPARE
dataa[]datab[] ageb
LPM_COMPARE
AND2AND2
AND2
AND2
AND2
OR3
OR3 OR3
OR8 OR8 OR8
OR4
OR6
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
QA
LDN
BA
QDQCQB
DNUPCIN
1
DC
CLK
4count
COUNTER
OR12
NOR8
NOR2
VTPS[7..0]DATA[7..0]
DATA[27..0]
MARK1
DATA[31..0]
VSPC[11..0]DATA[11..0]
MT[2]MT[1]MT[0]
MT[6]MT[5]MT[4]MT[3]
MT[7]
CLKTM
MARK2
DATA[27..0]
VTDEL[7..0]DATA[7..0]
CLKS
ACTIVEDATA[27..0]VTTIME[7..0]DATA[7..0]
SFRQ
SFREQ[27..0]
SUM[27..0]
DATA[27..0]
PHASE[27..0]RESULT[27..0]
ACTIVE
CLKSDIV
STTIMEDTIMEACTIVE
CLKTM
CLKSDIV
VTTIME[1]VTTIME[0]
VTDEL[1]VTDEL[0]
VSPC[1]VSPC[0]
VTPS[1]VTPS[0]
VTTIME[5]VTTIME[4]VTTIME[3]VTTIME[2]
VTDEL[5]VTDEL[4]VTDEL[3]VTDEL[2]
VSPC[5]VSPC[4]VSPC[3]VSPC[2]
VTPS[5]VTPS[4]VTPS[3]VTPS[2]
VTTIME[7]VTTIME[6]
VTDEL[7]VTDEL[6]
VSPC[7]VSPC[6]
VTPS[7]VTPS[6]
CLKSDIVCLKSDIVCLKTM
CLKS
VSPC[9]VSPC[8]
VSPC[11]VSPC[10]
DATA[7..0]MT[7..0]
MAX+plus II 9.3 File: P_TO_A.GDF Date: 01/01/2002 13:54:33 Page: 1
Previous phase
Previous phase + 1
Delayed Phase (sync. to SIN)
address[]inclockoutclock
q[]
LPM_ROM
address[]inclockoutclock
q[]
LPM_ROM
result[](cvalue)
LPM_CONSTANT
result[](cvalue)
LPM_CONSTANT
result[](cvalue)
LPM_CONSTANT
result[](cvalue)
LPM_CONSTANT
result[](cvalue)
LPM_CONSTANT
result[](cvalue)
LPM_CONSTANT
result[](cvalue)
LPM_CONSTANT
data[]q[]
LPM_DFF
data[]q[]
LPM_DFF
data[]q[]
LPM_DFF
data[]q[]
LPM_DFFdata[]q[]
LPM_DFF
data[]q[]
LPM_DFF
CLK INPUT
PHASE[27..0] INPUT
datab[]
result[]
dataa[]
LPM_ADD_SUB
datab[]
result[]
dataa[]
LPM_ADD_SUB
datab[]
result[]
dataa[]
LPM_ADD_SUB
datab[]
result[]
dataa[]
LPM_ADD_SUB
datab[]
result[]
dataa[]
LPM_ADD_SUB
WIRE
WIRE
WIRE
WIRE
result[]datab[]
sel1
dataa[]0
1
BUSMUX
result[]datab[]
sel
dataa[]0
1
BUSMUXresult[]
datab[]
sel
dataa[]0
1
BUSMUX
result[]datab[]
sel1
dataa[]0
1
BUSMUX
result[]datab[]
sel
dataa[]0
1
BUSMUXresult[]
datab[]
sel
dataa[]0
1
BUSMUX
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
D
DFF
CLRN
QPRN
VCC
VCC
VCC
VCC
GND
GND
NOR8
NOR8
NAND2
NAND2
SIN_N[13..0]OUTPUT
DPHASE[17..0]OUTPUT
SIN[13..0]OUTPUT
HW13
SIN[13..0]
HW[13..0]
CLK
R13
R13,HW[12..0]ROM[12..0]
IP[7..0]
HWN13
SIN_N[13..0]
HWN[13..0]
CLK
RN13
RN13,HWN[12..0]ROMN[12..0]
IPN[7..0]
PHASE[27..18]
PHASE[27..0]CLK
PPHASEI[27..18]
PPHASE[27..0]
PPHASEI[25..18]
CLK
PHASE[27..0]
PPHASE[25..18]
PPHASE25PPHASE24PPHASE23PPHASE22
CLKPPHASE21PPHASE20PPHASE19PPHASE18
PPHASE26
CLK
PPHASEI25PPHASEI24
PPHASEI26
PPHASEI23PPHASEI22PPHASEI21PPHASE20PPHASEI19PPHASEI18
CLK
CLK
CLK
CLK
CLK
CLKPPHASE27
CLK
CLKPPHASEI27
PPHASE[17..0]
CLK
HWN[12..0]CLK
HW[12..0]CLK
MAX+plus II 9.3 File: OUTPUT_STAGE.GDF Date: 01/01/2002 13:55:06 Page: 1
carry propagation
interpolated sine
always positive
for a 14-bit wide and 1024 word sineSIN_N-SIN does never exceed 6 bits plus sign
NOT
NOT
clockdataa[]
datab[]
result[]
LPM_MULT
clockdataa[]
datab[]
result[]
LPM_MULT
data[]
sclr1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
data[]
1
q[]
LPM_DFF
CLKINPUT
CLKSINPUT
AMPLITUDEINPUT
SRESETSB INPUT
SIN_N[13..0] INPUT
SIN[13..0] INPUT
DPHASE[17..0]INPUT
DATA[31..0] INPUT
SRESETBINPUT
DAC_CLKOUTPUT
AMPL[13..0]OUTPUT
datab[]
result[]
dataa[]clock
LPM_ADD_SUB
datab[]
result[]
dataa[]
LPM_ADD_SUB
WIRE
WIRE
GND
VCC
enable
sset
q[]data[]
LPM_FF
OR2
CLKDELTA[12..6]
CLK
DA[6..0]
ISIN[13..0]
DA6,DA6,DA6,DA6,DA6,DA6,DA6,DA[6..0]
RES[23..10]RES[23..0]
ISIN[13..0]
DEX[6..0]DSIN[6..0]
DELTA[13..0]
LOW,O_DP[5..0]
DPHASE[17..12]O_DP[5..0]
CLK
SIN[13..0]
DSIN[13..0]
SIN_N[13..0]
SIN[13..0]
CLK
HIGH
LOW
SRESETSB
DATA[9..0]
CLKS
CLK
Schematics
MiniMAX-FPGA
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: November 29, 1999 Sheet 1 of 7
Size Document Number REV
A3 1
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
U1
IBUF
U2
IBUF
U3
IBUF
U43
P88
A8
U44
P93
A9
A8
A9
U87
OPADP99NBUSY
U85
OBUF
U86VCC
NBUSY
A[0..15]
NIORD
NIOWR
DI[0..7]
DO[0..7]
DECODER
DECODER.SCH
DI[0..7]
DO[0..7]
NDE
SELECT
NIORD
NIOWR
BS[0..2]
CPUCLK
A[0..15]
NOD
U22
OBUFZ
U23INLAT
DO4
DI4
DO0
DI0
U30
P89,FASTAD4
U10
OBUFZ
U11INLAT
U26
P100,FASTAD0
U12
OBUFZ
U13INLAT
U27
P98,FASTAD1 DO1
A0
U31
P87,FASTAD5
U24
OBUFZ
U25INLAT
DO5
A4
NDE
BS[0..2]
CPUCLK
U73
IPADXCLK
A10
A11
A12
U69
IBUF
U4
IBUF
U5
IBUF
U45
P25
A10
U46
P23
A11
U47
P19
A12
U6
IBUF
U7
IBUF
U8
IBUF
U48
P17
A13
U49
P14
A14
U50
P12
A15
A13
A14
U70
IBUF
U71
IPADSTDP
U65
GCLK
U84
INV
U66
IPADCPUCLK
U20
OBUFZ
DI5
A5
DI1
A1
U32
P83,FASTAD6
U14
OBUFZ
U28
P94,FASTAD2
U15INLAT
U16
OBUFZ
DO2
DI2
A2
U18
OBUFZ
U21INLAT
DO6
DI6
A6
Detect HALT modeThis logic will keep
NIOWR
A15
NIORD
U67
ACLK
U51
IBUF
U52
IBUF
U53
P8NIORDU54
P5NIOWR
U57
P21BS0
ASTB
BS0
U59
INLAT
U60
INLAT
U72
AND3B1
Q
C
D
U81
FD
CE of the Flash EEPROMhigh during HALT modein order to reduce thepower consumption.
U19INLAT
DO7
DI7
A7
DO3
DI3
A3
U33
P81,FASTAD7
U17INLAT
U29
P92,FASTAD3
U35INLAT
U39
P60
A16 A16
PS0
U41
P62
A18
U37INLAT
A18
PS2
U77
NAND2B2U78
OR2
IDLE
U79
AND2
HALT
BS1
U61
INLAT
U75
AND3U56
P97BS2
U58
P96BS1
NINITU64
OPADP65NINIT
BS2
U62
OBUF
U63VCCQ
C
D
U76
FD
U82OR2
U80
AND2
U38INLAT
A19
PS3
A17
PS1
U42
P63
A19
F1C
U36INLAT
U40
P61
A17
U9
IBUF
U34
P86ASTB ASTB
U74
P48,FASTSELECT
U55
OBUFZ
SELECT
U68
AND2B1
U83
AND2B1
|PARTTYPE=3030PQ100-70
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: December 31, 2001 Sheet 2 of 7
Size Document Number REV
A3 DECODER.SCH 1
Title
Decoder
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
DO[0..7]DO[0..7]
CPUCLK
Port0
PORT0.SCH
DI[0..7]
NIORD
NIOWR DO[0..7]
SELPORT0
SELDDR0 CPUCLKU96
AND4B3
x=0
U91
NAND2B1
DI[0..7]
A[0..19]
NIORD
NIOWR
DI[0..7]
NIOWR
NIORD
A[0..19]
BS0
BS1
U89
XNOR2
U90
NOR2
I/O access
700x
U94
AND5B2
A4
A5
NDE
U97
AND4B2
A0
A1
A2
A0
A1
A2
x=1
Port1
PORT1.SCH
DI[0..7]
NIOWR
SELPORT1
Port2
PORT2.SCH
CPUCLKNIOWR
DI[0..7]
SELP21
SELP22
SELP23
NIORD
DO[0..7]
CLK_DBx=5U107
AND4B1
A0
x=6U108
AND4B1A0
A1
A2
BS2
A8
A9
A10
A6
A7 U95
AND5B5
A11
A12
A13
A14
A15 U105
AND5B2
U98
AND4B2
U99
AND4B1
A0
A1
A2
x=2
A1
A2
Port3
PORT3.SCH
NIORD
SELPORT3
DO[0..7]
CPUCLK
CLK_DB
Port4
PORT4.SCH
DI[0..7]
NIOWR
SELPORT4
U100
AND4B2
A0
A1
A2
A1
A2
x=3
x=4
U103
INVSELECT A0
D
C
CE
Q
U101
FDC
DI0
U251
AND4
A0
A1
A2
x=7
U92OBUFT
U93IBUF
SSNOU88
OPADP59SSN
DO0
SSNI
XU1TBUF
NIOWR
U102
NAND2B1
NIORD
A0
A1
A2
U104
AND4
D
C
CE
Q
U106
FDC
DI1 NODNOD
XU2
TBUF
DO1
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: December 19, 1999 Sheet 3 of 7
Size Document Number REV
A3 PORT0.SCH 1
Title
Port 0
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
DO[0..7]DO[0..7]
PO00XU3
TB00
D0D1D2D3D4D5D6D7
C
Q0Q1Q2Q3Q4Q5Q6Q7
CE
U109
RD8C
DI0
DI[0..7] DI[0..7]
NIOWR NIOWR
DI1DI2DI3DI4DI5DI6DI7
PO01PO02PO03PO04PO05PO06PO07
PI00
PI01
PI02
XU4
TB01
XU5
TB02
DO0
DO1
DO2
U112
INLAT
DDIR
PO00
U135
INVU111OBUFZ
DDIR
U127
Q00
U119OBUFZ
U120
INLAT
PO04
U142
INV U132
Q04
CPUCLK
U131
Q05
PI04
U121OBUFZ
U122
INLAT
PO05
U141
INVU113OBUFZ
DDIR
U128
Q01
PI00
U114
INLAT
DDIR
PO01
U136
INV
DO3
DO4
DDIR
PI03
PI04
XU6
TB03
XU7
TB04
XU8
TB05
DI0
U110
NAND2B1
D
C
CE
Q
U143
FDC
NIORD NIORD
SELPORT0
SELDDR0
PI05
PI06 XU9
TB06
XU10
TB07
DO5
DO6
PI01
DDIRU137
INVU115OBUFZ
DDIR
PI05
U123OBUFZ
U140
INV U130
Q06
U124
INLAT
PO06
PI06
U129
Q02
U116
INLAT
PO02
PI02
DO7PI07
U118
INLAT
DDIR
PO03
U138
INVU117OBUFZ
DDIR
U134
Q03
U125OBUFZ
U126
INLAT
PO07
U139
INV U133
Q07
PI07PI03
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: December 19, 1999 Sheet 4 of 7
Size Document Number REV
A3 PORT1.SCH 1
Title
Port 1 (Output Port)
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
U145
OBUF
U146
OPAD,SLOW
Q10PO10
DI[0..7] DI[0..7]
NIOWR NIOWR
D0D1D2D3D4D5D6D7
C
Q0Q1Q2Q3Q4Q5Q6Q7
CE
U144
RD8C
DI0DI1DI2DI3DI4DI5DI6DI7
PO10PO11PO12 PO11
PO12
U147
OBUF
U148
OBUF
U153
OPAD,SLOW
Q11
U154
OPAD,SLOW
Q12
U149
OBUF
U150
OBUF
U155
OPAD,SLOW
Q13
U156
OPAD,SLOW
Q14
SELPORT1
U151
OBUF
U152
OBUF
U157
OPAD,SLOW
Q15
U158
OPAD,SLOW
Q16
U159GND
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: March 18, 2000 Sheet 5 of 7
Size Document Number REV
A3 PORT2.SCH 1
Title
Port 2 (SIO, LCD Backlight/neg.V)
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
U199
,SLOWQ22
U200
,SLOWQ23
U196
OBUF
U197
OBUF
SERCLK
S
C
R
Q
U204
FRS
SERCLKCLK32
CLK16
CLK8
CLK4
CLK2
U206
AND5B4
D0D1D2D3D4D5D6D7
C
Q0Q1Q2Q3Q4Q5Q6Q7
CE
U176
RD8C
SERADRSPARE
BACK0BACK1BACK2BACK3
DI0DI1DI2DI3DI4DI5DI6
D0D1D2D3D4D5D6D7
C
Q0Q1Q2Q3Q4Q5Q6Q7
CE
U168
RD8C
DI0DI1DI2DI3DI4DI5DI6
DI[0..7] DI[0..7]
NIOWR NIOWR
SELP21
SELP23 SELP23
DI7
D0D1D2D3D4D5D6D7
C
Q0Q1Q2Q3Q4Q5Q6Q7
CE
U169
RD8C
DI0DI1
DI7
SLID0D1D2D3D4D5D6D7SRILLEFT
CECR
Q0Q1Q2Q3Q4Q5Q6Q7
U180
SR8RLED
U160
INLAT
CPUCLK
CPUCLKU205
AND2
CNT0
TX
CPUCLK
XR3PULLUP
U195
OBUF
SERDATA
SERADR
U198
OBUF
U201
,SLOWQ24
U202
,SLOWQ25SPARE
DO[0..7] DO[0..7]
XU11
TB20
U161
Q26
U162
Q27
U207
NAND2B1
U175
OBUF
SERDATA
CPUCLKCESR
DI2DI3DI4DI5DI6DI7
U179
AND2B1
SELP22
U188
AND2B1
NIOWR
Q
C
D
U189
FD
Q
C
D
U178
FD
U177GND
S
C
R
Q
U190
FRS
U191
OR2
U194
INV
TXBE
NIORD NIORD
SELP23
TX XU12
TB21
XU13
TB22
SERADR
SPARE
DO0
DO1
DO2
DO3XU14
TB23
XU15
TB24
U212
OR2
S
C
R
Q
U193
FRS
CPUCLKU183
OR2
CESR
START_TX
U186
AND5B5
U192
AND2CLK8CLK4CLK2
CLK2
CECR
Q0Q1Q2Q3Q4Q5Q6Q7
CEOTC
U163
CB8RE
CPUCLK
U164VCC
CPUCLK
CECR
Q0Q1Q2Q3Q4Q5Q6Q7
CEOTC
U170
CB8RE
BACK0BACK1
CLK32CLK16
CLK32
CLK16
CLK8
CLK4CLK64CLK128CLK256
CNT0
A0A1A2A3
B0B1B2B3
EQ
U209
COMP4
CLK2
U182
AND5
U203
AND2B1 U185OR2
U210
AND3B1
START_TX
XU16
TB25
XU17
TB26
DO4
DO5
DO6
DO7TXBE XU18
TB27
U211
AND3
Q0
Q1
Q2
TC
CE
R
C
U181
C8BCR
CPUCLK
U184GND
CLK32
CLK16
CLK8
CLK4BACK2BACK3
U165GND
U171
FDRSE
CLK_DB
U172
INV
U173
OBUF
U174
,FASTQ21
U166
OBUF
CLK256U167
Q20
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: December 31, 2001 Sheet 6 of 7
Size Document Number REV
A3 PORT3.SCH 1
Title
Port 3 (Input Port)
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
CPUCLK
XR4PULLUP
U221
Q30
CPUCLK
U214
INLAT
PI30
U228VCC
DO[0..7]DO[0..7]
XU19
TB30
NIORD NIORD
SELPORT3
U213
NAND2B1
XU20
TB31
XU21
TB32
PI230
PI231
PI232
DO0
DO1
DO2
PI30PI31PI32PI33
CLK_DB CLK_DB
PI130PI131
D0D1D2D3
C
Q0Q1Q2Q3
CE
U243
RD4C
PI132PI133
PI230PI231
D0D1D2D3
C
Q0Q1Q2Q3
CE
U244
RD4C
PI232PI233
U215
INLAT
U216
INLAT
PI31
XR5PULLUP
U222
Q31
XR6PULLUP
XR7PULLUP
U223
Q32
U217
INLAT
PI32DO3
DO4
XU22
TB33
XU23
TB34
XU24
TB35
PI233
XU25
TB36
XU26
TB37
DO5
DO6
PI33U224
Q33
U237
P71,FASTINTP1
CPUCLK
U235
FDRS
U236
OBUF
Q
C
D
U238
FD
U239
AND2B1
CPUCLK
DO7
U240
INVU252GND
PI30
PI130
PI230
U229
AND3B2
U230
AND3B1
U233
OR4
PI32
PI132
PI232
U245
AND3B2
U246
AND3B1
U249
OR4
U250
OR2
Q
C
D
U234
FD
CLK_DB
U247
AND3B2
U248
AND3B1
PI133
PI233
PI33PI31
PI131
PI231
U231
AND3B2
U232
AND3B1
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: December 31, 2001 Sheet 7 of 7
Size Document Number REV
A3 PORT4.SCH 1
Title
Port 4 (Output Port)
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
U145
OBUF
U146
OPAD,SLOW
Q34D6
DI[0..7] DI[0..7]
NIOWR NIOWR
D0D1D2D3D4D5D6D7
C
Q0Q1Q2Q3Q4Q5Q6Q7
CE
U144
RD8C
DI0DI1DI2DI3DI4DI5DI6DI7
D48
D6D12D24 D12
D24
U147
OBUF
U148
OBUF
U154
OPAD,SLOW
Q36
U153
OPAD,SLOW
Q35
U149
OBUF
U155
OPAD,SLOW
Q37D48
SELPORT4
Schematics
WOBBEL-PA
8 7 6 5 4 3 2 1
A
B
C
D
12345678
D
C
B
A
Date: May 14, 2000 Sheet 1 of 1
Size Document Number REV
A3 WOBBELPA.SCH 1
Title
Endstufe fuer Wobbelsender
GermanyD40229 DuesseldorfEdenkobener Weg 24Michael Kraemer
Michael Kraemer
5 9 4 8 3 7 2 6 1
P7
DSUB9HF
I1 1
I2 2
I3 3
I4 4
I5 5
I6 6
I7 7
I8 8
GND 9
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
Q8 11
COM 10
U2
ULN2803
VCC
VCC
101
9 873 2 4
U7RELAY-TQ2SA-5V
101
9 873 2 4
U6RELAY-TQ2SA-5V
101
9 873 2 4
U5RELAY-TQ2SA-5V
101
9 873 2 4
U4RELAY-TQ2SA-5V
C9
0.1uF
P1
C80.1uF
R3820
3
26
7
4U3
AD811AN
VCC12ML1
FP5
R251
R1751
P3
P4
R5150
R6150
R7
39
R882
R982
R10
91
R1156
R1256
R13
390
R1551
R14
6K2
R1651
P5
P6
-48dB-24dB-12dB-6dBVCC12PL2
FP5
C70.1uF
R1
51
R4
200
P2
C410uFT6.3
VCC 1
GND 2
+V 6
0V 5
-V 4
U1
NMA0512S
C10.1uF
VCC C20.1uF
C54.7uFT16
VCC12P
VCC12M
C30.1uF
C64.7uFT16
DC/DC Converter
1
U8M3
1
U9M3
1
U10M3
1
U11M3