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Transcript of Supertex inc. - Microchip Technologyww1.microchip.com/downloads/en/DeviceDoc/HV7355DB1...TP26 TP3...
Supertex inc.
Supertex inc. www.supertex.com
HV7355DB1
Doc.# DSDB-HV7355DB1B070314
General DescriptionThe HV7355 is a monolithic eight-channel, high-speed, high voltage, unipolar ultrasound transmitter pulser. This integrated, high performance circuit is in a single, 8x8x0.9mm, 56-lead QFN package.
The HV7355 can deliver guaranteed ±1.5A source and sink current to a capacitive transducer with 0 to +150V peak voltage. It is designed for medical ultrasound imaging and ultrasound material NDT applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for ATE systems and pulse signal generators as a signal source.
The HV7355’s circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents typically over ±1.5A for pulsing, with up to 150V swings. The upper limit frequency of the pulser waveform is dependent upon the load capacitance. With different capacitance load conditions the maximum output frequency is about 20MHz.
This demoboard datasheet describes how to use the HV7355DB1 to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser.
The HV7355 circuit uses DC-coupling from a 3.3V logic input to output TX0~7 internally, therefore the chip needs three sets of voltage supply rails: VLL (+3.3V), VDD/VSS (+/-5.0V) and VPP (up to +150V). The VPP high voltage supply can be changed rather quickly, compared to the capacitor gate-coupled driving pulsers. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier.
The control signal logic-high voltage should be the same as the VLL voltage of the IC, and the logic-low should be referenced to GND.
The HV7355DB1 output waveforms can be displayed using an oscilloscope by connecting the scope probe to the test points TX0~7 and GND. The soldering jumper can select whether or not to connect the on-board dummy load, a 330pF capacitor paralleling with a 2.5kΩ resistor. The test points can be used to connect the user’s transducer to easily evaluate the pulser.
Block Diagram
150V, 1.5A, Unipolar Ultrasound Pulser Demoboard
LTIN0
IN7
VLL
GND
MC
VSS
VSS
+5.0 to 150V+3.3V
CPF VPPVDDVPF
CWD
Q[7:0]
LT
LT
LT
-5.0V
D0SDI
Q7SDO
SCK
SETLE
CS
ENPWR
RGND
RGND
RGND
SUB
Q7
Q0
AVDD
VSUB
TX0
R32.5k
C4330pF
GND
DummyLoad
R2WaveformGenerator
CPLD
+3.3V
OSC
JTAG
EXCLK
EN
CLKIN
WAVEFREQ
SELEN
CW/RTZ
CWLRRTZPWREN
40MHz
6
TX7
LR
DataLatch
ShiftRegister
VDD
VDD VPP
VDD
VDD
VDDVDD
VPF
VPF
VPP
TX7
VPP
+5.0V
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
The PCB Layout TechniquesThe large thermal pad at the bottom of the HV7355 package is internally connected to the IC’s substrate (VSUB). This thermal pad should be connected to 0V or GND externally on the PCB. The designer needs to pay attention to the con-necting traces on the outputs TX0~7, as the high-voltage and high-speed traces. In particular, controlled-impedance to the ground plane and more trace spacing needs to be ap-plied in this situation.
High-speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds are used for the demo board PCB layout. The internal circuitry of the HV7355 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driv-ing capacitive loads, the supply voltage bypass capacitors and the driver to the FET’s gate-coupling capacitors should be as close to the pins as possible. The GND pin should have low inductance feed-through via connections that are connected directly to a solid ground plane. The VDD, VSS, VPP and CPP voltage-supply and/or bypass capacitor pins can draw fast transient currents of up to 2.0A, so they should be provided with a low-impedance bypass capacitor at the chip's pins. A ceramic capacitor of 1.0 to 2.0µF may be used. Only VPP to GND capacitors need be high voltage. CPF to VPP capacitors only need be low voltage. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise when using multiple HV7355 ICs, insert another ferrite bead between each chips supply line.
Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the out-put impedance of the HV7355’s high voltage power stages is very low, to obtain better waveform integrity at the load terminals after long cables, in some cases it may be desir-able to add a small value resistor in series with the outputs TX0~7. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal termi-nals of the HV7355.
This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 3.3V, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return cur-rent from a capacitive load cannot react with common induc-tance to create noise voltages in the input logic circuitry.
Testing the Integrated PulserThe HV7355 pulser demoboard should be powered up with a DC power supplie that has current limiting functions.
To meet the typical loading conditions, the on-board dummy load 330pF//2.5kΩ should be connected to the high voltage pulser output through the solder jumper when using an oscil-loscope’s high impedance probe. To evaluate different load-ing conditions, the values of the RC within the current and power limit of the device may be changed. In order to drive the user’s piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 70 to 75Ω coaxial cable is recommended. The coaxial cable end should be sol-dered to TX0~7 and GND directly with very short leads. If a user’s load is being used, the on-board dummy load should be disconnected by cutting the small shorting copper trace in between the zeroΩ resistor’s (R2, R12 etc.) pads. They are shorted by factory default.
All of the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that VPP voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is impor-tant to have short ground leads to the circuit board ground plane.
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
HV7355DB1 Schematic
6
24
11
11
2
33 4
6
VZ2
VZ5
EN
VZ8
VZ4
VZ3
VZ9
VZ6
VZ7
LE MC
SE
T
CS
SD
IS
CK
VP
PV
CC
VD
D
VP
P
VS
S
VP
P
VD
D
VC
C
VC
C
VS
SV
CC
VD
D
VC
C
VC
C =
+3.
3VV
DD/V
SS =
+/-5
.0V
VP
P =
+5.
0 to
+15
0V
J2E
XC
LKEX
=0
D7 R
ED
TP37
TP34
C9
1µF
160V
TP11
BAT54DW-7
BAT54DW-7D
22B
TP26
TP3
TP14
EN
1
GN
D2
OU
T3
VC
C4
40M
Hz
X1
EN
56
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
MC
LE SE
TC
SS
CK
SD
I
SD
O
TX0
TX0
TX1
TX1
TX2
TX2
TX3
TX3
TX4
TX4
TX5
TX5
TX6
TX6
TX7
TX7
VLL
AVDD
VDD
VDD
CPF
CPFVPPVPPVPPVPPVPPVPPVPPVPP
GND
GND
VSS
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
JX9577
TP9
TP31
TP17
R14
1.0k
D4 Y
LW
TP12
JTA
G J
3
TP40
C31
0.22
TP1
R9
1.0k
TP18
SW2
TP4
TP21
D6 G
RN
41725
23567
109
2411
SET
LE
MC
CS
EN
VCC
VCC
VCC
32
31
30
29
28
35
26
15
SD
O39
SC
K40
CLK
43
38 37 22 21 19 18 14 13
W4
ZE;794ZNaXS66
TP13
13
TP36
D22
A
TP38
B1100-13
D17
TP2
R34
2.55
k1W
TP39
TP10
C22
0.22
C37
330p
F25
0V
12
J1
R17
50
R21
50
R22
50
R23
50
R36
50
R39
50
R45
50
R46
50
R4
1.0k
BAT54DW-7
D20
B
D3 R
ED
TP6
R2 0
TP24
TP7
R25
33k
TP15
TP23
BAT54DW-7
D20
A
D5 Y
LW
R15
50
TP30
D15
B1100-13
R20
50
TP32
TP33
R47
50
R48
50
R49
50
R50
50
R51
50
R32
2.55
k1WR
542.
55k
1WR11
2.55
k1WR
242.
55k
1WR19
2.55
k1WR
132.
55k
1WR3
2.55
k1W
R12 0 R18 0 R23 0 R10 0 R37 0 R52 0 R53 0
C23
330p
F25
0VC24
330p
F25
0VC7
330p
F25
0VC29
330p
F25
0VC21
330p
F25
0VC20
330p
F25
0VC4
330p
F25
0V
C27
1µF
160V
C6
1µF
160V
C28
1µF
160V
C8
1µF
C5
1µF
C14
1µC
121µ
C13
1µ
C19
0.22
TP8
TP5
C1
022
C2
022
C3
022
VC
C
R5
1.0k
R6
1.0k
R7
1.0k
R8
1.0k
C18
0.22
VC
C
2
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
TP16
TP20
TP19
TP22
TP25
TP27
TP6
TP28
TP29
C36 1µ
R20 50
VC
CV
DD
VS
SV
PP
MH
3M
H2
MH
1
12
34
56
12
34
56
HE
AD
ER
6 J
4
MH
4
R35
1.0
R38
1.0
R31 1.0
R30 1.0
C32
0.22
C33
0.22
C34
0.22
C35
0.22
SW1
SW3
SW4
SW5
R26
33k
R27
33k
R28
33k
R29
33k
R40
200
R41
200
R42
200
R43
200
R45
200
VC
C
C30
0.22
GNDGNDGND
WAVFRESELENAMOD
TMSTDITDOTCK
57
54
17
44
25
46
47
26
27
24
45
42 43 41 40 39 38 37 36 35 34 33 32 31 30 29 28
1 2 3 4 5 6 7 8 15 11 14 9 12 10 13
MC LE
SE
TC
SS
CK
SD
I
16
55
23
48
53
184921205251501922
TP35
VD
D
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
HV7355DB1 PCB and Board Layout
Actual Board Size: 72.4mm x 68.4mm
Power Connector Description1 VCC +3.3V Logic voltage input for VLL and CPLD. (100mA)
2 GND 0V, Ground
3 VDD +5.0V HV7355 positive VDD supply. (25mA)
4 VSS -5.0V HV7355 negative VSS supply. (-25mA)
5 GND 0V, Ground
6 VPP +10 to +150V positive high voltage supply. (5mA)
Voltage Supply Power-Up and Operation Sequence1 +VCC +3.3V positive logic supply voltage for HV7355’s VLL and CPLD VCC.
2 +VDD / -VSS ±5.0V positive and negative VDD and VSS power supply.
3 +VPP +10 to +150V positive high voltage.Note:
Power-down in reverse order
Push Button OperationsWAV Toggle select pulse B-mode waveforms: None, 1-cycle, 3-cycles, 7-cycles.
FREQ Toggle select frequency: 20, 10, 5, 2.5, 1.25 and 0.625MHz when X1 oscillator is 40MHz.
SEL Toggle select. Increases the off-time between 2 consecutive pulses.
EN Toggle ON or OFF HV7355 chip enable
MODE Toggle select between B-mode and CW.
LED IndicatorSET Set the latch registers of serial interface, when high, all latches are set to logic high.
LE Latch enable when low, data can be latched into the registers of serial interface.
MC Mode control, high indicates B-mode and low indicates CW.
PWR HV7355 VLL 3.3V and CPLD chip VCC power supply indicator.
EN HV7355 chip enable signal indicator. Power state initially is OFF until EN is pushed.
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
Typical Waveforms
Figure 1. Input logic and TX output waveforms of 5.0MHz (0 to +150V with 330pF//2.5kΩ load)
Figure 2. Rise and fall time at 0 to +150V (with 330pF//2.5kΩ load)
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
Typical Waveforms (cont.)
Figure 3. Multiple channel at 5.0MHz (0 to +150V with 330pF//2.5kΩ load)
Figure 4. FFT Plot of Second Harmonic Distortion (HD2) -36dB at 5.0MHz, VPP = 150V (with 330pF//2.5kΩ load)
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
Typical Waveforms (cont.)
Figure 5. Output Waveform at 10MHz and VPP = 120V (with 330pF//2.5kΩ load)
Figure 6. Output Waveform at 2.5MHz and VPP = 120V (with 330pF//2.5kΩ load)
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HV7355DB1
Supertex inc. www.supertex.com
Doc.# DSDB-HV7355DB1B070314
Typical Waveforms (cont.)
Figure 7. Output Waveform at 20MHz at VPP = 75V (with 330pF//2.5kΩ load)
Figure 8. Power on EN chip enable to VPF setting time
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receivesan adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilityto the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry andspecifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888www.supertex.com9
HV7355DB1
Doc.# DSDB-HV7355DB1B070314
Bill of MaterialsComponent Description Manufacturer Part Number
C1 - C3, C18, C19, C22, C30 - C35 CAP CER 0.22µF 16V X7R 10% 0603 TDK C1608X7R1C224K
C4, C7, C20 - C24, C29, C37 CAP CER 330pF 200V X7R 0603 Panasonic ECJ-1VB2D331K
C5, C8, C12, C13, C14, C36 CAP CER 1.0µF 16V X7R 0603 TDK C1608X7R1C105M
C6, C9, C27, C28 CAP CER 1µF 100V X7R 20% 1210 TDK C3225X7R2A105M
D3, D7 LED THIN 635NM RED DIFF 0805 SMD Lumex SML-LXT0805IW-TR
D4, D5 LED THIN 585NM YEL DIFF 0805 SMD Lumex SML-LXT0805YW-TR
D6 LED THIN 565NM GRN DIFF 0805 SMD Lumex SML-LXT0805GW-TR
D15, D17 DIODE SCHOTTKY 100V 1A SMA Diodes Inc. B1100-13
D20, D22 DIODE SCHOTTKY DUAL 30V SOT-363 Diodes Inc. BAT54DW-7
J1 CONN HEADER 2POS .100 VERT GOLD Molex 22-28-4023
J2 CONN JACK END LAUNCH PCB GOLD SMA Johnson 142-0711-821
J3 CONN HEADER 6POS .100 VERT GOLD Molex 22-28-4063
J4 CONN HEADER 10POS .100 VERT GOLD Tyco 1-640454-0
R2, R10, R12, R18, R23, R37, R52, R53 Solder Gap (SHORT) NA NA
R3, R11, R13, R19, R24, R32, R34, R54 RES 2.55kΩ 1W 1% 2512 SMD Panasonic ERJ-1TNF2551U
R4, R5, R6, R7, R8, R9, R14 RES 1.00kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF1001V
R15 - R17, R20 - R22, R33, R36, R39,
R45 - R51RES 49.9Ω 1/16W 1% 0603 SMD Panasonic ERJ-3EKF49R9V
R25, R26, R27, R28, R29 RES 33.2kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF3322V
R30, R31, R35, R38 RES 1.00Ω 1/10W 1% 0603 SMD Rohm MCR03EZPFL1R00
R40, R41, R42, R43, R44 RES 200Ω 1/16W 1% 0603 SMD Panasonic ERJ-3EKF2000V
SW1, SW2, SW3, SW4, SW5 SWITCH LT 4.7MMX3.5MM 100GF SMD Panasonic EVQ-P2002M
TP3, TP15 TEST POINT PC MULTI PURPOSE BLK Keystone 5011
U2 IC CPLD 72 MCELL C-TEMP 44-VQFP Xilinx XC9572XL-5VQ44C
U3 IC HV7355K6-G 4-ch RTZ Supertex Inc. HV7355K6-G
X1 OSC CLOCK 40.000MHz 3.3V SMD CTS CB3LV-3C-40.0000-T