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Summary of Thermal Studies of L-Shape Module

Steven Blusk, Brian MaynardSyracuse University

Velo Upgrade Workshop, Module 0, May 5, 2010

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Introduction• Thermo-mechanical issues

– Keep silicon safely away from the point at which it will thermal run away.

– Minimize thermal gradient across module• Mechanical deformation, internal stresses, bi-metallic effects, etc.

• Here, I will focus on L-shape design, as this is favorable from a physics perspective.

• Thermal modeling using ANSYS– Focus for today– Should mention we did compare some simple thermal simulations with

analytical calculations, and they agreed.

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L-Shape GeometryRay Mountain, 3-24-2010

1 2 3

4 5 6

7 8

9 10

11 12

In ‘diamond option’diamond detectorsclose to IP, underneathchips 4, 5, 7, and 9.

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Basic “Agreed-on” Parametersrelevant for thermal analysis

• Substrate Thickness: 200 m – Diamond assumed for now.

• Silicon thickness: 150 m• Chip:

– Size: 14.1 mm x 14.1 mm (+ 1 mm for digital back end.)– Total chip power < 3 W/chip

• Analog Pixel Power: < 1.3 W/chip. (15-20 W/pixel) Digital power < 1.7 W/cm2 (in pixel vs backend ?)

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Materials in the “Sandwich”

Silicon 0.150

ASIC 0.150

Substrate 0.200

Epoxy 0.050Al 0.050

All dimensions in mm

Material Thermal Conductivity

(W / m K)

Silicon 150

ASICs 190

Glue 1

Aluminum 200

CVD Diamond 1600

Very small sensitivity to using slightly different values.

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Cooling Channel Placement

1.0 cm

1.5 cm

Cooling Channel

Drawing complimentsof R. Mountain

NB: 50 um of gluebetween cooling channel & substrate

Obvious, this isnot a “real” coolingchannel, but basicallyfixes the temperatureat a fixed distance fromsilicon edge.

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Power Contributions - Silicon

-1.91 16

0 -4

1 16 6 30

0.6 1 1exp

8.2 8.62 10

/

248

8.13 10 /

e

ref ref

O

ref

e

T rP P

T x T T

P Power Volume

T temp in K

r radius in mm

T K

P W m

Beneficial annealing reduces current by ~ 40%, and is included in

Silicon self-heating (at 1x1016 neq/cm2, 900 V)Radial & temperature dependent power dissipation in silicon

1 160

eP

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Power Contribution - Chip Power

(1) PA = Constant analog pixel power Vary from 0.5 to 1.5 W / chip

(2) Radial dependent power (Pr)Occupancy-dependent power (?) Pr = Kp (7.5 mm/r) (vary Kp from 0.5 – 2.5)

Digital Power in Backend of chip (PD) : PD: Vary from 0.5 to 2.5 W/chip

Analog power in pixel cells.Assume 2 contributions.

r

chip

P da

Total Pr vs Chip #

1 2 3

4 5 6

7 8

9 10

11 12

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Methodology

1. Fix cooling channel at -35 C

2. Fix the Analog Power, PA (say 0.5 W/chip) Vary digital back end power, PD and radial-

dependent power, Pr.

Record highest temperature of silicon. Make ‘highest temperature table’ for PD vs Pr

3. Repeat step 2 for 1.0 W/chip and 1.5 W/chip

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Results

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PA = 0.5 W/chip

W/chip 0.5 1 1.5 2 2.5 T<

0.5 -24.6 -20.7 -16.6 -12.1 -7.3 10

1 -22.8 -18.8 -14.6 -10.2 -5.3 15

1.5 -21.0 -16.9 -12.7 -8.1 -2.8 20

2 -19.1 -15.0 -10.6 -5.8 0.1 25

2.5 -17.3 -13.0 -8.5 -3.3 3.5 30

PD (W/chip)

KP

Table shows the highest temperature of the silicon sensor.‘Dash’ meansThermalRunaway

50

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PA = 1.0 W/chip

W/chip 0.5 1 1.5 2 2.5 T<

0.5 -19.9 -15.8 -11.5 -6.8 -1.1 10

1 -18.1 -13.9 -9.4 -4.4 2.1 15

1.5 -16.2 -11.9 -7.2 -1.8 6.5 20

2 -14.2 -9.8 -4.9 1.2 - 25

2.5 -12.3 -7.7 -2.4 5.0 - 30

PD (W/chip)

KP

Table shows the highest temperature of the silicon sensor. PA=1.0 W/chipPD=1.5 W/chipPr ~ 0.2-0.5 W/chip

50

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PA = 1.5 W/chip

W/chip 0.5 1 1.5 2 2.5 T<

0.5 -15.0 -10.6 -5.7 0.2 - 10

1 -13.0 -8.5 -3.3 3.7 - 15

1.5 -11.0 -6.2 -0.4 9.6 - 20

2 -8.9 -3.8 2.7 - - 25

2.5 -6.7 -1.2 7.2 - - 30

PD (W/chip)

KP

Table shows the highest temperature of the silicon sensor.PA=1.5 W/chipPD=1.5 W/chipPr ~ 0.2-0.5 W/chip

50

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Thermal Profile – “Low Power” Scenario

“Low power”scenario

PA=0.5 W/chipPD=0.5 W/chipkP=0.5

Note that upper & lower half not exactly symmetric with respect to distance tocooling channel(see slide 6)

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Thermal Profile – “High Power” Scenario

“High power”scenario

PA=1.5 W/chipPD=1.5 W/chipkP=1.5

Not a whole lot of headroom if chip is near theupper end of the spec.

Should try very hard tokeep chip power “wellbelow” the spec. value.

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Summary (1)• For chip power close to maximum values in

Timepix2 specs (see talk by Xavi Llopart here), silicon approaches ~ -5 C, close to runaway..– If no radial dependent power (Pr=0), gain 1-2 C.

– Critical to keep power to a minimum.– This assumes we can deliver -35C to cooling

channels.. Can an upgraded CO2 cooling system achieve this????

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Summary (2) Other tests performed & considerations• Splitting top 6 chips and bottom 6 chips give comparable

thermal performance to full module (to within 1 C)• Thicker diamond substrate 200 m400 m would give

about ~2-3 C lower temperature. (Diamond not bottleneck)• Could move cooling channel closer than 1.5 cm (or 1.0 cm)

along the one edge? Would help a bit..– Moving further away would have significant consequences.

• ‘Diamond option’ would certainly help thermally:– In “low power” scenario, Tmax decreases -24.6 C -25.2 C – In “high power” scenario, Tmax decreases ~ -3 C -9 C

• Simulations for dose of 1.0x1016 neq/cm2 (~100 fb-1)– If only 50 fb-1, then half the dose, lower silicon power loss.

• Need head room! Some possible small gains or losses having to do with glue conductivity, thickness, other heat loads, etc.

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Summary (3)Questions

• Real estate availability for cooling channel and readout cables from chips?– How close can we get the cooling lines?– Any idea what the readout cables will look like?

Cu-Kapton flex?

• Tube should be low profile, squished down.The ‘art of tube squishing’.

• Possibly thermal “fingers” instead of tubes?

• How cold can we get with upgraded cooling plant?

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Plans• Armed with these tools and detailed

simulations, we’d like to construct a mechanical mock up (starting this summer)– Substrate, 2 silicon layers, glue, heaters,

cooling, RTDs, etc– Measure thermal profile (in vacuum), and

compare to ANSYS simulation of the mechanical model.

• Also thinking about modeling the thermal stresses and mechanical deformations.