Study of PIC Development Board

7/25/2019 Study of PIC Development Board

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Ex No 1 Study of PIC Development Board

Peripheral Interface Controller(16f8!" #

$i%h&Performance 'ISC CP

Only 35 single-word instructions to learn

All single-cycle instructions except for program

branches, which are two-cycle

Operating speed: DC !" #$% cloc& input

DC !"" ns instruction cycle

'p to () x *+ words of lash rogram #emory,

'p to 3.( x ( bytes of Data #emory /0A#1,

'p to !5. x ( bytes of 220O# Data #emory

inout compatible to other !(-pin or +"++-pin

4C*.C and 4C*. microcontrollers6

Peripheral )eature*

7imer": (-bit timercounter with (-bit prescaler

7imer*: *.-bit timercounter with prescaler,can be incremented during

8leep 9ia external crystalcloc& 7imer!: (-bit timercounter with (-bit period register, prescaler and

postscaler 7wo Capture, Compare, # modules

Capture is *.-bit, max6 resolution is *!65 ns

Compare is *.-bit, max6 resolution is !"" ns

# max6 resolution is *"-bit

8ynchronous 8erial ort /881 with 84 /#aster mode1 and 4!C

/#aster8la9e1 'ni9ersal 8ynchronous Asynchronous 0ecei9er 7ransmitter /'8A078C41

with ;-bit address detection arallel 8la9e ort /81 ( bits wide withexternal 0D, 0 and C8

controls /+"++-pin only1


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Special +icrocontroller )eature*:

*"",""" erasewrite cycle 2nhanced lash program memory typical

*,""",""" erasewrite cycle Data 220O# memory typical

Data 220O# 0etention > +" years

8elf-reprogrammable under software control 4n-Circuit 8erial rogramming? /4C81 9ia two pins

8ingle-supply 5= 4n-Circuit 8erial rogramming

atchdog 7imer /D71 with its own on-chip 0C oscillator for reliable

operation rogrammable code protection

ower sa9ing 8leep mode

8electable oscillator options

4n-Circuit Debug /4CD1 9ia two pins

)i%,PIC 16f8 !

!rchitecture of PIC16)8

PIC microcontroller*are based on ad9anced 'ISC architecture,048C stands for 0educed

4nstruction 8et Computing6 4n this architecture, the instruction set of hardware gets reduced which

increases the execution rate /speed1 of system6 4C microcontrollers follow $ar9ard architecture for


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internal data transfer6 4n $ar9ard architecture there are two separate memories for program and data6

7hese two memories are accessed through different buses for data communication between memories

and C' core6 7his architecture impro9es the speed of system o9er =on @eumann architecture in

which program and data are fetched from the same memory using the same bus6 4C*. series

controllers are (-bit instruction set6 4C*( series controllers are based on *.-bit instruction set64n

addition, the 4C family is based on a 0educed 4nstruction 8et Computer /048C1 configuration whichit use fewer instructions than a Complex 4nstruction 8et Computer /C48C16 All the 4C de9ices use

less than ." instructions64n general, the 4C*. de9ices ha9e only 35 instructions, whereas the

4C* de9ices ha9e only 5( instructions6 7here is a substantial amount of program code

compatibility amongst ; different de9ices in the 4C family6 A program written for one 4C de9ice

can easily be assembled and used in another de9ice type with a minimum number of modifications6

7he 4C family is fully static de9ices, meaning that they preser9e the contents of their

registers when the cloc& freBuency is reduced to %ero6 4n 4C microcontrollers, each instruction ta&es

four cloc& periods to execute6 4f a *#$% cloc& freBuency is used, the corresponding cloc& period is

*sec, so each instruction will ta&e +secthis time is called the instruction cycle time67he fastestde9ices in the 4C family can operate at cloc& freBuencies up to 33#$%, with corresponding

instruction cycle times of *!*nsec6 #ost instructions execute in one instruction cycle, but some

reBuire two cycles because they need to branch to some destination other than the next address in the

C6#icrochip characteri%es 4C microcontrollers according to their instruction word lengths6

7he low-end 4Cs, such as the eight pin *!C5 series, ha9e *! bit word length

instructions6 7he midrange 4Cs, such as the 4C*., ha9e *+ bit instructions and the high-end

* 4Cs ha9e *. bit instructions6 All 4C microcontrollers are, howe9er, classified as eight bit

microcontrollers as they all manipulate data in byte units on an eight bit wide data bus6A detailed

&nowledge or understanding of these concepts is not essential to actually use 4C microcontrollersall that is needed is practice in writing programs and some experimentation with microcontroller

circuits to gain experience6


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7he Buestion may arise that if 4C*( are called (-bit microcontrollers, then what about them being

based on *.-bit instructions set6 E4C*( is an (-bit microcontrollerF this statement means that the

C' core can recei9etransmit or process a maximum of (-bit data at a time6 On the other hand the

statement E4C*( microcontrollers are based on *.-bit instruction setF means that the assembly

instruction sets are of *.-bit6

7he data memory is interfaced with (-bit bus and program memory is interfaced with *.-bit bus as

depicted in the following figure6


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7he high performance of the 4Cmicro? de9ices can be attributed to a number of architectural

features commonly found in 048C microprocessors6 7hese include:

$ar9ard architecture

Gong ord 4nstructions

8ingle ord 4nstructions

8ingle Cycle 4nstructions

4nstruction ipelining

0educed 4nstruction 8et

0egister ile Architecture

Orthogonal /8ymmetric1 4nstructions

Harvard Architecture

$ar9ard architecture has the program memory and data memory as separate memories and is

accessed from separate buses6


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7his impro9es bandwidth o9er traditional 9on @eumann architecture in which program and data arefetched from the same memory using the same bus6 7o execute an instruction, a 9on @eumann

machine must ma&e one or more /generally more1 accesses across the (-bit bus to fetch the

instruction6

7hen data may need to be fetched, operated on, and possibly written6 As can be seen from this

description, that bus can be extremely contested6 hile with a $ar9ard architecture, the instruction is

fetched in a single instruction cycle /all *+-bits16

hile the program memory is being accessed, the data memory is on an independent bus and can be

read and written6 7hese separated buses allow one instruction to execute while the next instruction is

fetched6


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Long Word Instructions

Gong word instructions ha9e a wider /more bits1 instruction bus than the (-bit Data #emory


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7he fetch of the instruction ta&es one 7CH, while the execution ta&es another 7CH6 $owe9er, due to

the o9erlap of the fetch of current instruction and execution of pre9ious instruction, an instruction is

fetched and another instruction is executed e9ery single 7CH6

Single Cycle Instructions

ith the rogram #emory bus being *+-bits wide, the entire instruction is fetched in a single

machine cycle /7CH16 7he instruction contains all the information reBuired and is executed in a

single cycle6

7here may be a one cycle delay in execution if the result of the instruction modified the contents of

the rogram Counter6 7his reBuires the pipeline to be flushed and a new instruction to be fetched6

Reduced Instruction Set

hen an instruction set is well designed and highly orthogonal /symmetric1, fewer instructions are

reBuired to perform all needed tas&s6 ith fewer instructions, the whole set can be more rapidly

learned6

Register File Architecture

7he register filesdata memory can be directly or indirectly addressed6 All special function registers,

including the program counter, are mapped in the data memory6


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Orthogonal (Symmetric Instructions

Orthogonal instructions ma&e it possible to carry out any operation on any register using any

addressing mode6 7his symmetrical nature and lac& of Ispecial instructionsJ ma&e programmingsimple yet efficient6 4n addition, the learning cur9e is reduced significantly6

7he mid-range instruction set uses only two non-register oriented instructions, which are used for

two of the cores features6

One is the 8G22 instruction which places the de9ice into the lowest power use mode6 7he other is

the CG0D7 instruction which 9erifies the chip is operating properly by pre9enting the on-chip

atchdog 7imer /D71 from o9erflowing and resetting the de9ice6

Instruction Flo!"Pipelining

An I4nstruction CycleJ consists of four K cycles /K*, K!, K3, and K+16 etch ta&es one instruction

cycle while decode and execute ta&es another instruction cycle6 $owe9er, due to ipelining, each

instruction effecti9ely executes in one cycle6 4f an instruction causes the program counter to change

/e6g6 LO7O1 then an extra cycle is reBuired to complete the instruction6

7he instructionfetchbegins with the program counter incrementing in K*6

4n the execution cycle, the fetched instruction is latched into the I4nstruction 0egister /401J in cycle

K*6 7his instruction is then decoded and executed during the K!, K3, and K+ cycles6 Data memory is

read during K! /operand read1 and written during K+ /destination writes16


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7he abo9e process occurs in a single machine cycle6 4n 4C microcontroller, a single machine cycle

consists of + oscillation periods6 7hus an instruction needs + cloc& periods to be executed6 7his

ma&es it faster than other ("5* microcontrollers6

2arly processors and controllers could fetch or execute a single instruction in a unit of time6 7he 4C

microcontrollers are able to fetch and execute the instructions in the same unit of time thus increasing

their instruction throughput6

7his techniBue is &nown as instruction pipelining where the processing of instructions is split into a

number of independent steps6


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#$#OR% OR&A'IA)IO' OF PIC*+F,--

7here are two memory bloc&s in the #emory Organi%ation program memory and data memory6

2ach bloc& has its own bus, so that access to each bloc& can occur during the same oscillator cycle67he data memory can further be bro&en down into Leneral urpose 0A# and the 8pecial unction

0egisters /80s16

7he operations of the 80s that control the IcoreJ are described here6 7he 80s used to control the

peripheral modules are described in the section discussing each indi9idual peripheral module6

7he memory of a 4C *.( chip is di9ided into 3 sections6 7hey are,

rogram memory

Data memory and

Data 220O#

Program memory

rogram memory contains the programs that are written by the user6 7he program counter /C1

executes these stored commands one by one6 'sually 4C*.( de9ices ha9e a *3 bit wide program

counter that is capable of addressing ()M*+ bit program memory space6 7his memory is primarily

used for storing the programs that are written /burned1 to be used by the 4C6

7hese de9ices also ha9e ()N*+ bits of flash memory that can be electrically erasable reprogrammed6

2ach time we write a new program to the controller, we must delete the old one at that time6 7he

figure below shows the program memory map and stac&6


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0eset =ector

On any de9ice, a reset forces the rogram Counter /C1 to address "h6 e call this address the I0eset

=ector AddressJ since this is the address that program execution will branch to when a de9ice resetoccurs6 Any reset will also clear the contents of the CGA7$ register6 7his means that any branch at

the 0eset =ector Address /"h1 will ump to that location in AL2" of the program memory6

4nterrupt =ector

hen an interrupt is ac&nowledged the C is forced to address """+h6 e call this the I4nterrupt

=ector AddressJ6

hen the C is forced to the interrupt 9ector, the CGA7$ register is not modified6 Once in the

ser9ice interrupt routine /4801, this means that before any write to the C, the CGA7$ register

should be written with the 9alue that will specify the desired location in program memory6


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7he program counter /C1 specifies the address of the instruction to fetch for execution6 7he C is

*3-bits wide6 7he low byte is called the CG register6 7his register is readable and writable6 7he high

byte is called the C$ register6 7his register contains the CP*!:(> bits and is not directly readable

or writable6 All updates to the C$ register go through the CGA7$ register6

8tac&

7he stac& allows a combination of up to ( program calls and interrupts to occur6 7he stac& contains

the return address from this branch in program execution6 #id-0ange #C' de9ices ha9e an (-le9el

deep x *3-bit wide hardware stac&6 7he stac& space is not part of either program or data space and

the stac& pointer are not readable or writable6 7he C is pushed onto the stac& when a CAGG

instruction is executed or an interrupt causes a branch6

7he stac& is popped in the e9ent of a 027'0@, 027G or a 02742 instruction execution6

CGA7$ is not modified when the stac& is ushed or opped6

After the stac& has been pushed eight times, the ninth push o9erwrites the 9alue that was stored fromthe first push6 7he tenth push o9erwrites the second push6

Note 1#

7here are no status bits to indicate stac& o9erflow or stac& underflow conditions6 7here are no

instructionsmnemonics called '8$ or O6 7hese are actions that occur from the execution of the

CAGG, 027'0@, 027G, and 02742 instructions, or the 9ectoring to an interrupt address6


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rogram #emory aging

8ome de9ices ha9e program memory si%es greater then !) words, but the CAGG and LO7O

instructions only ha9e a **-bit address range6 7his **-bit address range allows a branch within a !)program memory page si%e6

7o allow CAGG and LO7O instructions to address the entire *) program memory address range,

there must be other two bits to specify the program memory page6 7hese paging bits come from the

CGA7$P+:3> bits6 hen doing a CAGG or LO7O instruction, the user must ensure that page bits

/CGA7$P+:3>1 are programmed so that the desired program memory page is addressed6 hen one

of the return instructions is executed, the entire *3-bit C is popped from the stac&6 7herefore,

manipulation of the CGA7$P+:3> is not reBuired for the return instructions6

.ata #emory Organi/ation

7he data memory of 4C*.( is separated into multiple ban&s which contain the general purpose

registers /L01 and special function registers /8016 According to the type of the microcontroller,

these ban&s may 9ary6 7he 4C*.( chip only has four ban&s /


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7hese control bits are located in the 87A7'8 0egister /87A7'8P:5>16 7o mo9e 9alues from one

register to another register, the 9alue must pass through the register6 7his means that for all

register-to-register mo9es, two instruction cycles are reBuired6 7he entire data memory can be

accessed either directly or indirectly6 Direct addressing may reBuire the use of the 0*:0" bits6

4ndirect addressing reBuires the use of the ile 8elect 0egister /8016

4ndirect addressing uses the 4ndirect 0egister ointer /401 bit of the 87A7'8 register for accesses

into the


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Note#7he 8pecial unction 0egister /801 Area may ha9e Leneral urpose 0egisters /L0s1

mapped in these locations6


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4f the 87A7'8 register is the destination for an instruction that affects the Q, DC or C bits, then the

write to these three bits is disabled6 7hese bits are set or cleared according to the de9ice logic6

urthermore, the 7O and D bits are not writable, therefore, the result of an instruction with the87A7'8 register as destination may be different than intended6

O74O@R02L 0egister

7he O74O@R02L 0egister is a readable and writable register, which contains 9arious control bits

to configure the 7#0" pre-scalerD7 post-scaler, the 2xternal 4@7 4nterrupt, 7#0" and the wea&pull-ups on O0716 'ser software should ensurethe appropriate interrupt flag bits are clear prior to enabling an interrupt6

42* 0egister


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7he 42* register contains the indi9idual enable bits for the peripheral interrupts6

40* 0egister

7he 40* register contains the indi9idual flag bits for the peripheral interrupts6

@ote:

4nterrupt flag bits are set when an interrupt condition occurs, regardless of the state of its

corresponding enable bit or the global enable bit, L42 /4@7CO@P>16 'ser software should ensure

the appropriate interrupt bits are clear prior to enabling an interrupt6

42! 0egister

7he 42! register contains the indi9idual enable bits for the CC! peripheral interrupt, the 88 bus

collision interrupt, and the 220O# write operation interrupt6

40! 0egister

7he 40! register contains the flag bits for the CC! interrupt, the 88 bus collision interrupt and the

220O# write operation interrupt6

@ote:


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4nterrupt flag bits are set when an interrupt condition occurs, regardless of the state of its

corresponding enable bit or the global enable bit, L42 /4@7CO@P>16

'ser software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt6

CO@ 0egister

7he ower Control /CO@1 0egister contains flag bits to allow differentiation between a ower-on

0eset /O01, a


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instruction using the 4@D register actually accesses the register pointed to by the ile 8elect

0egister, 806

0eading the 4@D register itself indirectly /80 S T"T1 will read ""h6 riting to the 4@D register

indirectly results in a no-operation /although status bits may be affected16 An effecti9e ;-bit address

is generated by the concatenation of the 40 bit /87A7'8P>1 with the (-bit 80 register6

.ata $$PRO# and FLASH #emory

7he data 220O# and lash program memory is readable and writable during normal operation

/o9er the full =DD range16 7his memory is not directly mapped in the register file space6 4nstead, it is

indirectly addressed through the 8pecial unction 0egisters6

7he 220O# data memory allows single-byte read and writes6 7he lash program memory allows

single-word reads and four-word bloc& writes6 rogram memory write operations automatically

perform an erase-before write on bloc&s of four words6 A byte write in data 220O# memory

automatically erases the location and writes the new data /erase-before-write16 7he write time is

controlled by an on-chip timer6 7he writeerase 9oltages are generated by an on-chip charge pump,

rated to operate o9er the 9oltage range of the de9ice for byte or word operations6

7he 220O# Data memory is rated for high erase writes cycles6 7he GA8$ program memory is

rated much lower, because 220O# data memory can be used to store freBuently updated 9alues6

An on-chip timer controls the right time and it will 9ary with 9oltage and temperature, as well as

from chip to chip6

A byte or word write automatically erases the location and writes the new 9alue6 riting to

220O# data memory does not impact the operation of the de9ice6


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riting to program memory will cease the execution of instructions until the write is complete6 7he

program memory cannot be accessed during the write6 During the write operation, the oscillator

continues to run, the peripherals continue to function and interrupt e9ents will be detected andessentially IBueuedJ until the write is complete6 hen the write completes, the next instruction in the

pipeline is executed and the branch to the interrupt 9ector will ta&e place, if the interrupt is enabled

and occurred during the write6

0ead and write access to both memories ta&e place indirectly through a set of 8pecial unction

0egisters /8016 7he six 80s used are:

22DA7A

22DA7$

22AD0

22AD0$

22CO@*

22CO@!

7he 220O# data memory allows byte read and writes operations without interfering with the

normal operation of the microcontroller6

hen interfacing to 220O# data memory, the 22AD0 register holds the address to be accessed6

Depending on the operation, the 22DA7A register holds the data to be written, or the data read, at the

address in 22AD06

7he 4C*.(3(+ de9ices ha9e *!( bytes of 220O# data memory and therefore, reBuire that the

#8< of 22AD0 remain clear6 7he 220O# data memory on these de9ices does not wrap around to

", i6e6, "x(" in the 22AD0 does not map to "x""6 7he 4C*.(.( de9ice has !5. bytes of

220O# data memory and therefore, uses all (-bits of the 22AD06


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7he GA8$ program memories allows non-intrusi9e read access, but write operations cause the

de9ice to stop executing instructions, until the write completes6

hen interfacing to the program memory, the 22AD0$: 22AD0 registers form a two-byte word,

which holds the *3-bit address of the memory location being accessed6 7he register combination of

22DA7$: 22DA7A holds the *+-bit data for writes, or reflects the 9alue of program memory after a

read operation6

Uust as in 220O# data memory accesses, the 9alue of the 22AD0$: 22AD0 registers must be

within the 9alid range of program memory, depending on the de9ice: """"h to *h for the

4C*.(3(+, or """"h to 3h for the 4C*.(.(6 Addresses outside of this range do not

wrap around to """"h6

22CO@* and 22CO@! 0egisters

7he 22CO@* register is the control register for configuring and initiating the access6 7he 22CO@!

register is not a physically implemented register, but is used exclusi9ely in the memory write

seBuence to pre9ent inad9ertent writes6

7here are many bits used to control the read and write operations to 220O# data and GA8$

program memory6 7he 22LD bit determines if the access will be a program or data memory access6

hen clear, any subseBuent operations will wor& on the 220O# data memory6 hen set, all

subseBuent operations will operate in the program memory6


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7he desired memory location pointed to by 22AD0$: 22AD0 will be erased6 7hen, the data 9alue

in 22DA7$: 22DA7A will be programmed6 hen complete, the 224 flag bit will be set and the

microcontroller will continue to execute code6

7he 0200 bit is used to indicate when the 4C*.( de9ice has been reset during a write

operation6 0200 should be cleared after ower-on 0eset6 7hereafter, it should be chec&ed on any

other 028276

7he 0200 bit is set when a write operation is interrupted by a #CG0 0eset, or a D7 7ime-out

0eset, during normal operation6 4n these situations, following a 02827, the user should chec& the

0200 bit and rewrite the memory location, if set6

7he contents of the data registers, address registers and 22LD bit are not affected by either #CG0

0eset, or D7 7imeout 0eset, during normal operation6

0eading the 220O# Data #emory

0eading 220O# data memory only reBuires that the desired address to access be written to the

22AD0 register and clear the 22LD bit6 After the 0D bit is set, data will be a9ailable in the

22DA7A register on the 9ery next instruction cycle6

22DA7A will hold this 9alue until another read operation is initiated or until it is written by

firmware6

7he steps to reading the 220O# data memory are:


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rite the address to 22DA7A6 #a&e sure that the address is not larger than the memory si%e of the 4C*.( de9ice6

Clear the 22LD bit to point to 220O# data memory6

8et the 0D bit to start the read operation6

0ead the data from the 22DA7A register6

riting to the 220O# Data #emory

7here are many steps in writing to the 220O# data memory6


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Clear the 22LD bit to point to 220O# data memory6

8et the 02@ bit to enable program operations6

Disable interrupts /if enabled16

2xecute the special fi9e instruction seBuence:

- rite 55h to 22CO@! in two steps /first to ,then to 22CO@!1

- rite AA to 22CO@! in two steps /first to , then to 22CO@!1

- 8et the 0 bit 2nable interrupts /if using interrupts16

Clear the 02@ bit to disable program operations6

At the completion of the write cycle, the 0 bit is cleared and the 224 interrupt flag bit is set6

0eading the GA8$ rogram #emory

0eading GA8$ program memory is much li&e that of 220O# data memory, only two @O

instructions must be inserted after the 0D bit is set6

7hese two instruction cycles that the @O instructions execute, will be used by the microcontroller to

read the data out of program memory and insert the 9alue into the 22DA7$: 22DA7A registers6

Data will be a9ailable following the second @O instruction6 22DA7$ and 22DA7A will hold their

9alue until another read operation is initiated, or until they are written by firmware6

7he steps to reading the GA8$ program memory are:

rite the address to 22AD0$: 22AD06 #a&e sure that the address is not larger than the memory si%e of the 4C*.(

de9ice6

8et the 22LD bit to point to GA8$ program memory6

8et the 0D bit to start the read operation6

2xecute two @O instructions to allow the microcontroller to read out of program memory6 0ead the data from the 22DA7$: 22DA7A registers6

riting to the GA8$ rogram #emory


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riting to GA8$ program memory is uniBue, in that the microcontroller does not execute

instructions while programming is ta&ing place6 7he oscillator continues to run and all peripherals

continue to operate and Bueue interrupts, if enabled6 Once the write operation completes, the

processor begins executing code from where it left off6 Uust li&e 220O# data memory, there are

many steps in writing to the GA8$ program memory6


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I"O Registers

7hese registers are used for the 4O control6 29ery 4O port in the 4C microcontroller has two

registers: port data register and port direction control register6

ort data register has the same name as the port it controls6 or example, the 4C*.(A

microcontroller has fi9e port data registers, O07A, O07


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)imer Registers

Depending on the model used, some 4C microcontrollers ha9e only one timer, and some may ha9e

up to three timers6 4n this section we shall loo& at the 4C*.(+ microcontroller, which has only onetimer6 7he extension to se9eral timers is similar and we shall see in the proects section how to use

more than one timer6

7he timer in the 4C*.(+ microcontroller is an (-bit register /called 7#0"1, which can be used as a

timer or a counter6 hen used as a counter, the register increments each time a cloc& pulse is applied

to pin 7"C)* of the microcontroller6

hen used as a timer, the register increments at a rate determined by the system cloc& freBuency and

a pre-scaler selected by register O74O@R02L6 rescaler rates 9ary from *:! to *:!5.6 or example,

when using a +-#$% cloc&, the basic instruction cycle is * Rs /the cloc& is internally di9ided by

four16 4f we select a pre-scaler rate of *:*., the counter will be incremented at e9ery *. Rs6 7he

7#0" register has address "* in the 0A#6

A timer interrupt is generated when the timer o9erflows from !55 to "6 7his interrupt can be enabled

or disabled by our program6 7hus, for example, if we need to generate interrupts at inter9als of !""

Rs using a +-#$% cloc&, we can select a pre-scaler 9alue of *:+ and enable timer interrupts6

7he timer cloc& rate is then + Rs6 or a time-out of !"" Rs, we ha9e to send 5" cloc&s to the timer6

7hus, the 7#0" register should be loaded with !5. 5" R !".Vi6e6, a count of 5" before an

o9erflow occurs6 7he watchdog timerFs oscillator is independent from the C' cloc& and the time-out is *( ms6

7o pre9ent a time-out condition the watchdog must be reset periodically 9ia software6 4f the

watchdog timer is not reset before it times out, the microprocessor will be forced to ump to the reset


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address6 7he pre-scaler can be used to extend the time-out period and 9alid rates are *, !, +, (, *., 3!,

.+, and *!(6 or example, when set to *!(, the time-out period is about ! s /*( R *!( R !3"+ ms16

7he watchdog timer can be disabled during programming of the de9ice if it is not used6

A". Converter Registers

7he AD con9erter is used to interface analog signals to the microcontroller6

7he AD con9erts analog signals /e6g6, 9oltage1 into digital form so that they can be connected to acomputer6 AD con9erter registers are used to control the AD con9erter ports6 On most 4C

microcontrollers eBuipped with AD, O07A pins are used for analog input and these port pins are

shared between digital and analog functions6

4C*.(. includes fi9e AD con9erters6 8imilarly, 4C*.( includes eight AD con9erters6 7he

width of the AD con9erter can be ( bits or *" bits6


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usually timer interrupts, such as the timer o9erflow generating an interrupt6 Depending on the model

used, different 4C microcontrollers may ha9e a different number of interrupt sources6 or example,

the 4C*.(+ microcontroller has the following four sources of interrupts:

2xternal interrupts from 4@7 /0


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7he C' sometimes wor&s in conunction with the AG' to complete the execution of the instruction

/in arithmetic and logical operations16 7he C' controls the program memory address bus, the data

memory address bus, and accesses to the stac&6

4nstruction Cloc&

2ach instruction cycle /7CH1 is comprised of four K cycles /K*-K+16 7he K cycle time is the same

as the de9ice oscillator cycle time /7O8C16 7he K cycles pro9ide the timingdesignation for the

Decode, 0ead, rocess Data, rite, etc6, of each instruction cycle6 7he following diagram shows therelationship of the K cycles to the instruction cycle6

7he four K cycles that ma&e up an instruction cycle /7CH1 can be generali%ed as:

K*: 4nstruction Decode Cycle or forced @o operation

K!: 4nstruction 0ead Data Cycle or @o operation

K3: rocess the Data

K+: 4nstruction rite Data Cycle or @o operation


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2ach instruction will show a detailed K cycle operation for the instruction6

Arithmetic Gogical 'nit /AG'1

4Cmicro #C's contain an (-bit AG' and an (-bit wor&ing register6 7he AG' is a general purpose

arithmetic and logical unit6 4t performs arithmetic and


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are non9olatile memory locations and the operating mode is determined by the 9alue

written during de9ice programming6 7he oscillator modes are:

X G Gow reBuency /ower1 Crystal

X 7 Crystal0esonator

X $8 $igh 8peed Crystal0esonator

X 0C 2xternal 0esistorCapacitor /same as 270C with CG)O'71

X 270C 2xternal 0esistorCapacitor

X 270C 2xternal 0esistorCapacitor with CG)O'7

X 4@70C 4nternal + #$% 0esistorCapacitor

X 4@70C 4nternal + #$% 0esistorCapacitor with CG)O'7

7hese oscillator options are made a9ailable to allow a single de9ice type the Yexibility to

Wt applications with different oscillator reBuirements6

$i%h Speed

ro9ides highest dri9e le9el a9ailable for crystals and ceramic resonators

Designed for + #$% and higher freBuency crystals and and most ceramic

resonators $ighest current consumption, but the fastest mode a9ailable

opular mode for resonators since they tend to reBuire a stronger dri9e thancrystals

!lphanumeric .CD #

GCD /GiBuid Crystal Display1 screen is an electronic display module and find a

wide range of applications6 A *.x! GCD display is 9ery basic module and is 9ery

commonly used in 9arious de9ices and circuits6 7hese modules are preferred o9er se9en

segmentsand other multi segment G2Ds6 7he reasons being: GCDs are economical

easily programmable ha9e no limitation of displaying special Z e9encustom

characters/unli&e in se9en segments1, animationsand so on6

A *.x! GCD means it can display *. characters per line and there are ! such

lines6 4n this GCD each character is displayed in 5x pixel matrix6 7his GCD has two

registers, namely, Command and Data6 7he command register stores the command

instructions gi9en to the GCD6 A command is an instruction gi9en to GCD to do a

predefined tas& li&e initiali%ing it, clearing its screen, setting the cursor position,

controlling display etc6 7he data register stores the data to be displayed on the GCD6 7he
http://www.engineersgarage.com/content/seven-segment-displayhttp://www.engineersgarage.com/content/seven-segment-displayhttp://www.engineersgarage.com/content/ledhttp://www.engineersgarage.com/microcontroller/8051projects/create-custom-characters-LCD-AT89C51http://www.engineersgarage.com/microcontroller/8051projects/create-custom-characters-LCD-AT89C51http://www.engineersgarage.com/microcontroller/8051projects/create-custom-characters-LCD-AT89C51http://www.engineersgarage.com/microcontroller/8051projects/display-custom-animations-LCD-AT89C51http://www.engineersgarage.com/content/ledhttp://www.engineersgarage.com/microcontroller/8051projects/create-custom-characters-LCD-AT89C51http://www.engineersgarage.com/microcontroller/8051projects/create-custom-characters-LCD-AT89C51http://www.engineersgarage.com/microcontroller/8051projects/display-custom-animations-LCD-AT89C51http://www.engineersgarage.com/content/seven-segment-displayhttp://www.engineersgarage.com/content/seven-segment-display


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data is the A8C44 9alue of the character to be displayed on the GCD6 Clic& to learn more

about internal structure of aGCD6

Pin Description:

/0/ matrix di*play #

7his *.-button &eypad pro9ides a useful human interface component for

microcontroller proects6 Con9enient adhesi9e bac&ing pro9ides a simple way to mount

the &eypad in a 9ariety of applications6

#atrix &eypads use a combination of four rows and four columns to pro9ide

button states to the host de9ice, typically a microcontroller6 'nderneath each &ey is a

pushbutton, with one end connected to one row, and the other end connected to one

column6 7hese connections are shown in igure *6

Pin

No)unction Name

* Lround /"=1 Lround

! 8upply 9oltage 5= /+6= 563=1 =cc

3 Contrast adustment through a 9ariable resistor =22
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+ 8elects command register when low and data register when high 0egister 8elect

5 Gow to write to the register $igh to read from the register 0eadwrite

. 8ends data to data pins when a high to low pulse is gi9en 2nable

(-bit data pins

D

** D


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chip charge pumpsand external capacitors6 7his ma&es it useful for implementing 08-!3! in de9ices

that otherwise do not need any 9oltages outside the " = to [ 5 = range, aspower supplydesign does

not need to be made more complicated ust for dri9ing the 08-!3! in this case6 7he recei9ers reduce

08-!3! inputs /which may be as high as \ !5 =1, to standard 5 = 77Gle9els6 7hese recei9ers ha9e a

typical threshold of *63 =, and a typical hysteresisof "65 =6

4t is helpful to understand what occurs to the 9oltage le9els6 hen a #A!3! 4C recei9es a

77G le9el to con9ert, it changes a 77G logic " to between [3 and [*5 =, and changes 77G logic * to

between -3 to -*5 =, and 9ice 9ersa for con9erting from 08!3! to 77G6 7his can be confusing when

you reali%e that the 08!3! data transmission 9oltages at a certain logic state are opposite from the

08!3! control line 9oltages at the same logic state

'S232 line type and lo%ic level 'S232 volta%e 44. volta%e to5from +!232

Data transmission /0x7x1 logic " [3 = to [*5 = " =

Data transmission /0x7x1 logic * -3 = to -*5 = 5 =

Control signals /078C78D70D801 logic " -3 = to -*5 = 5 =

Control signals /078C78D70D801 logic * [3 = to [*5 = " =

ig6#A !3!
https://en.wikipedia.org/wiki/Charge_pumphttps://en.wikipedia.org/wiki/Charge_pumphttps://en.wikipedia.org/wiki/Power_supplyhttps://en.wikipedia.org/wiki/Power_supplyhttps://en.wikipedia.org/wiki/Power_supplyhttps://en.wikipedia.org/wiki/Transistor-transistor_logichttps://en.wikipedia.org/wiki/Transistor-transistor_logichttps://en.wikipedia.org/wiki/Hysteresishttps://en.wikipedia.org/wiki/Hysteresishttps://en.wikipedia.org/wiki/Charge_pumphttps://en.wikipedia.org/wiki/Power_supplyhttps://en.wikipedia.org/wiki/Transistor-transistor_logichttps://en.wikipedia.org/wiki/Hysteresis


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SEEN SE7+EN4 DISP.!#

!n .ED or .i%ht Emittin% Diode9 i* a *olid *tate optical PN&:unction diode ;hich emit* li%ht ener%y

in the form of ia*ed >y a volta%e allo;in% current to flo; acro** it* :unction9

and in Electronic* ;e call thi* proce** electrolumine*cence,

7he actual colour of the 9isible light emitted by an G2D, ranging from blue to red to orange, is decided by the

spectral wa9elength of the emitted light which itself is dependent upon the mixture of the 9arious impurities added

to the semiconductor materials used to produce it6

&*e%ment Di*play

Gight 2mitting Diodesha9e many ad9antages o9er traditional bulbs and lamps, with the main ones being their small

si%e, long life, 9arious colours, cheapness and are readily a9ailable, as well as being easy to interface with 9arious

other electronic components and digital circuits6


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segment forms part of a numerical digit /both Decimal and $ex1 to be displayed6 An additional (th G2D is

sometimes used within the same pac&age thus allowing the indication of a decimal point, /D1 when two or more -

segment displays are connected together to display numbers greater than ten6

2ach one of the se9en G2Ds in the display is gi9en a positional segment with one of its connection pins being

brought straight out of the rectangular plastic pac&age6 7hese indi9idually G2D pins are labelled from athrough

to grepresenting each indi9idual G2D6 7he other G2D pins are connected together and wired to form a common pin6

8o by forward biasing the appropriate pins of the G2D segments in a particular order, some segments will be light

and others will be dar& allowing the desired character pattern of the number to be generated on the display6 7his then

allows us to display each of the ten decimal digits "through to ;on the same -segment display6

7he displays common pin is generally used to identify which type of -segment display it is6 As each G2D has two

connecting pins, one called the IAnodeJ and the other called the ICathodeJ, there are therefore two types of G2D -

segment display called: Common Cathode/CC1 and Common !node/CA16

7he difference between the two displays, as their name suggests, is that the common cathode has all the cathodes of

the -segments connected directly together and the common anode has all the anodes of the -segments connectedtogether and is illuminated as follows6

*6 7he Common Cathode /CC1 4n the common cathode display, all the cathode connections of the G2D segments

are oined together to logic I"J or ground6 7he indi9idual segments are illuminated by application of a I$4L$J, or

logic I*J signal 9ia a current limiting resistor to forward bias the indi9idual Anode terminals /a-g16

Common Cathode 7-segment Display

!6 7he Common Anode /CA1 4n the common anode display, all the anode connections of the G2D segments are

oined together to logic I*J6 7he indi9idual segments are illuminated by applying a ground, logic I"J or IGOJ

signal 9ia a suitable current limiting resistor to the Cathode of the particular segment /a-g16

Common Anode 7-segment Display


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4n general, common anode displays are more popular as many logic circuits can sin& more current than they can

source6 Also note that a common cathode display is not a direct replacement in a circuit for a common anode display

and 9ice 9ersa, as it is the same as connecting the G2Ds in re9erse, and hence light emission will not ta&e place6

Depending upon the decimal digit to be displayed, the particular set of G2Ds is forward biased6 or instance, to

display the numerical digit ", we will need to light up six of the G2D segments corresponding to a, b, c, d, eand f6

7hen the 9arious digits from "through ;can be displayed using a -segment display as shown6

-8egment Display 8egments for all @umbers6

7hen for a -segment display, we can produce a truth table gi9ing the indi9idual segments that need to be

illuminated in order to produce the reBuired decimal digit from "through ;as shown below6

7-segment Display Truth Table

Decimal

Di%it

Individual Se%ment* Illuminated

a > c d e f %

" M M M M M M

* M M

! M M M M M

3 M M M M M


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+ M M M M

5 M M M M M

. M M M M M M

M M M

( M M M M M M M

; M M M M M

Dri9ing a -segment Display

Although a -segment display can be thought of as a single display, it is still se9en indi9idual G2Ds within a single

pac&age and as such these G2Ds need protection from o9er current6 G2Ds produce light only when it is forward

biased with the amount of light emitted being proportional to the forward current6

7his means then that an G2Ds light intensity increases in an approximately linear manner with an increasing current6

8o this forward current must be controlled and limited to a safe 9alue by an external resistor to pre9ent damage to

the G2D segments6

7he forward 9oltage drop across a red G2D segment is 9ery low at about !-to-!6! 9olts, /blue and white G2Ds can

be as high as 36. 9olts1 so to illuminate correctly, the G2D segments should be connected to a 9oltage source in

excess of this forward 9oltage 9alue with a series resistance used to limit the forward current to a desirable 9alue6

7ypically for a standard red coloured -segment display, each G2D segment can draw about *5 mA to illuminated

correctly, so on a 5 9olt digital logic circuit, the 9alue of the current limiting resistor would be about !""] /59

!91*5mA, or !!"] to the nearest higher preferred 9alue6

8o to understand how the segments of the display are connected to a !!"]current limiting resistor consider the

circuit below6

Driving a 7-segment Display


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4n this example, the segments of a common anode display are illuminated using the switches6 4f switch ais closed,

current will flow through the IaJ segmentof the G2D to the current limiting resistor connected to pin aand to "

9olts, ma&ing the circuit6 7hen only segment awill be illuminated6 8o a GO condition /switch to ground1 is

reBuired to acti9ate the G2D segments on this common anode display6


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4n this simple circuit, each G2D segment of the common cathode display has its own anode terminal connected

directly to the +5** dri9er with its cathodes connected to ground6 7he current from each output passes through a

*&] resistor that limits it to a safe amount6 7he binary input to the +5** is 9ia the four switches6 7hen we can see

that using a

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