Strasbourg, France, 17 December, 2004, seminair

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Grzegorz DEPTUCH

MAPS technology

decoupled charge sensing and signal transfer (improved radiation tolerance, random access, etc.), small pitch (high tracking precision), low amount of material, fast readout, moderate price, SoC, etc.

advantages:

P + + S U B S T R AT E

P E P I-L A Y E R

c h a r g e s h a re d b e tw ee n n e i g h b o u r i n g p i x e l s

ch a r ge co l lec t ed e n t ire l y

b y o n e pi x e ls

P W E L L

N +N +N +

N W E L L

D E P L E T IO N

Z O N E

PA SS IVAT IO N

O X ID E

I N C ID EN T P H O TO N S

h

h

P + + S U B S T R AT E

P E P I-L A Y E R

c h a r g e s h a re d b e tw ee n n e i g h b o u r i n g p i x e l s

ch a r ge co l lec t ed e n t ire l y

b y o n e pi x e ls

P W E L L

N +N +N +

N W E L L

D E P L E T IO N

Z O N E

PA SS IVAT IO N

O X ID E

I N C ID EN T P H O TO N S

h

h

MIMOSA V 1×106 pixelsmicro-photograph

R E S _ E L

g n d

v d d v d d

M 1

M 1 - r e s e t t r a n s i s t o r

M 2 - s o u r c e f o l lo w e r

M 3 - r o w s w it c h

M 2

M 3

R O W _ S E L

C O L U M N

L I N E

R E S _ E L

g n d

v d d v d d

M 1

M 1 - r e s e t t r a n s i s t o r

M 2 - s o u r c e f o l lo w e r

M 3 - r o w s w it c h

M 2

M 3

R O W _ S E L

C O L U M N

L I N E

Strasbourg, France, 17 December, 2004, seminair

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Grzegorz DEPTUCH

MIMOSA V 1×106 pixel device

0.6 µm CMOS process with 14 µm epitaxial layer, 4 matrices of 512 × 512 pixels read-out in parallel;

pixel: 17 × 17 µm2, diodes: P1 - 9.6 pm2, P2 - 24.0 pm2, control logic and all pads aligned along one side,

results:Noise mean ENC: 20.74 e-

detection efficiency MIPs (): 99.3%

spatial resolution MIPs (): 1.7 µm

pixel-pixel gain nonuiformity ~3%

MIMOSA V

Chip-Detector design

MIMOSA = Minimum Ionising Particle MOS APS

3T design

Chip design not optimised for any particular application, aimed at relativistic charged particle detection - DESIGNED in joined IReS-LEPSI effort in 2001

Strasbourg, France, 17 December, 2004, seminair

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Grzegorz DEPTUCH

Architecture of the prototype

Matrix of sequentially addressed pixels, multiplexed on single output buffer.

MIMOSA V 1×106 pixel device

Strasbourg, France, 17 December, 2004, seminair

- - 44 - -

Grzegorz DEPTUCH

MIMOSA V 1×106 pixel device Default Readout Method

Readout time = Integration time ~8 ms @ 40 MHz fclk.

Strasbourg, France, 17 December, 2004, seminair

- - 55 - -

Grzegorz DEPTUCH

back-s

ide illu

min

ate

d M

IMO

SA

V –

f

ab

ricati

on

Strasbourg, France, 17 December, 2004, seminair

- - 66 - -

Grzegorz DEPTUCH

back-side illuminated MIMOSA V - mountingBack-side illuminated thinned M5 device – a test vehicle for demonstration of 20 keV E- detection capability for Beam Monitoring system and other affined applications• Bonding pads 85×85 µm2 inside 10 µm deep wells

• positive response from microbonding sa - idea of use Au ball-bonding technique – not successful because of pad cratering

• finally 17 µm Al wedge bonding with special deep wedge was used