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LECTURE BY:

SRIKANTH JADCHERLA

Slides rendered by

P.SNIGDHA

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Does the design

meet a given

timing

requirement?!! How fast can I run

the design?!!!

Static Timing analysis is a technique usedin digital circuit design to analyse if the

circuit will satisfy timing constraints.

Timing closure refers to a set ofoptimization techniques which modify the

circuit layout to meet the

defined performance goals.

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Library elements and timing representation. Libertyformat

Definition of timing paths

Setup Hold

PVT (revision)

Latch vs. register timing Clock latency and skew

(clock uncertaintyskew, jitter)

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Format of the library is liberty - .lib

Library elements will have various attributes

connection details , properties of the cell(name , area, pins , maximum capacitance,

maximum fan-out ,timing tables.. )

For example:

Pin names, capacitance,

Input slopes Vs. Propagation delays etc.,

A C

B

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Varying slopes

Different loads:

(small (large

Capacitance) Capacitance)

Hence propagation slopes will vary according to the slopes and loads

Therefore inputs A and B will have different loads and transition

slopes.

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NON LINEAR DELAY MODEL

The loads and slopes are represented using Non-Linear-Delay-Models or

Composite Current Source Models.

NLDMs use Look Up Tables(LUT) consisting of different load values,rise time values, fall time values etc.,

NLDMs are alone not sufficient. Timing requires functionality.

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Why the timing needs functionality??

In the above example:

Timing arc for a given rise or fall times at A and for a given

load at C, NLDM gives rise or fall times at C indirectly the

transition time from A to C.

Transition over input has an effect on output. This is called

transition delay.Sometimes it is not necessary. For example:

LOGIC ZERO

A shows continuous transitions and B holds a value of zero

so the output always remains zero. No timing is required.

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Timing must know the logic of the cells.

Timing path can be defined as the propagation of the change at an

input pin to an output pin.

Every path operates with a clock and/or similar constraint.

So generalising a circuit different timing paths would be:

Three flip-flops resulting in four timing paths

Ff/latch/

primary

Input

ff

ff

gate gate

gateClk

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CONTINUED..

So the path starts at the source and propagates to the sink.

The source can be a flip-flop, a latch, primary input, hard macro input.

The sink can be a flip-flop or a latch, data pins, hard macro input,

primary output.

The rest of them would include propagation path.

In the previous example the gates form the propagation path.

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Ff/latch/

primary

Input

gate gateFf/latch/

primary

InputC1

C2

Launch

edge of flip-

flop

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The delays associated must be in such a way that data has to go out of the

flop propagate through this and be ready in time with the clock.

NOTE: In the same clock how is it going??

Each pulse reaches C1 to C2.

So the following inequality may be derived.

Flip-flop internal delay should not be confused with path set up delay.

Both are different.Data has to travel from source to sink within the

Q1 + (D1 + D2) + SETUP TIME

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When there is a launch of data propagating and set up amounts to a

period where the data must be ready i.e.,

After the time d2(delay of last gate) by the time the you through thisperiod data must be propagated through d2 and data ready for the

capture while 2nd flip-flop. This is actually the set up time.

CONTINUED

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:

Now if the flip-flops are connected back to back???

Here data for the next flip flop will be launched and captured at the

same edge . The inequality condition would be

Ff/latch/

primary

Input

Ff/latch/

primary

Input

Q1(CLOCK TO FLOP DELAY) + C1

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As soon as the launch data before launch edge reaches C2 it will actually

hit flip-flop2 and registered as next gate.

Data moves one cycle!!! Difficult to debug.

How to reduce the problem??Place hold tick buffers to increase the delay:

This delays the capture event

Q1 + C1 + TBUF

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SUMMARY OF SET UP AND HOLD TIME

SET UP HOLDTIME

(Source launches) (Sink captures)

L1 to C1 L1 to C0L2 to C2 L2 to C1

L3 to C3 L3 to C2

L1 C1 C2

C0 L2 L3

tsup th

Period of stability before clock edge

is set up and after clock is hold.

To avoid problem data must be stable

Before tsup of clock and after th

of the clock

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Variation in propagation of clock from C1 to C2 can help or damage. This

is called uncertainty. And the difference between C1 and C2 is the

actual skew.

Uncertainty is to be considered during synthesis /placement-Routing.

Why????

Before clock tree synthesis or before we actually place buffers into end

points the difference between C1 & C2 is not known. So uncertainty is

the constraint during synthesis.

UNCERTAINTY = JITTER + SKEW + MARGIN + SOME OTHER VARIATIONS.

Generally clocks are produced by PLL.

Eg: If u have 10ns of clock u would get only 9.9 or 10.1ns. The 0.1ns is the

variation.

This is termed as Jitter

CLOCK UNCERTAINTY SKEW AND JITTER

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WHAT IS SKEW???

Actual Clock Skew is the maximum difference in latency to the clock

end points .

NOTE: The actual concept of finding maximum number and median

out of million random numbers is useful here.

FF

FF

FF

FF

FF

Clockpin

As the design increases the difference has to be computed.

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Consider an example:

If there was a class to attend and if the student is late by2min then he will miss the class where as if it was the lecturer

who is late then there is no problem.

Comparing this with launch and capture paths. If the launch

path is running late then there would be a problem

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EXAMPLE IN THE CASE OF CIRCUITS

In the above example if C1 is increasing the amount of time

available for setup increases. If C2 increases the amount of

time available for setup decreases.

That is why if there is clock period of 10ns Vs. 11ns, for 11ns

Timing would be easier. So as clock period increases timing

becomes easier

Ff/latch/

primary

Input

Ff/latch/

primary

Input

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PROCESS VOLTAGE TEMPERATURE

How does the set up and hold time vary with PVT???

Conditions Process Voltage Temp

Effect on setup and

hold times.

SLOW P V TSet up time becomes

worst. Propagation

delay increases

Less hold violations.

TYPICAL P V TTypical set up and hold

times

FAST P V T

Hold time becomes

worst. Propagation

delay decreases

Less setup violations.

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LATCH UP Vs. REGISTER TIMING

Register latchCLK Enable

Basically Involves Non blocking Involves Blocking

Assignments. Assignments.

Reflection of setup and the No set up and

behaviour of the elements. reflection behaviour

Samples by capture edge.Sequential logics use registers Combination logics

use latches

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