ST17H30Q 15W SoC for Wireless Power Transmitter with built ...€¦ · 2017/2 Cynthia 2.6.0 Updated...

ST17H30Q15WSoCforWirelessPowerTransmitterwith Built-inBluetooth-LE DS-ST17H30Q-E15 Ver 2.7.0

2017/6/15

LENZE TECH

NO

LOG

Y

Keyword:

Features;Package;Pinlayout;Memory;MCU;

Workingmode;Wakeupsource;RFTransceiver;

Baseband;Clock;Timers;Interrupt;Interface;

QDEC;ADC;PWM;Electricalspecification;Application

Brief:

This datasheet is dedicated for Lenze Wireless Power

Transmitter, supported WPC1.2.4 Certificate, low cost

BLE+2.4G dualmode SoC ST17H30Q. In this datasheet,

key features, working modes, main modules, electrical

specification and application of the ST17H30 are

introduced.

Datasheet for Lenze ST17H30Q

DS-ST17H30Q-E15 1 Ver2.4.0

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DS-ST17H30Q-E15 2 Ver2.4.0

RevisionHistory

Version MajorChanges Date Author

1.0 Initialrelease 2015/4 S.G.J.,Y.C.Q,F.F.,L.Y.,Cynthia

1.1.0

Updatedpackagedimensionfigure(Figure1-2insection1.5),andsection1.2.2~1.2.3,12.3~12.4

2015/6 X.S.J.,L.Y.,Cynthia

1.2.0

Addedorderinginformation,packagedimension,pinlayout,GPIOlookuptables,pull-up/pull-downresistorandschematicforSOP16package;

UpdatedGP4&GP5pinmultiplexedfunction(I2C)forQFN24package.

2015/7S.G.J.,L.X.,H.Z.F.,X.S.J.,L.Y.,

Cynthia

1.3.0AddedIOdrivestrengthinformation

2015/7 L.Y.,Cynthia

1.4.0AddedTSSOP16packageinformation

2015/8 X.S.J.,L.Y.,Cynthia

1.5.0 DeletedIRmode 2015/10 L.Y.,Cynthia

1.6.0 DeletedSOP16package 2015/12 L.Y.,Cynthia

1.7.0UpdatedconnectionrelationshipbetweenGPIOandrelatedmodules.

2016/2 S.G.J.,Cynthia

1.8.0

AddedeSOP8 packageinformation;

AddedreferencedesignforST17H30QES16.

2016/3 X.X.,X.S.J.,L.X.,Cynthia

1.9.0UpdatedreferencedesignforST17H30QET24,ST17H30QES16andST17H30QEP8

2016/3 H.Z.F.,L.X.,Cynthia

2.0.0UpdatedDCcharacteristicsandorderinginformation.

2016/7 L.J.R.,X.S.J.,Cynthia

2.1.0UpdatedpackagedimensionfortheST17H30QES16

2016/7 X.S.J.,Cynthia

2.2.0 Updatedregisterconfigurationto 2016/10 Z.J.Q.,Cynthia


DS-ST17H30Q-E15 3 Ver2.4.0

Version MajorChanges Date Author

selectVGP23or1/3*VGP23asADCinput:digitalregister0x2c[2:0],andanalogregisterafe3V_reg02<3>.

2.3.0 UpdatedWPC1.2.supported 2016/11 C.K.X.,Cynthia

2.4.0Updated3.3Vanalogregistertable(3v_reg12~3v_reg45)

2016/12 C.K.X.,Cynthia

2.5.0OfficialversionforST17H30QET24

2017/2 Cynthia

2.6.0 UpdatedWPC1.2.3supported 2017/5 Billy

2.7.0UpdatedWPC1.2.4supported,updatedEPP(MP-A11)supported

2018/3 Billy


DS-ST17H30Q-E15 4 Ver2.4.0

1 Tableofcontents

1 Overview.............................................................................................................101.1 Blockdiagram.............................................................................................101.2 Keyfeatures................................................................................................11

1.2.1 Generalfeatures....................................................................................11

1.2.2 RFFeatures............................................................................................12

1.2.3 Featuresofpowermanagementmodule..............................................12

1.3 Typicalapplication......................................................................................131.4 Orderinginformation.................................................................................131.5 Package.......................................................................................................131.6 Pinlayout....................................................................................................151.7 LenzeSDK...................................................................................................17

2 Memory..............................................................................................................173 MCU..................................................................................................................183.1 Workingmodes..........................................................................................18

3.1.1 Activemode...........................................................................................19

3.1.2 Idlemode...............................................................................................19

3.1.3 Power-savingmode...............................................................................19

3.1.3.1 Briefintroduction.............................................................................193.1.3.2 Registerconfigurationofpower-savingmode..................................203.1.3.3 Wakeupsource.................................................................................24

3.1.3.3.1 Wakeupsource–GPIO.................................................................243.1.3.3.2 Wakeupsource–QDEC................................................................243.1.3.3.3 Wakeupsource–32Ktimer..........................................................243.1.3.3.4 Wakeupsource–pad....................................................................24

3.1.3.4 Transitionsequence..........................................................................253.2 Reset...........................................................................................................26

4 2.4GRFTransceiver............................................................................................274.1 Blockdiagram.............................................................................................274.2 Functiondescription...................................................................................284.3 Baseband....................................................................................................28

4.3.1 Packetformat........................................................................................28

4.3.2 RSSI........................................................................................................28

5 Clock....................................................................................................................28


DS-ST17H30Q-E15 5 Ver2.4.0

5.1 Systemclock...............................................................................................29

5.1.1 Systemclocksources.............................................................................29

5.1.2 FHSselect..............................................................................................30

5.1.3 HSdividerclock.....................................................................................30

5.2 Moduleclock..............................................................................................30

5.2.1 SARADCclock........................................................................................30

5.3 Registertable.............................................................................................306 Timers.................................................................................................................326.1 Timer0~Timer2...........................................................................................32

6.1.1 Registertable........................................................................................32

6.1.2 Mode0(SystemClockMode)................................................................34

6.1.3 Mode1(GPIOTriggerMode).................................................................35

6.1.4 Mode2(GPIOPulseWidthMode).........................................................36

6.1.5 Mode3(TickMode)...............................................................................37

6.1.6 Watchdog..............................................................................................37

6.2 32KLTIMER.................................................................................................386.3 Systemtimer..............................................................................................39

7 InterruptSystem.................................................................................................407.1 Interruptstructure.....................................................................................407.2 Registerconfiguration................................................................................40

7.2.1 Enable/Maskinterruptsources.............................................................41

7.2.2 Interruptmodeandpriority..................................................................41

7.2.3 Interruptsourceflag..............................................................................42

8 Interface..............................................................................................................428.1 GPIO...........................................................................................................42

8.1.1 Basicconfiguration................................................................................43

8.1.1.1 Multiplexedfunctions.......................................................................438.1.1.2 Drivestrength...................................................................................45

8.1.2 ConnectionrelationshipbetweenGPIOandrelatedmodules..............46

8.2 I2C...............................................................................................................49

8.2.1 Pinconfiguration...................................................................................49

8.2.2 LenzeI2Ccommunicationprotocol.......................................................49

8.2.3 Registertable........................................................................................50


DS-ST17H30Q-E15 6 Ver2.4.0

8.2.4 I2CSlavemode......................................................................................51

8.2.4.1DMAmode...........................................................................................528.2.4.2Mappingmode.....................................................................................538.2.4.3Commandanalysismode.....................................................................53

8.3 SWS............................................................................................................548.4 Pull-up/Pull-downresistor..........................................................................54

9 QuadratureDecoder...........................................................................................569.1 Inputpinselection......................................................................................569.2 Commonmodeanddoubleaccuracymode...............................................569.3 Readrealtimecountingvalue....................................................................589.4 QDECinterrupt...........................................................................................599.5 QDECreset.................................................................................................599.6 Otherconfiguration....................................................................................599.7 Registertable.............................................................................................60

10 SARADC..............................................................................................................6110.1 Registertable...............................................................................................6110.2 SARADCclock...............................................................................................6210.3 SelectADCrange,resolutionandsamplingtime.........................................6210.4 Selectinputmodeandchannel....................................................................6310.5 ADCstart......................................................................................................6310.6 ADCstatus....................................................................................................6310.7 ADCdata.......................................................................................................64

11 PWM...................................................................................................................6411.1 Registertable...............................................................................................6411.2 EnablePWM.................................................................................................6611.3 SetPWMclock..............................................................................................6611.4 PWMwaveform,polarityandoutputinversion...........................................66

11.4.1 PWMwaveform.....................................................................................67

11.4.2 InvertPWMoutput...............................................................................67

11.4.3 Polarityforsignalframe........................................................................67

11.5 PWMmode..................................................................................................68

11.5.1 SelectPWMmode.................................................................................68

11.5.2 Continuousmode..................................................................................68

11.5.3 Countingmode......................................................................................69

11.6 PWMinterrupt.............................................................................................6912 KeyElectricalSpecifications................................................................................6912.1 Absolutemaximumratings..........................................................................69


DS-ST17H30Q-E15 7 Ver2.4.0

12.2 Recommendedoperatingcondition.............................................................7012.3 DCcharacteristics.........................................................................................7012.4 ACcharacteristics.........................................................................................71

13 Application..........................................................................................................7513.1 ApplicationexamplefortheST17H30QET24...............................................75

13.1.1 Schematic..............................................................................................75

13.1.2 Layout....................................................................................................77

13.1.3 BOM(BillofMaterial)............................................................................77


DS-ST17H30Q-E15 8 Ver2.4.0

2 TableofFiguresFigure1-1 Blockdiagramofthesystem.............................................................11Figure1-2 PackagedimensionfortheST17H30QET24(Unit:mm)...................14Figure1-3 PinassignmentfortheST17H30QET24............................................15Figure2-1 Physicalmemorymap.......................................................................17Figure2-2 MCUmemorymap...........................................................................18Figure3-1 Blockdiagram...................................................................................18Figure3-2 Transitionchartofworkingmodes...................................................19Figure3-3 Wakeupsource.................................................................................25Figure4-1 BlockdiagramofRFtransceiver.......................................................27Figure5-1 Blockdiagramofsystemclock..........................................................29Figure8-1 LogicrelationshipbetweenGPIOandrelatedmodules...................47Figure8-2 I2Ctimingchart................................................................................50Figure8-3 I2Cslaveaddress..............................................................................52Figure8-4 ReadformatinI2CDMAmode.........................................................52Figure8-5 WriteformatinI2CDMAmode........................................................53Figure8-6 ReadformatinI2CMappingmode...................................................53Figure8-7 WriteformatinI2CMappingmode..................................................53Figure9-1 Commonmode.................................................................................57Figure9-2 Doubleaccuracymode.....................................................................58Figure9-3 Readrealtimecountingvalue..........................................................59Figure9-4 Shuttlemode....................................................................................60Figure11-1PWMoutputwaveformchart...........................................................68Figure11-2Continuousmode.............................................................................68Figure11-3Countingmode.................................................................................69Figure13-1SchematicfortheST17H30QET24....................................................76Figure13-2LayoutfortheST17H30QET24..........................................................77


DS-ST17H30Q-E15 9 Ver2.4.0

3 TableofTables

Table1-1 OrderinginformationoftheST17H30Q...........................................13Table1-2 PinfunctionsfortheST17H30QET24...............................................15Table3-1 Registersindigitalcore.....................................................................20Table3-2 3.3Vanalogregisters(afe3V_reg05~afe3V_reg06)(bit).................20Table3-3 3.3Vanalogregisters(3v_reg12~3v_reg45)...................................22Table3-4 Registerconfigurationforreset,wakeupandpowerdownenabling26Table4-1 PacketFormat...................................................................................28Table5-1 Registertableforclock.....................................................................30Table6-1 RegisterconfigurationforTimer0~Timer2.......................................32Table6-2 3.3VanalogregistertableforLTIMER..............................................39Table6-3 RegistertableforSystemTimer........................................................40Table7-1 RegistertableforInterruptsystem...................................................40Table8-1 GPIOlookuptable1fortheST17H30QET24....................................43Table8-2 IOdrivestrengthforST17H30QET24................................................45Table8-3 GPIOlookuptable2fortheST17H30QET24....................................48Table8-4 I2Cpinconfiguration........................................................................49Table8-5 RegistertableforI2C........................................................................50Table8-6 3.3VanalogregistersrelatedtoPull-up/Pull-downresistor.............54Table9-1 Inputpinselection............................................................................56Table9-2 RegistertableforQDEC....................................................................60Table10-1 RegistertableforSARADC...............................................................61Table11-1 RegistertableforPWM....................................................................64Table12-1 AbsoluteMaximumRatings..............................................................69Table12-2 Recommendedoperationcondition.................................................70Table12-3 DCcharacteristics.............................................................................70Table12-4 ACCharacteristics.............................................................................71Table13-1 BOMtablefortheST17H30QET24...................................................77


DS-ST17H30Q-E15 10 Ver2.4.0

1 Overview

TheST17H30QisLenze-developedwirelesspowertransmitter,supportWPC1.2.4

standard, single coil quick charge transmission, compliant all kinds of receiving

equipmentof internationalwirelesschargingstandard,suchassmartphones,smart

watches,anti-corrosionandIoTproducts,powerinputsupportQC2.0/QC3.0adapter.

ultra-lowcostBLEand2.4GdualmodeSoCsolutionwhichisfullystandardcompliant

and allows easy connectivity with Bluetooth Smart Ready mobile phones, tablets,

laptops.It’scompletelyRoHS-compliantand100%lead(Pb)-free.

1.1 Blockdiagram

TheST17H30Qisdesignedtoofferultra-lowcost,highefficiencywirelesspower

transmitter, low power Bluetooth Smart application capabilities, which integrates

powerful32-bitMCU,advancedBLE/2.4GRadio,16KBon-chipOTP,6KBon-chipSRAM,

a 10bit ADC, a quadrature decoder (QDEC), up to four-channel PWM, flexible I/O

interfaces, andnearly all of theperipheral blocksneeded forBluetooth LowEnergy

applicationsdevelopment.

Thesystem’sblockdiagramisasshowninFigure1-1:

RISC32bitMCU

Timer0/1/2WatchdogGPIO

SWS

RESET

POWER-ONRESET

LDO

POWERManagementControllerBROWNOUT

BLE/2.4GRFTransceiver

POWERMANAGEMENT

I2CSlave

1QuadratureDecoder

16KBOTP6KBSRAM

16/12MHzCrystal,32MHz/32KHzRC

Oscillator

32KLTIMER

DMA

Clock

Memory

MSPI

PWM

10bitADC


DS-ST17H30Q-E15 11 Ver2.4.0

Figure1-1 Blockdiagramofthesystem

Based on the ST17H30Qwith high-volume-assembly and high integration, few

externalcomponentsareneededtosatisfycustomers’ultra-lowcostrequirement.

1.2 Keyfeatures

1.2.1 Generalfeatures

Generalfeaturesareasfollows:

1) CompatiblewithWPC1.2/WPC1.2.3/WPC1.2.4standard

2) Metalobjectdetection(FOD)

3) Compatiblewith 15W/10W/5W(including Apple 7.5W fast charging), Automatic

detecttosetoutputpower

4) CompatiblewithAppleWatchchargeStandard(350mAchargingcurrent)

5) Conversionefficiency85%

6) Detectiondistance:0~10mm

7) Modulationmethod:ASK/FSK2-Way

8) Embed32-bitARMcortexM3highperformanceMCUwithclockupto48MHz.

9) Programmemory:16KBon-chipOTP.

10) Datamemory:6KBon-chipSRAM.

11) 16/12MHzCrystaland32KHz/32MHzembeddedRCoscillator.

12) Upto14GPIOsdependingonpackageoption,withconfigurableinternalpull-up

orpull-downresistors.

13) Debuginterface:SWS(SingleWireSlave).

14) SupportsMSPIandI2CSlaveinterface.

15) EmbedsaSARADC:Upto10bitresolutionand4inputchannels.

16) Embedsonequadraturedecoder(QDEC).

17) Supportsuptofour-channelPWMoutput.

18) Embedsthreegeneral32-bittimersTimer0~Timer2.

² Timer0~Timer2areavailableinactivemode

² Timer0~Timer1supportsfourmodes


DS-ST17H30Q-E15 12 Ver2.4.0

² GenerallyTimer2isprogrammableaswatchdog

19) A low-frequency 32K timer LTIMER available in suspend mode or deep sleep

mode.

20) Operatingtemperature:-40℃~+85℃ industrialtemperaturerange.

1.2.2 RFFeatures

RFfeaturesinclude:

1) BLE/2.4GHz RF transceiver embedded, working in worldwide 2.4GHz ISM

band.

2) Adaptivefrequencyhopping.

3) Bluetooth4.0Compliant,1Mbpsdataratemode.

4) RxSensitivity:-94dBmat1Mbpsmode.

5) Txoutputpowerupto+6dBm.

6) Autoacknowledgementandretry.

7) Single-pinantennainterface.

8) RSSImonitoring.

1.2.3 Featuresofpowermanagementmodule

Featuresofpowermanagementmoduleinclude:

1) Powersupplyof1.9V~3.6V.

2) EmbeddedLDO.

3) Batterymonitor:Embeddedlowbatterydetection.

4) Multiplestagepowermanagementtominimizepowerconsumption.

5) Lowpowerconsumption:

² Transmittermodecurrent:15mA@0dBmpower,22mA@maxpower

² Receivermodecurrent:12mA

² Suspendmodecurrent:10uA

² Deepsleepmodecurrent:0.7uA


DS-ST17H30Q-E15 13 Ver2.4.0

1.3 Typicalapplication

TheST17H30QistypicallyusedforBLE(BluetoothLowEnergy)applications.

² WirelessCharger

² Beacon

² FindMe

² SelfieShutter

1.4 Orderinginformation

Table1-1 OrderinginformationoftheST17H30Q

ProductPackage

Type

Temperature

Range

Package

Marking

Packing

Method

Ordering

Number

Minimum

OrderQuantity

ST17H30Q

24-pin

4X4mm

TQFN

-40℃ ~+85℃ ST17H30QET24 TR ST17H30QET24R 3000

*Note:Packingmethod“TR”meanstapeandreel.

1.5 Package

PackagedimensionfortheST17H30QET24isshownasFigure1-2.


DS-ST17H30Q-E15 14 Ver2.4.0

Figure1-2 PackagedimensionfortheST17H30QET24(Unit:mm)


DS-ST17H30Q-E15 15 Ver2.4.0

1.6 Pinlayout

PinassignmentfortheST17H30QET24isasshowninFigure1-3:

Figure1-3 PinassignmentfortheST17H30QET24

Functionsof24pinsfortheST17H30QET24aredescribedinTable1-2:

Table1-2 PinfunctionsfortheST17H30QET24

QFN24 4X4

No. Pin Name Pin Type Description

1 MSDO Digital I/O Memory SPI data output/GPIO

2 MSDI Digital I/O Memory SPI data input/GPIO

3 MSCN Digital I/O Memory SPI chip-select(Active

low)/GPIO

4 SWS Digital I/O single wire slave/GPIO

5 GP9/pwm0 # Digital I/O GPIO9/PWM0 output


DS-ST17H30Q-E15 16 Ver2.4.0

QFN24 4X4

No. Pin Name Pin Type Description

6 GP10/pwm1 # Digital I/O GPIO10/PWM1 output

7 VPP6P75V POWER for OTP program 6.75V power supply

8 DVDD3 PWR 3.3V IO supply

9 DVSS GND Digital LDO ground

10 VDDDEC PWR Digital LDO 1.8V output

11 GP17/pwm2_inv/ANA0 * Digital I/O GPIO17/PWM2 inverting

output/Analog input 0 for SAR ADC

12 GP18/ANA1 * Digital I/O GPIO18/Analog input 1 for SAR ADC

13 GP22/scl/ANA2 * Digital I/O GPIO22/I2C_SCL/Analog input 2 for

SAR ADC

14 GP23/sda/ANA3 * Digital I/O GPIO23/I2C_SDA/Analog input 3 for

SAR ADC

15 XC1 Analog I/O 16MHz crystal input+

16 XC2 Analog I/O 16MHz crystal input-

17 AVDD3 PWR Analog 3.3V supply

18 GP30/scl Digital I/O GPIO30/I2C_SCL

19 GP31/sda * Digital I/O GPIO31/I2C_SDA

20 AVDD3 PWR RF 3.3V supply

21 ANT1 Analog I/O RF antenna

22 RESETB Digital I Power on reset, active low

23 GP5/sda/pwm2_inv/ pwm3 #

Digital I/O GPIO5/I2C_SDA (not

recommended)/PWM2 inverting output/PWM3 output

24 MCLK Digital I/O Memory SPI clock/GPIO

*Note: (1) Pins with bold typeface can be used as GPIOS. Please refer to Section 8.1 fordetails.(2)Thepinsmarkedwithanasterisksupportconfigurableinternal1MΩ/10KΩpull-upresistoror100KΩpull-downresistorwhicharedisabledbydefault.Thepinsmarkedwith a pound sign support internal 100KΩ pull-down resistor which is disabled bydefault.PleaserefertoSection8.4fordetailsaboutpull-up/pull-downresistor.(3)TheI2CinterfaceonlysupportsSlavemode.

(4)Pindrivestrength:AlltheGPIOpinssupportdrivestrengthof4mAor0.7mA(4mA


DS-ST17H30Q-E15 17 Ver2.4.0

when “DS”=1, 0.7mA when “DS”=0) with the following exceptions: MCLK, MSDO,MSDI andMSCN support drive strength of 4mA or 2mA (4mA when “DS”=1, 2mAwhen“DS”=0);SWSsupportsdrivestrengthof8mAor4mA(8mAwhen“DS”=1,4mAwhen “DS”=0). “DS” configuration will take effect when the pin is used as output.PleaserefertoSection8.1 GPIO for corresponding “DS” register address andthedefaultsetting.

1.7 LenzeSDK

AfullfeaturedSDKisprovidedwiththechipforBLEapplications.Thecustomer

caneasilydevelophisownBLEapplicationsbyemployingthefirmware,alongwith

thesystemconfigurationdatacomposedaccordingtothespecifichardwaredesign.

2 Memory

TheST17H30Qembeds6KBdatamemory (SRAM),and16KBprogrammemory

(OTP).

SRAM/Registermemorymapisshownasfollows:

0x808000

0x8097FF0x809800

6KB SRAM

0x807FFF

0x800000

Register

Figure2-1 Physicalmemorymap

Registeraddress:from0x800000to0x807FFF;

6KBSRAMaddress:from0x808000to0x809800.

Both register and 6KB SRAM address can be accessed via I2C Slave and SWS

interface.

OTP/Externalflashaddressmappingisconfigurable.


DS-ST17H30Q-E15 18 Ver2.4.0

OTP/external SPI FLASH

SRAM

0x0000

0x8000000x7FFFFF

IO

Configurable

0xFFFFFF

Figure2-2 MCUmemorymap

ExternalFLASHaddresscanbeaccessedviaMSPIinterface.

Addressspacestartingfrom0x800000canbeaccessedviadebuginterface.

3 MCU

TLRI SC32 Core

I nst ruct i on Cache Cont rol l er

16KB OTP

6KB SRAM

I nt errupt Cont rol l er

Ti mer 0/ 1/ 2Wat ch Dog

Level I nt errupt s

Edge I nt errupt s

I nst r uct i on Bus

Dat a Bus

SPI Fl ash

Regi st er Bus

GPI OsModul e Out pus

Figure3-1 Blockdiagram

TheST17H30Qintegratesapowerful32-bitMCUdevelopedbyLenze.Thedigital

core isbasedon32-bitRISC,andthe lengthof instructions is16bits; fourhardware

breakpointsaresupported.

3.1 Workingmodes

TheST17H30Qhas fourworkingmodes:Active, Idle, SuspendandDeepSleep.

Thissectionmainlygivesthedescriptionofeveryworkingmodeandmodetransition.


DS-ST17H30Q-E15 19 Ver2.4.0

Idle State

Suspend State

Active State

Deep Sleep State

Wakeup

Wakeup

Wakeup

Figure3-2 Transitionchartofworkingmodes

3.1.1 Activemode

In active mode, the MCU block is at working state, and the ST17H30Q can

transmitorreceivedataviaitsembeddedRFtransceiver.TheRFtransceivercanalso

bepowereddownifnodatatransferisneeded.

3.1.2 Idlemode

InIdlemode,theMCUblockstalls,andtheRFtransceivercanbeatworkingstate

or bepowereddown. The timeneeded for the transition from Idlemode toActive

modeisnegligible.

3.1.3 Power-savingmode

3.1.3.1 Briefintroduction

For theST17H30Q, thereare twokindsofpower-savingmodes:suspendmode

anddeepsleepmode.Thetwomodeshavesimilartransitionsequencesbutdifferent

register settings. For 1.8V digital core, it’s still providedwith theworking power by

1.8VLDOinsuspendmode;whileindeepsleepmode,the1.8VLDOwillbeturnedoff,

andthedigitalcoreispowereddown.

Insuspendmode,theRFtransceiverispowereddown,andtheclockoftheMCU

blockisstopped.Itonlytakesabout400usfortheST17H30Qtoentertheactivemode

fromsuspendmode.

While in deep sleep mode, both the RF transceiver and the MCU block are


DS-ST17H30Q-E15 20 Ver2.4.0

powereddownwithonlypowermanagementblockbeingactive.Thetransitiontime

neededfromdeepsleepmodetoactivemodeis1ms,almostthesameaspower-up

time.

3.1.3.2 Registerconfigurationofpower-savingmode

For the ST17H30Q, power-saving mode related registers are configurable via

digitalcoreand3.3Vanalogregisters.

Table3-1 Registersindigitalcore

Address Mnemonic Type Description Resetvalue

0x6e WAKEUPEN R/W

Wakeupenable[0]:enablei2cwakeupwhentransaction[1]:enableQDECwakeup[2]:rsvd[3]:enablewakeupfromgpio[4]: enable i2c wakeup when slave IDmatchedSystemresumecontrol[5]:enableGPIOremotewakeup[6]:rsvd

[7]sleepwakeupresetsystemenable

00

0x6f PWDNEN W

[0]:suspendenable[5]:rstall(actaspoweronreset)[6]:mculowpowermode[7]: stall mcu trig If bit[0] set 1, thensystemwill go to suspend.Or only stallmcu

Address0x6eservestoenablevariouswakeupsourcesfrompower-savingmode.

PleaserefertoSection3.1.3.3Wakeupsourcefordetails.

Table3-2 3.3Vanalogregisters(afe3V_reg05~afe3V_reg06)(bit)

Address(bit) MnemonicResetvalue

Description

afe3V_reg05<0> 32K_rc_pd 0Powerdown32KHzRCoscillator1:Powerdown32KHzRCoscillator0:Powerup32KHzRCoscillator


DS-ST17H30Q-E15 21 Ver2.4.0


Description

afe3V_reg05<1> reserved 0

afe3V_reg05<2> 32M_rc_pd 0Powerdownof32MHzRCoscillator 1:Powerdown32MHzRCoscillator0:Powerup32MHzRCoscillator

afe3V_reg05<3> xtal_LDO_pd 0Powerdownof16MHzcrystaloscillator1:Powerdown0:Powerup

afe3V_reg05<4> ldo_ana_pd 0PowerdownofanalogLDO1:Powerdown0:Powerup



afe3V_reg05<7> BBPLL_LDO_pd_3V 0PowerdownbasebandpllLDO1:Powerdown0:Powerup

afe3V_reg06<0> comp_pd 1PowerdownSARADC1:Powerdown0:Powerup

afe3V_reg06<1> rx_lnaLDO_pd 1PowerdownLNALDOinRFtransceiver1:Powerdown0:Powerup

afe3V_reg06<2> rx_anaLDO_pd 1PowerdownanalogLDOinRFtransceiver1:Powerdown0:Powerup

afe3V_reg06<3> rx_rfLDO_pd 1PowerdownRFLDOinRFtransceiver1:Powerdown0:Powerup

afe3V_reg06<4> pll_BG_pd 1PowerdownBandgapinPLL1:Powerdown0:Powerup

afe3V_reg06<5> reserved

afe3V_reg06<6> pll_vco_ldo_pd 1PowerdownVCOLDO1:Powerdown0:Powerup

afe3V_reg06<7> pll_cp_ldo_pd 1

Powerdowncpandprescaleranaogcircuitldo 1:Powerdown0:powerup


DS-ST17H30Q-E15 22 Ver2.4.0

Table3-3 3.3Vanalogregisters(3v_reg12~3v_reg45)

Addr Name Description

r12 0x0c bufferthisbufferwillberesetwhenwatchdogresetorwholechipreset(address0x6fwrite0x20)

r13 0x0d bufferthisbufferwillberesetwhenwatchdogresetorwholechipreset(address0x6fwrite0x20)

r14 0x0e bufferthisbufferwillberesetwhenwatchdogresetorwholechipreset(address0x6fwrite0x20)

r15 0x0f 32ktimer_cnt[7:0] 32ktimercnt[0]=1means4cyclesof32k r16 0x10 32ktimer_cnt[15:8] r17 0x11 32ktimer_cnt[23:16]

r180x12[0] 32ktimer_cnt[24] 0x12[1] 32ktimerenable 32ktimerenable

r190x13[6:0] r_dly

[6:0]wakeuporpowerondelayfordigitalLDOisready.

0x13[7] rsvd

r20

0x14[2:0] wd_v 32kwatchdogvalue 0x14[3] wd_en 32kwatchdogenable

0x14[7:4] pad_pol[3:0]padpolarity,onebitcontroltwopadwakeuppolarity.pad_pol[4]controlpad_wakeup_en[1:0].

r21

0x15[3:0] xtl_quick xtlquicksettle0xfmeansdisable

0x15[5:4] wd_wkup_srcwatchdogwakeupsourceselect[4];digwakeupsourceenablewatchdog.[5],padwakeupsourceenablewatchdog

0x15[7:6] rsvd r22 0x16 pad_wakeup_en [7:0]-->p_gpio[24:17].[0]-->p_gpio[17]

r23

0x17[2:0] wakeup_en[0]->digitalwakeupenable[1]-->32ktimerwakeupenable,[2]padwakeupenable

0x17[3] 32ktimerreset 0x17[4] rsvd 0x17[5] 32ktimerclockselect 0:32kosc,116Mxtl0x17[6] rsvd 0x17[7] rsvd

r24

0x18[0] pwdn_auto_en autopd32kosc enable0x18[1] rsvd 0x18[2] pwdn_auto_en autopd16mxtal enable

0x18[3] pwdn_auto_enautopdldo_ana,BBPLL_ldo,sar_adc,rx_lnaLDO,rx_anan_ldo,rx_rfLDO,pll_bg,pll_vco_ldo,pll_cp_ldo

0x18[4] pwdn_en powerdownsequenceenable


DS-ST17H30Q-E15 23 Ver2.4.0

Addr Name Description

0x18[5] pd_llkldo pdlowleakageldo0x18[6] pd_ldo_en pddigitalldoenable0x18[7] iso_en isolationenable

r25 0x19 buffer thisbufferwillberesetonlyatpoweronr26 0x1a buffer thisbufferwillberesetonlyatpoweronr27 0x1b buffer thisbufferwillberesetonlyatpoweronr28 0x1c buffer thisbufferwillberesetonlyatpoweron

0x1d~0x1f rsvd

r32 0x20 readonly32ktimer_cnt[7:0](1cycleof32kclockwillchangethereslult)

r33 0x21 readonly 32ktimer_cnt[15:8]r34 0x22 readonly 32ktimer_cnt[23:16]

r35

0x23[0] rsvd 0x23[1] w/r write1to cleantimerwakeupstatus.0x23[2] w/r write1tocleandigitalwakeupstatus0x23[3] w/r write1tocleanpadwakeupstatus0x23[4] wd_status write1to cleanwatchdogstatus.0x23[5] readonly rsvd0x23[6] readonly 32ktimer_cnt[24]

0x23[7] w/r32ktimerenabletogglesignal,write1toenable32ktimer

r36

0x24[0] trk32mmanulen 0x24[1] trk32men 0x24[2] trk32kmanulen 0x24[3] trk32ken 0x24[4] mode_12m 1,12Mxtal,0:16Mxtal0x24[7:3] rsvd

r37 0x25 trk32m_m_cap

r380x26[6:0] trk32k_m_cap 0x26[7] rsvd

r39 0x27 rsvd r40 0x28 r41 0x29 r42 0x2a

r430x2b[2:0] pad_wakeupen[10:8] [0]->p_gpio[26],[1]->p_gpio[27],[2]->p_gpio[31]0x2b[3] rsvd 0x2b[6:4] pad_pol[6:4] pad_pol[6:4]^pad_wakeup_en[10:8]

r44

32Mrccapvalue 32Mcalibrationreadonlyr45

32krccapvalue 32kcalibrationreadonly


DS-ST17H30Q-E15 24 Ver2.4.0

3.1.3.3 Wakeupsource

3.1.3.3.1 Wakeupsource–GPIO

Thiswakeupsourcecanonlywakeupthesystemfromsuspendmode.

First,settherightpolarityofIOviathe“Polarity”register(0x584,0x58c,0x594,

0x59c, 0x5a4). Polarity 1 indicates corresponding IO is active low,while 0 indicates

correspondingIOisactivehigh.

Second, set the right mask via the “Irq” register (0x587, 0x58f, 0x597, 0x59f,

0x5a7).1:enablethisIOaswakeupsource;0:disablethisIO.

Third,setboththedigitalcoreaddress0x6ebit[3]and3v_reg23bit[0]to1soas

toactivatethismode.

PleaserefertoSection8.1 GPIO for details about polarity and mask

registersofeachGPIO.

3.1.3.3.2 Wakeupsource–QDEC

Thiswakeupsourcecanonlywakeupthesystemfromsuspendmode.

First,digitalcoreaddress0x6e[1]shouldbesetto1b’1.

Second,address3V_reg23bit[0]shouldbesetto1b’1.

Third,addressesafe3V_reg05<0>and3V_reg24 [0]shouldbeclearedtopower

up32KRCclock,thenwrite0x64[7]and0x65[0]to1.

After this wakeup source is enabled, once there’s wheel rolling, squarewaves

outputaregeneratedandthesystemiswakened.

3.1.3.3.3 Wakeupsource–32Ktimer

Thiswakeupsource isabletowakeupthesystemfromsuspendmodeordeep

sleepmode.

Address3V_reg23bit[1]istheenablingbitforwakeupsourcefrom32ktimer.

3.1.3.3.4 Wakeupsource–pad

Thiswakeupsource isabletowakeupthesystemfromsuspendmodeordeep

sleepmode.

3v_reg23[2]shouldbesetto1b’1toenablepadwakeupsource.


DS-ST17H30Q-E15 25 Ver2.4.0

3v_reg22 and 3v_reg43[2:0] are enabling signal for pad wakeup sources:

3v_reg22bit[7:0]->[GP24~GP17];3v_reg43bit[2:0]->[GP31,GP27,GP26].1:enable

thisIOaswakeupsource;0:disablethisIO.

Polarity is controlled by 3v_reg20[7:4] and 3v_reg43[6:4]: 3v_reg43[6] controls

polarity of GP31, bit[5] controls polarity of GP27, bit[4] controls polarity of GP26;

3v_reg20bit[4] controlspolarityofGP17andGP18,bit[5] controlspolarityofGP19

andGP20,bit[6]controlspolarityofGP21andGP22,bit[7]controlspolarityofGP23

and GP24. Polarity 1 indicates corresponding IO is active low, while 0 indicates

correspondingIOisactivehigh.

3.1.3.4 Transitionsequence

First,enablethetargetwakeupsource,anddisableotherwakeupsources.

NOTE:Indeepsleepmode,thewakeup_dig(includingwakeupsource-QDECand

wakeup source-GPIO, shownas Figure3-3) can’tbe selectedaswakeup source; the

effectivewakeupsourceis32Ktimerorpadwakeupsource.

Wakeup_t i mer wakeup

Pad wakeup

PM_TOP

32K t i mer

Wakeup_di g

Qdec wakeup

Gpi o wakeup

Figure3-3 Wakeupsource

Second,select rightpower-savingmode:deepsleepmodeorsuspendmode. If

deepsleepmodeistobeselected,r24bit[7]andbit[5]shouldbesetto1;r24bit[7]


DS-ST17H30Q-E15 26 Ver2.4.0

andbit[5]shouldbeclearedifsuspendmodeistobeselected.

Third,configureotherenablingbits:setr23bit[7]to1;setr24bits[3:0]to1111,

andalsosetr24bit[6]to1.

Fourth,Writedata0x81todigitalcoreaddress0x6ftotriggerthewholesystem.

Thesystementersdeepsleepmodeorsuspendmode(power-savingstatusdepends

onthesettingofr24).

3.2 Reset

Except forpoweronreset, it isalso feasibletocarryoutsoftwarereset for the

wholechiporsomemodules.Settingaddress0x6f[5]to1b’1istoresetthewholechip.

Addresses0x60~0x62servetoresetindividualmodules:ifsomebitissettologic“1”,

thecorrespondingmoduleisreset.

Table3-4 Registerconfigurationforreset,wakeupandpowerdownenabling

Address Mnemonic Type Description ResetValue

0x60 RST0 R/W

Resetcontrol,1forreset,0forclear[0]:mcu[1]:zb[2]:rsvd[3]:dma[4]:algm[5]:sws[6]:aif

[7]:rsvd

00

0x61 RST1 R/W

[0]rsvd[1]i2c[2]rsvd[3]pwm[4]rsvd[5]rsvd[6]mspi[7]bbpll

df

0x62 RST2 R/W[0]adc[1]algs[2]mcic

00


DS-ST17H30Q-E15 27 Ver2.4.0


[3]mcicautoresetatsuspend[4]systimer[5]rsvd[6]rsvd[7]rsvd

0x6f PWDNEN W

[0]suspendenable[5]:rstall(actaspoweronreset)[6]:mculowpowermode[7]:stallmcutrigIfbit[0]set1,thensystem will go to suspend. Or onlystallmcu

4 2.4GRFTransceiver

4.1 Blockdiagram

The ST17H30Q integrates advanced BLE/2.4GHz RF transceiver. The RF

transceiver works in theworldwide 2.4GHz ISM (Industrial ScientificMedical) band

andcontainsanintegratedbalunwithasingle-endedRFTx/Rxportpin.Nomatching

componentsareneeded.

The transceiver consists of a fully integrated frequency synthesizer, a power

amplifier, a modulator and a receiver. The transceiver works in standard-compliant

BLEmodewhichsupportsFSK/GFSKmodulations.

LNA

TX Filter

RX Filter

Baseband Modulator

Baseband Demodulator

RF Synthesizer

ANT

PA

Figure4-1 BlockdiagramofRFtransceiver

TheinternalPAcandeliveramaximum6dBmoutputpower,avoidingtheneeds

foranexternalRFPA.


DS-ST17H30Q-E15 28 Ver2.4.0

4.2 Functiondescription

Air interface data rate, the modulated signaling rate for RF transceiver when

transmittingandreceivingdata,supports1MbpsmodefortheST17H30Q.

For the ST17H30Q, RF transceiver can operate with frequency ranging from

2.400GHzto2.4835GHz.TheRFchannel frequencysettingdeterminesthecenterof

thechannel.

4.3 Baseband

The baseband contains dedicated hardware logic to perform fast AGC control,

access code correlation, CRC checking, data whitening, encryption/decryption and

frequencyhoppinglogic.

ThebasebandsupportsallfeaturesrequiredbyBluetoothv4.0specification.

4.3.1 Packetformat

PacketformatisshownasTable4-1:

Table4-1 PacketFormat

LSB MSB

Preamble(1octet)

AccessAddress(4octets)

PDU(2to39octets)

CRC(3octets)

Packetlength80bit~376bit(80~376us@1Mbps).

4.3.2 RSSI

The ST17H30Q provides accurate RSSI (Receiver Signal Strength Indicator)

indicationwhichcanbereadonperpacketbasis.

5 Clock


DS-ST17H30Q-E15 29 Ver2.4.0

5.1 Systemclock

5.1.1 Systemclocksources

Figure5-1 Blockdiagramofsystemclock

There are four selectable clock sources for system clock, including: 32MHz RC

oscillator,hsdividerclock,16MHzpadclock(externalcrystaloscillator)and32KHzRC

oscillator.RegisterCLKSEL(address0x66[6:5])isusedtoselectsystemclocksource.

Commonlya16MHzcrystaloscillatorcanbeemployedtogenerateabasicclock

signal for thesystem.Themaximumfrequencytoleranceof thecrystal is ±60ppm.

Anda low-powerRCoscillatorcanbeused togeneratea32KHzclock signal for the

wakeuptimer.

PLL

RC 32MCal i br at ed RC Osci l l at or

Cal i br at ed RC Osci l l at or

/ 3

RC_32MCal i br at ed RC Osci l l at or

FHS

MUX

FHS di vi der

sys_cl k

hs di vi der cl k

Pad_16MCr yst alOsci l l at or

64M f r om RF ADC

192M

RC 32K

{0x67[0], 0x66[7]}

00

0x66[6:5]

Cloc

k MU

X

Cr yst al Osci l l at or Pad_16M

11

10

01

00

01

10

11

0x66[4:0]


DS-ST17H30Q-E15 30 Ver2.4.0

5.1.2 FHSselect

Thehighspeedclock(FHS)isselectableviaaddress{0x67[0],0x66[7]}fromthe

following sources:192MHzclock fromPLL,64MHzclock fromRFADC,32MHzclock

fromRCoscillatoror16MHzpadclock(externalcrystaloscillator).

5.1.3 HSdividerclock

Ifaddress0x66[6:5]issetto2b’01toselecttheHSdividerclockassystemclock

source,systemclockfrequencyisadjustableviaaddress0x66[4:0].FSystemclock=FFHS/

(systemclockdividervalueinaddress0x66[4:0]+1).

5.2 Moduleclock

Registers CLKEN0~CLKEN2 (address 0x63~0x65) are used to enable or disable

clock for various modules. By disable the clocks of unused modules, current

consumptioncouldbereduced.

5.2.1 SARADCclock

ADCclockderivesfromFHS.Address0x6b[7]shouldbesetto1b’1toenableADC

clock.

ADCclockfrequencydividingfactorcontainsstepandmod.

Addresses0x6b[6:4]and0x69[7:0]servetoconfigureADC_step[10:0].

Addresses0x6b[3:0]and0x6a[7:0]servetoconfigureADC_mod[11:0].

ADCclockiscalculatedaccordingtotheformulabelow:

F"#$&'(&) = F+,- ∗ adc_step[10: 0]/adc_mod[11: 0]

5.3 Registertable

Table5-1 Registertableforclock


0x63 CLKEN0 R/WClock enable control: 1 for enable; 0 fordisable[0]:mcu

8c


DS-ST17H30Q-E15 31 Ver2.4.0


[1]:zb[2]:rsvd[3]:dma[4]:algm[5]:sws[6]:aif[7]:rsvd

0x64 CLKEN1 R/W

[0]rsvd[1]i2c[2]rsvd[3]pwm[4]rsvd[5]rsvd[6]systimer[7]qdecsysclk

00

0x65 CLKEN2 R/W

[0]32kforqdec[1]rsvd[2]rsvd[3]rsvd[4]rsvd[5]rsvd[6]rsvd[7]rsvd

00

0x66 CLKSEL R/W

Systemclockselect [4:0]:systemclockdivider:fhs/((CLKSEL[4:0]+1)).Fhsreferto{0x67[0],0x66[7]}FHS_sel[6:5] 2’b00:32mclockfromrc 2’b01:hsdividerclk2’b10:16Mclockfrompad2’b11:32kclkfromrc[7]FHSsel(see0x67definition)

ff

0x67 FHS_sel R/W

{0x67[0],0x66[7]}fhsselect2’b00:192Mclockfrompll2’b01:64M2’b10:32Mclockfromosc2’b11:16Mclockfrompad

00

0x68 rsvd R/W 0x69 Adcstep[7:0] R/W adc_step[7:0] 000x6a Adcmod[7:0] R/W adc_mod[7:0] 20x6b adcmodstep R/W [3:0]adc_mod[11:8] 00


DS-ST17H30Q-E15 32 Ver2.4.0


[7:4] adc_step[11:8], adc_step[11] isenablebit.adc_clk=clk_hs*adc_step[10:0]/adc_mod[11:0]

0x6c DMIC_step R/W rsvd 10x6d DMIC_mod R/W rsvd 2

6 Timers

6.1 Timer0~Timer2

TheST17H30Qsupportsthreegeneral32-bittimersincludingTimer0~Timer2in

activemode.

Timer0andTimer1supportfourmodes:Mode0(SystemClockMode),Mode1

(GPIOTriggerMode),Mode2(GPIOPulseWidthMode)andMode3(TickMode).

Timer2 only supports Mode0 and Mode3. Generally Timer 2 is configured as

“watchdog”tomonitorfirmwarerunning.

6.1.1 Registertable

Table6-1 RegisterconfigurationforTimer0~Timer2

Address Mnemonic Type Description Reset

Value

0x620 TMR_CTRL0 RW

[0]Timer0 enable

[2:1] Timer0 mode.

0 using sclk, 1, using gpio,

2 count widht of gpi, 3 tick

[3]Timer1 enable

[5:4] Timer1 mode.

[6]Timer2 enable

[7]Bit of timer2 mode

00

0x621 TMR_CTRL1 RW [0]Bit of timer2 mode 00


DS-ST17H30Q-E15 33 Ver2.4.0


Value

[7:1]Low bits of watch dog capture

0x622 TMR_CTRL2 RW

[6:0]High bits of watch dog capture. It is

compared with [31:18] of timer2 ticker

[7]watch dog capture

00

0x623 TMR_STATUS RW

[0] timer0 status, write 1 to clear [1] timer1 status, write 1 to clear [2] timer2 status, write 1 to clear [3] watch dog status, write 1 to clear

0x624 TMR_CAPT0_0 RW Byte 0 of timer0 capture 00






0x62a TMR_CAPT1_2 RW Byte 2 of timer1 capture 00

0x62b TMR_CAPT1_3 RW Byte 3 of timer1 capture 00

0x62c TMR_CAPT2_0 RW Byte 0 of timer2 capture 00

0x62d TMR_CAPT2_1 RW Byte 1 of timer2 capture 00

0x62e TMR_CAPT2_2 RW Byte 2 of timer2 capture 00

0x62f TMR_CAPT2_3 RW Byte 3 of timer2 capture 00

0x630 TMR_TICK0_0 RW Byte 0 of timer0 ticker









DS-ST17H30Q-E15 34 Ver2.4.0


Value



0x63a TMR_TICK2_2 RW Byte 2 of timer2 ticker

0x63b TMR_TICK2_3 RW Byte 3 of timer2 ticker

6.1.2 Mode0(SystemClockMode)

InMode0,systemclockisemployedasclocksource.

AfterTimerisenabled,TimerTick(i.e.countingvalue)isincreasedby1oneach

positiveedgeofsystemclock frompreset initialTickvalue.Generally the initialTick

valueissetto0.

Once current Timer Tick value matches the preset Timer Capture (i.e. timing

value),aninterruptisgenerated,TimerstopscountingandTimerstatusisupdated.

StepsofsettingTimer0forMode0istakenasanexample.

1st:SetinitialTickvalueofTimer0

Set Initial value of Tick via registers TMR_TICK0_0~TMR_TICK0_3 (address

0x630~0x633). Address 0x630 is lowest byte and 0x633 is highest byte. It’s

recommendedtoclearinitialTimerTickvalueto0.

2nd:SetCapturevalueofTimer0

Set registers TMR_CAPT0_0~TMR_CAPT0_3 (address 0x624~0x627). Address

0x624islowestbyteand0x627ishighestbyte.

3rd:SetTimer0toMode0andenableTimer0

Set register TMR_CTRL0 (address 0x620) [2:1] to 2b’00 to select Mode 0;

Meanwhile set address 0x620[0] to 1b’1 to enable Timer0. Timer0 starts counting

upward,andTickvalueisincreasedby1oneachpositiveedgeofsystemclockuntilit

reachesTimer0Capturevalue.


DS-ST17H30Q-E15 35 Ver2.4.0

6.1.3 Mode1(GPIOTriggerMode)

InMode1,GPIOisemployedasclocksource.The“m0”/”m1”registerspecifies

theGPIOwhichgeneratescountingsignalforTimer0/Timer1.

AfterTimerisenabled,TimerTick(i.e.countingvalue)isincreasedby1oneach

positive/negativeedgeofGPIOfrompresetinitialTickvalue.GenerallytheinitialTick

value is set to 0. The “Polarity” register specifies the GPIO edge when Timer Tick

countingincreases.

Note: Refer to Section 8.1.2 for corresponding “m0”, “m1” and “Polarity” register

address.

Once current Timer Tick value matches the preset Timer Capture (i.e. timing

value),aninterruptisgeneratedandtimerstopscounting.






2nd:SetCapturevalueofTimer1

Set registers TMR_CAPT1_0~TMR_CAPT1_3 (address 0x628~0x62b). Address

0x628islowestbyteand0x62bishighestbyte.

3rd:SelectGPIOsourceandedgeforTimer1

SelectcertainGPIOtobetheclocksourceviasetting“m1”register.

Select positive edge or negative edge of GPIO input to trigger Timer1 Tick

incrementviasetting“Polarity”register.

4th:SetTimer1toMode1andenableTimer1

Set address 0x620[5:4] to 2b’01 to select Mode 1; Meanwhile set address

0x620[3] to1b’1 toenableTimer1.Timer1 starts countingupward,andTimer1Tick

valueisincreasedby1oneachpositive/negative(specifiedduringthe3rdstep)edge

ofGPIOuntilitreachesTimer1Capturevalue.


DS-ST17H30Q-E15 36 Ver2.4.0

6.1.4 Mode2(GPIOPulseWidthMode)

InMode2,systemclock isemployedastheunittomeasurethewidthofGPIO

pulse.The“m0”/“m1”register specifies theGPIOwhichgeneratescontrol signal for

Timer0/Timer1.

After Timer is enabled, Timer Tick is triggered by a positive/negative

(configurable)edgeofGPIOpulse.ThenTimerTick(i.e.countingvalue)isincreasedby

1oneachpositiveedgeof systemclock frompreset initialTickvalue.Generally the

initialTickvalueissetto0.The“Polarity”registerspecifiestheGPIOedgewhenTimer

Tickstartscounting.

Note: Refer to Section 8.1.2 for corresponding “m0”, “m1” and “Polarity” register

address.

While a negative/positive edge of GPIO pulse is detected, an interrupt is

generated and timer stops counting. The GPIO pulse width could be calculated in

termsoftickcountandperiodofsystemclock.


1st:SetinitialTimer0Tickvalue




2nd:SelectGPIOsourceandedgeforTimer0

SelectcertainGPIOtobetheclocksourceviasetting“m0”register.

SelectpositiveedgeornegativeedgeofGPIO input to triggerTimer0 counting

startviasetting“Polarity”register.

3rd:SetTimer0toMode2andenableTimer0

Setaddress0x620[2:1]to2b’10toselectMode2;Meanwhilesetaddress0x620

[0]to1b’1toenableTimer0.

Timer0 Tick is triggered by a positive/negative (specified during the 2nd step)

edgeofGPIOpulse.Timer0startscountingupwardandTimer0Tickvalueisincreased

by1oneachpositiveedgeofsystemclock.

While a negative/positive edge of GPIO pulse is detected, an interrupt is


DS-ST17H30Q-E15 37 Ver2.4.0

generatedandTimer0tickstops.

4th:ReadcurrentTimer0TickvaluetocalculateGPIOpulsewidth

ReadcurrentTimer0Tickvaluefromaddress0x630~0x633.

ThenGPIOpulsewidthiscalculatedasfollows:

GPIOpulsewidth

= Systemclockperiod ∗ (currentTimer0Tick − intialTimer0Tick)

ForinitialTimer0Tickvaluesettotherecommendedvalueof0,then:

GPIOpulsewidth = Systemclockperiod ∗ currentTimer0Tick.

6.1.5 Mode3(TickMode)

InMode3,systemclockisemployed.

AfterTimerisenabled,TimerTickstartscountingupward,andTimerTickvalueis

increasedby1oneachpositiveedgeofsystemclock.

Thismodecouldbeusedastimeindicator.Therewillbenointerruptgenerated.

TimerTickkeepsrollingfrom0to0xffffffff.WhenTimertickoverflows,itreturnsto0

andstartscountingupwardagain.



Set Initial valueofTickviaaddress0x630~0x633.Address0x630 is lowestbyte

andaddress0x633ishighestbyte.It’srecommendedtoclearinitialTimerTickvalue

to0.

2nd:SetTimer0toMode3andenableTimer0

Set address 0x620[2:1] to 2b’11 to select Mode 3, meanwhile set address

0x620[0]to1b’1toenableTimer0.Timer0Tickstartstoroll.

3rd:ReadcurrentTimer0Tickvalue

CurrentTimer0Tickvaluecanbereadfromaddress0x630~0x633.

6.1.6 Watchdog

Programmable watchdog could reset chip from unexpected hang up or

malfunction.


DS-ST17H30Q-E15 38 Ver2.4.0

OnlyTimer2supportsWatchdog.

Timer2 Tick has 32bits. Watchdog Capture has only 14bits, which consists of

TMR_CTRL2(address0x622)[6:0]ashigherbitsandTMR_CTRL1(address0x621)[7:1]

as lower bits. Chip will be reset when the Timer2 Tick[31:18] matchesWatch dog

capture.

1st:ClearTimer2Tickvalue

Clear registers TMR_TICK2_0 ~TMR_TICK2_3 (address 0x638~0x63b). Address

0x638islowestbyteand0x63bishighestbyte.

2nd:EnableTimer2

SetregisterTMR_CTRL0(address0x620)[6]to1b’1toenableTimer2.

3rd:Set14-bitWatchdogCapturevalueandenableWatchdog

Set address 0x622[6:0] as higher bits of watchdog capture and 0x621[7:1] as

lowerbits.Meanwhilesetaddress0x622[7]to1b’1toenableWatchdog.

ThenTimer2Tickstartscountingupwardsfrom0.

If bits[31:18] of Timer2 Tick value read from address 0x638~0x63b reaches

watchdogcapture,thechipwillbereset.

6.2 32KLTIMER

The ST17H30Q supports a low frequency (32KHz) LTIMER in suspendmode or

deepsleepmode.Thistimercanbeusedasonekindofwakeupsource.

Analogregister3V_reg35[7]shouldbesetto1b’1toenabletheLTIMER.

3V_reg16~3V_reg18[6:0]servetoconfiguretimingvaluefortheLTIMERwiththe

unitofms.

3V_reg18[7] serves to selectmode for the LTIMER: continuousmode,or single

mode. In continuous mode, when the LTIMER expires, the timing value is

automatically reloaded, the counting value returns to zero and starts counting

upwardsagain.Insinglemode,whentheLTIEMRexpires,itstopscounting.

3V_reg23[5] serves to select clock source for the LTIMER: 32K RC oscillator, or

16MPadclock.

Currentcountingvaluecanbereadfrom3V_reg32~3V_reg34and3V_reg35[6].


DS-ST17H30Q-E15 39 Ver2.4.0

Table6-2 3.3VanalogregistertableforLTIMER

Addr(Decimal)

Addr(Hexadecimal)

Name Description Defaultvalue

r16 0x10 32ktimer_cnt[7:0]32ktimercnt[0]=1means4cyclesof32k

r17 0x11 32ktimer_cnt[15:8]

r18

0x12[6:0] 32ktimer_cnt[22:16]

0x12[7] 32ktimermode32ktimermode,1:continuousmode,0:singlemode

r23

0x17[2:0] wakeup_en

[0]->digitalwakeupenable[1]-->32ktimerwakeupenable,[2]padwakeupenable

0x17[3] 32ktimerreset 0x17[4] rsvd 0x17[5] 32ktimerclockselect 0:32kosc,116Mxtl 0x17[6] rsvd

0x17[7] rsvdpowerdownsequenceenable

r32 0x20 readonly32ktimer_cnt[7:0](1cycleof32kclockwillchangethereslult)

r33 0x21 readonly 32ktimer_cnt[15:8] r34 0x22 readonly 32ktimer_cnt[23:16]

r35

0x23[0] rsvd

0x23[1] w/rwrite1tocleantimerwakeupstatus.

0x23[2] w/rwrite1tocleandigitalwakeupstatus

0x23[3] w/rwrite1tocleanpadwakeupstatus

0x23[4] wd_statuswrite1tocleanwatchdogstatus.

0x23[5] readonly rsvd 0x23[6] readonly 32ktimer_cnt[24]

0x23[7] w/r32ktimerenabletogglesignal,write1toenable32ktimer

6.3 Systemtimer

TheST17H30QalsosupportsaSystemTimer.


DS-ST17H30Q-E15 40 Ver2.4.0

Table6-3 RegistertableforSystemTimer

Address Mnemonic R/W FunctionDefaultValue

0x740 Sys_timer[7:0] R/W 000x741 Sys_timer[15:8] R/W 000x742 Sys_timer[23:16] R/W 00

0x743 Sys_timer[31:24] R/WSystemtimercounter,writetosetinitialvalue.Thisisthesystimercounter

00

7 InterruptSystem

7.1 Interruptstructure

The interrupting function is applied to manage dynamic program sequencing

basedonreal-timeeventstriggeredbytimers,pinsandetc.

For the ST17H30Q, there are 24 interrupt sources in all: 16 types are

level-triggeredinterruptsourcesand8typesareedge-triggeredinterruptsources.

WhenCPUreceivesaninterruptrequest(IRQ)fromsomeinterruptsource,itwill

decidewhether to respond to the IRQ. IfCPUdecides to respond, itpausescurrent

routine and starts to execute interrupt service subroutine. Program will jump to

certain code address and execute IRQ commands. After finishing interrupt service

subroutine,CPUreturnstothebreakpointandcontinuestoexecutemainfunction.

7.2 Registerconfiguration

Table7-1 RegistertableforInterruptsystem


0x640 MASK_0 RW

Byte0interruptmask,level-triggeredtype{irq_host_cmd|irq_qdec, rsvd, irq_pwm,irq_dma,rsvd,time2,time1,time0}[7]:irq_host_cmd|irq_qdec[6]:rsvd[5]:irq_pwm[4]:irq_dma[3]:rsvd[2]:time2[1]:time1[0]:time0

00

0x641 MASK_1 RW Byte1interruptmask,level-triggeredtype 00


DS-ST17H30Q-E15 41 Ver2.4.0


{an_irq, irq_software, irq_zb, rsvd, rsvd,rsvd,rsvd,rsvd}[7]:an_irq[6]:irq_software[5]:irq_zb[4]:rsvd[3]:rsvd[2]:rsvd[1]:rsvd[0]:rsvd

0x642 MASK_2 RW

Byte2interruptmask,edge-triggeredtype{gpio2risc[0], rsvd, rsvd, rsvd, pm_irq,irq_gpio,rsvd,rsvd}[7]:gpio2risc[0][6]:rsvd[5]:rsvd[4]:rsvd[3]:pm_irq[2]:irq_gpio[1]:rsvd[0]:rsvd

00

0x643 IRQMODE RW[0]interruptenable[1]reserved(Multi-Addressenable)

00

0x644 PRIO_0 RWByte0ofpriority1:Highpriority; 0:Lowpriority

00

0x645 PRIO_1 RW Byte1ofpriority 000x646 PRIO_2 RW Byte2ofpriority 000x648 IRQSRC_0 R Byte0ofinterruptsource 0x649 IRQSRC_1 R Byte1ofinterruptsource 0x64a IRQSRC_2 R Byte2ofinterruptsource

7.2.1 Enable/Maskinterruptsources

Various interrupt sources could be enabled or masked by registers

MASK_0~MASK_2(address0x640~0x642).

7.2.2 Interruptmodeandpriority

Interrupt mode is typically-used mode. Register IRQMODE (address 0x643)[0]

shouldbesetto1b’1toenableinterruptfunction.


DS-ST17H30Q-E15 42 Ver2.4.0

IRQ tasks could be set as High or Low priority via registers PRIO_0~PRIO_2

(address 0x644~0x646). When more than one interrupt sources assert interrupt

requests at the same time, CPU will respond depending on respective interrupt

prioritylevels.It’srecommendednottomodifyprioritysetting.

7.2.3 Interruptsourceflag

Three bytes in registers IRQSRC_0~IRQSRC_2 (address 0x648~0x64a) serve to

indicate IRQ sources. Once IRQ occurs from certain source, the corresponding IRQ

sourceflagwillberaisedto“High”.UsercouldidentifyIRQsourcebyreadingaddress

0x648~0x64a.

Whenhandlingedge-triggeredtypeinterrupt,thecorrespondingIRQsourceflag

needstobeclearedviaaddress0x64a.Taketheinterruptsourceirq_gpioforexample:

First enable the interrupt sourceby settingaddress0x642[2] to1; then set address

0x643 [0] to1 toenable the interrupt. In interrupthandling function,24-bitdata is

readfromaddress0x648~0x64atodeterminewhichIRQsourceisvalid;ifdatabit[18]

is 1, it means the irq_gpio interrupt is valid. Clear this interrupt source by setting

address0x64abit[2]to1.

As for level-type interrupt, IRQ interrupt source status needs to be cleared via

setting corresponding module status register. Take Timer0 IRQ interrupt source for

example, register TMR_STATUS (address 0x623) [0] should be written with 1b’1 to

clearTimer0status(refertoSection6.1.1).

8 Interface

8.1 GPIO

The ST17H30QET24 supports up to 14 GPIOs. Except for dedicated GPIOs, all

digitalIOscanbeusedasgeneralpurposeIOs.PleaserefertoSection1.6foravailable

GPIOresources.


DS-ST17H30Q-E15 43 Ver2.4.0

8.1.1 Basicconfiguration

8.1.1.1 Multiplexedfunctions

PleaserefertoTable8-1forvariousGPIOinterfaceconfiguration.

Table8-1 GPIOlookuptable1fortheST17H30QET24

Pin

Name

Default

FunctionPriority0 Priority1 Priority2

Actas

GPIO

ActasGPIO Input

Enable

DS(Drive

Strength)OEN Input Output

MCLK MCLK 5a6[2] 5a2[2] 5a0[2] 5a3[2] 5a1[2] 5a5[2]

MSDO MSDO 5a6[3] 5a2[3] 5a0[3] 5a3[3] 5a1[3] 5a5[3]

MSDI MSDI 5a6[4] 5a2[4] 5a0[4] 5a3[4] 5a1[4] 5a5[4]

MSCN MSCN 5a6[1] 5a2[1] 5a0[1] 5a3[1] 5a1[1] 5a5[1]

SWS SWS 5a6[5] 5a2[5] 5a0[5] 5a3[5] 5a1[5] 5a5[5]

GP9/

pwm0

GPIO

input 58e[1] 58a[1] 588[1] 58b[1] 589[1] 58d[1]

GP10/

pwm1

GPIO

input 58e[2] 58a[2] 588[2] 58b[2] 589[2] 58d[2]

GP17/

pwm2_inv/

ANA0

GPIO

inputpwm2_inv 596[1] 592[1] 590[1] 593[1] 591[1] 595[1]

GP18/

ANA1

GPIO

input NA 592[2] 590[2] 593[2] 591[2] 595[2]

GP22/

scl/

ANA2

GPIO

inputscl NA 592[6] 590[6] 593[6] 591[6] 595[6]

GP23/

sda/

ANA3

GPIO

inputsda 596[7] 592[7] 590[7] 593[7] 591[7] 595[7]

GP30/

scl

GPIO

inputscl NA 59a[6] 598[6] 59b[6] 599[6] 59d[6]

GP31/ GPIO sda 59e[7] 59a[7] 598[7] 59b[7] 599[7] 59d[7]


DS-ST17H30Q-E15 44 Ver2.4.0

Pin

Name

Default

FunctionPriority0 Priority1 Priority2

Actas

GPIO

ActasGPIO Input

Enable

DS(Drive

Strength)OEN Input Output

sda input

GP5/

sda/

pwm2_inv/

pwm3

GPIO

input

5d4[0]=1

sda

(this

function

shouldbe

disabled)

5d4[1]=1

pwm3pwm2_inv 586[5] 582[5] 580[5] 583[5] 581[5] 585[5]

*Notes:

(1)OEN:activelow.0:outputenable.

(2)InputEnable:activehigh.1:inputenable.

(3)NA:noconfiguration.

(4)Priority0>Priority1>Priority2.

(5)FortheST17H30QET24,it’snotrecommendedtouseGP5asI2C_SDAfunction.

ThepinsamongGP0~GP32(includingGP5,GP9~GP10,GP17~GP18,GP22~GP23,

GP30~GP31)areusedasGPIO input functionbydefault. Forapinwithmultiplexed

function(s), toenable the functionwith lowerpriority,other function(s)withhigher

priorityshouldbedisabledfirst.

TaketheMCLKasanexample:

(1) ThispinactsasMCLKfunctionbydefault.

(2) TousethepinasGPIOfunction,address0x5a6[2]shouldbesetto1b’1.

If the pin is used as output, its “OEN” register (address 0x5a2[2]) and “Input

Enable”register(address0x5a1[2])shouldbecleared.

Ifthepinisusedasinput,its“OEN”register(address0x5a2[2])and“InputEnable”

register(address0x5a1[2])shouldbesetto1b’1.

TaketheGP5/sda/pwm2_inv/pwm3asanotherexample:


DS-ST17H30Q-E15 45 Ver2.4.0

(1) ThispinactsasGPIOinputbydefault.

(2) TousethepinasGPIOoutput,address0x586[5]shouldbesetto1b’1,and

addresses{0x582[5],0x581[5]}shouldbecleared.

(3) Touse thepinaspwm3function,addresses {0x586[5],0x5d4[0]} shouldbe

cleared,and0x5d4[1]shouldbesetto1b’1.

(4) To use the pin as pwm2_inv function, addresses {0x586[5], 0x5d4[0],

0x5d4[1]}shouldbecleared.

8.1.1.2 Drivestrength

The registers in the “DS” column are used to configure corresponding pin’s

drivingstrength:“1”indicatesmaximumdrivelevel,while“0”indicatesminimaldrive

level.The“DS”configurationwilltakeeffectwhenthepinisusedasoutput.It’ssetas

the strongestdriving levelbydefault. In actual applications,driving strength canbe

decreasedtolowerlevelifnecessary.

As shown inTable8-2,all theGPIOpins supportmaximumdrive levelof4mA

(“DS”=1)andminimaldrivelevelof0.7mA(“DS”=0)withthefollowingexceptions:

² MCLK, MSDO, MSDI and MSCN: maximum=4mA (“DS”=1), minimum=2mA

(“DS”=0);

² SWS:maximum=8mA(“DS”=1),minimum=4mA(“DS”=0).

Table8-2 IOdrivestrengthforST17H30QET24

No. Pin Name Drive Strength

“DS”=0 “DS”=1

1 MSDO 2mA 4mA

2 MSDI 2mA 4mA

3 MSCN 2mA 4mA

4 SWS 4mA 8mA

5 GP9/pwm0 # 0.7mA 4mA 6 GP10/pwm1 # 0.7mA 4mA 11 GP17/pwm2_inv/ANA0 * 0.7mA 4mA 12 GP18/ANA1 * 0.7mA 4mA 13 GP22/scl/ANA2 * 0.7mA 4mA


DS-ST17H30Q-E15 46 Ver2.4.0

No. Pin Name Drive Strength

“DS”=0 “DS”=1

14 GP23/sda/ANA3 * 0.7mA 4mA 18 GP30/scl 0.7mA 4mA 19 GP31/sda * 0.7mA 4mA

23 GP5/sda/pwm2_inv/ pwm3 #

0.7mA 4mA

24 MCLK 2mA 4mA

8.1.2 ConnectionrelationshipbetweenGPIOandrelatedmodules

GPIO can be used to generate GPIO interrupt signal for interrupt system,

countingorcontrolsignalforTimer/Countermodule,orGPIO2RISCinterruptsignalfor

interruptsystem.

Forthe“ExclusiveOr(XOR)”operationresultforinputsignalfromanyGPIOpin

andrespective“polarity”value,ononehand,ittakes“And”operationwith“irq”and

generatesGPIOinterruptrequestsignal;ontheotherhand,ittakes“And”operation

with“m0/m1”,andgeneratescountingsignal inMode1orcontrolsignal inMode2

forTimer0/Timer1,orgeneratesGPIO2RISCinterruptrequestsignal.

GPIOinterruptrequestsignal=|((input^polarity)&irq);

Counting(Mode1)orcontrol(Mode2)signalforTimer0=|((input^polarity)&m0);

Counting(Mode1)orcontrol(Mode2)signalforTimer1=|((input^polarity)&m1);

GPIO2RISC[0]interruptrequestsignal=|((input^polarity)&m0);

Ti mer 0

Ti mer 1Input

Polarity

m1

m0

Irq GPIO_IRQ

Timer0_IRQ

Timer1_IRQ

GPIO2RISC[0]_IRQ


DS-ST17H30Q-E15 47 Ver2.4.0

Figure8-1 LogicrelationshipbetweenGPIOandrelatedmodules

Please refer to Table 8- 3 and Table 7- 1 to learn how to configure GPIO for

interruptsystemorTimer0/Timer1(Mode1orMode2).

(1) FirstenableGPIOfunction,IEanddisableOEN.

(2) GPIOIRQsignal:SelectGPIOinterrupttriggeredge(positiveedgeornegative

edge) via configuring “Polarity” register, and set corresponding GPIO

interruptenablingbit“Irq”register.FinallyenableGPIOinterrupt(irq_gpioat

address0x642[2]).

User can readaddresses {0x5c0~0x5c3, 0x5d0} to seewhichGPIOasserts

GPIO interrupt request signal. Note: 0x5c0[5] --> GP5, 0x5c1[1] --> GP9,

0x5c1[2]-->GP10,0x5c2[1]-->GP17,0x5c2[2]-->GP18,0x5c2[6]-->GP22,

0x5c2[7]-->GP23,0x5c3[6]-->GP30,0x5c3[7]-->GP31,0x5d0[1]-->MSCN,

0x5d0[2]-->MCLK,0x5d0[3]-->MSDO,0x5d0[4]-->MSDI,0x5d0[5]-->SWS.

(3) Timer/Counter counting or control signal: Configure “Polarity” register (In

Mode 1, it determines GPIO edge when Timer Tick counting increases; in

Mode2, itdeterminesGPIOedgewhenTimerTick starts counting)andset

“m0/m1”register.

Usercanreadaddresses{0x5c4~0x5c7,0x5d1}/{0x5c8~0x5cb,0x5d2}tosee

whichGPIOassertscountingsignal(inMode1)orcontrolsignal(inMode2)

for Timer0/Timer1. Note: Timer0: {0x5c4[5] --> GP5, 0x5c5[1] --> GP9,

0x5c5[2]-->GP10,0x5c6[1]-->GP17,0x5c6[2]-->GP18,0x5c6[6]-->GP22,

0x5c6[7]-->GP23,0x5c7[6]-->GP30,0x5c7[7]-->GP31,0x5d1[1]-->MSCN,

0x5d1[2]-->MCLK,0x5d1[3]-->MSDO,0x5d1[4]-->MSDI,0x5d1[5]-->SWS}

/Timer1:{0x5c8[5]-->GP5,0x5c9[1]-->GP9,0x5c9[2]-->GP10,0x5ca[1]-->

GP17,0x5ca[2] -->GP18,0x5ca[6] -->GP22,0x5ca[7] -->GP23,0x5cb[6] -->

GP30,0x5cb[7]-->GP31,0x5d2[1]-->MSCN,0x5d2[2]-->MCLK,0x5d2[3]-->

MSDO,0x5d2[4]-->MSDI,0x5d2[5]-->SWS}.

(4) GPIO2RISCIRQsignal:SelectGPIO2RISCinterrupttriggeredge(positiveedge

or negative edge) via configuring “Polarity”, and set corresponding GPIO

enablingbit“m0”.EnableGPIO2RISC[0]interrupt,i.e.“gpio2risc[0]”(address


DS-ST17H30Q-E15 48 Ver2.4.0

0x642[7]).

User can read addresses {0x5c4~0x5c7, 0x5d1} to see which GPIO asserts

GPIO2RISC[0] interrupt request signal.Note: {0x5c4[5] -->GP5,0x5c5[1] -->

GP9, 0x5c5[2] -->GP10, 0x5c6[1] -->GP17, 0x5c6[2] -->GP18, 0x5c6[6] -->

GP22,0x5c6[7]-->GP23,0x5c7[6]-->GP30,0x5c7[7]-->GP31,0x5d1[1]-->

MSCN,0x5d1[2]-->MCLK,0x5d1[3]-->MSDO,0x5d1[4]-->MSDI,0x5d1[5]-->

SWS}.

Table8-3 GPIOlookuptable2fortheST17H30QET24

PinInput

(R)

Polarity

1:activelow

0:activehigh

Irq m0 m1

MCLK 5a0[2] 5a4[2] 5a7[2] 5ac[2] 5b4[2]

MSDO 5a0[3] 5a4[3] 5a7[3] 5ac[3] 5b4[3]

MSDI 5a0[4] 5a4[4] 5a7[4] 5ac[4] 5b4[4]

MSCN 5a0[1] 5a4[1] 5a7[1] 5ac[1] 5b4[1]

SWS 5a0[5] 5a4[5] 5a7[5] 5ac[5] 5b4[5]

GP9/pwm0 588[1] 58c[1] 58f[1] 5a9[1] 5b1[1]

GP10/pwm1 588[2] 58c[2] 58f[2] 5a9[2] 5b1[2]

GP17/pwm2_inv/

ANA0590[1] 594[1] 597[1] 5aa[1] 5b2[1]

GP18/ANA1 590[2] 594[2] 597[2] 5aa[2] 5b2[2]

GP22/scl/ANA2

590[6] 594[6] 597[6] 5aa[6] 5b2[6]

GP23/sda/ANA3

590[7] 594[7] 597[7] 5aa[7] 5b2[7]

GP30/scl 598[6] 59c[6] 59f[6] 5ab[6] 5b3[6]

GP31/sda 598[7] 59c[7] 59f[7] 5ab[7] 5b3[7]

GP5/sda/

580[5] 584[5] 587[5] 5a8[5] 5b0[5]


DS-ST17H30Q-E15 49 Ver2.4.0

PinInput

(R)

Polarity

1:activelow

0:activehigh

Irq m0 m1

pwm2_inv/pwm3

8.2 I2C

The ST17H30Q embeds I2C hardware module, which could only act as Slave

mode. I2C isapopular inter-IC interfacerequiringonly2bus lines,aserialdata line

(SDA)andaserialclockline(SCL).

8.2.1 Pinconfiguration

Table8-4showsI2Cinterfaceconfigurationandpriority:

Table8-4 I2Cpinconfiguration

a)~586[5]&5d4[0] Reserved(GP4/GP5)

b)~58e[5] Reserved(GP12/GP13)

c)~596[7] GP22/GP23

d)~59e[7] GP30/GP31

Priority:a)>b)>c)>d)

To use GP22 and GP23 of the ST17H30QET24 as I2C_SCL and I2C_SDA

respectively, address 596[7] should be cleared, meanwhile GP5 should not be

configuredasI2C_SDAfunction.

It’s noted that the I2C_SCL pin must be configured as “input” via setting the

corresponding“InputEnable”registerto1b’1.

8.2.2 LenzeI2Ccommunicationprotocol

Lenze I2C module supports standard mode (100kbps), Fast-mode (400kbps),

Fast-modeplus(1Mbps)andHigh-speedmode(3.4Mbps)withrestrictionthatsystem


DS-ST17H30Q-E15 50 Ver2.4.0

clockmustbebyatleast10xofdatarate.

Two wires, SDA and SCL carry information between Master device and Slave

device connected to the bus. Each device is recognized by unique address.Master

deviceisthedevicewhichinitiatesadatatransferonthebusandgeneratestheclock

signalstopermitthattransfer.Slavedeviceisthedeviceaddressedbyamaster.

BothSDAandSCLarebidirectional linesconnectedtoapositivesupplyvoltage

viaapull-upresister.Whenthebusisfree,bothlinesareHIGH.It’snotedthatdatain

SDAlinemustkeepstablewhenclocksignalinSCLlineisathighlevel,andlevelstate

inSDAlineisonlyallowedtochangewhenclocksignalinSCLlineisatlowlevel.

Figure8-2 I2Ctimingchart

8.2.3 Registertable

Table8-5 RegistertableforI2C

Address Name R/W DescriptionReset

Value

0x00 rsvd RW

0x01 I2CID RW I2CID 0x5c

0x02 rsvd RW

0x03 I2CSCT RW

[0]:addressautoincreaseenable

[1]:rsvd

[2]enablehostaddress

0x01

0x20 PCMD RWCommandsentbyhost

[6]:Hosttodevice


DS-ST17H30Q-E15 51 Ver2.4.0

Address Name R/W DescriptionReset

Value

[7]:Devicetohost

0x21 HOSTCS

W/r[0]:host_rd_clear_en:hostreadauto

clearenable

r/o[1]:host_cmd_rd:i2chostoperation

havehappenedandisreadoperation

r/o[2]:host_cmd_wr:i2chostoperation

havehappenedandiswriteoperation

0x01

0x22 irq

[0]:write1clearsoftware_irq,read

softwareirqstatus

[1]:write1clearan_irq,readan_irq

status

[2]:write1clearhost_pkt_irq,read

host_pkt_irqstatus

[3]rsvd

[4]write1totriggersoftwareirq

0x3e Reg_host_map_adrl R/WI2Cmapping[7:0]:LowerbyteofMapping

modebufferaddress0x80

0x3f Reg_host_map_adrh R/WI2Cmapping[15:8]:Higherbyteof

Mappingmodebufferaddress0x9f

8.2.4 I2CSlavemode

TheI2CoftheST17H30QcanonlybeusedasSlave. I2Cslaveaddresscouldbe

configuredinI2CID(address0x01)[7:1].


DS-ST17H30Q-E15 52 Ver2.4.0

Figure8-3 I2Cslaveaddress

In I2CSlavemode,Master could initiate transactionanytime. I2C slavemodule

willreplyACKautomatically.

SubmodesincludingDirectMemoryAccess(DMA)mode,Mappingmodeanda

specific“CommandAnalysis”modearesupported.Thelatterisdesignedspeciallyfor

theuserwhowantstodefineandusehisownI2Cprotocolandread/writeformat.

8.2.4.1DMAmode

InDMAmode,otherdevices(Master)couldread/writeRegisterand/orSRAMof

theST17H30QviaI2Cprotocol,andinitialaccessaddressisspecifiedbyI2CMaster.In

this mode, I2C Slave will execute the read/write command from I2C Master

automatically. But user needs to notice that the lowest system clock shall be 10x

fasterthanI2Cbitrate.

Theaccessaddress isoffsetby0x800000. InST17H30Q,Registeraddressstarts

from0x800000andSRAMaddressstartsfrom0x808000.Forexample,ifAddr(High)is

0xaaandAddr(Low)is0xcc,therealaddressofaccesseddatais0x80aacc.

Master could access data of the ST17H30Q via I2C byte by byte, and access

addresssupportsautomaticalincrementbysettingaddress0x03[0]to1.

START ID W

8bits

ACK AddrH ACK AddrL ACK

DATA ACK

STOP

8bits 8bits

8bits

ReadFormatinDMAmode

START ID R

8bits

ACK NAK STOP

Figure8-4 ReadformatinI2CDMAmode

START ID W

8bits

ACK AddrH ACK AddrL ACK DATA ACK STOP

8bits 8bits 8bits

WriteFormatinDMAmode


DS-ST17H30Q-E15 53 Ver2.4.0

Figure8-5 WriteformatinI2CDMAmode

8.2.4.2Mappingmode

Address0x03[2]shouldbesetto1b’1toenableMappingmode.

In Mapping mode, data written and read by I2C master will be redirected to

specified 128-byte buffer in SRAM. The initial address of the 128-byte buffer is

configurableviaaddresses0x3e~0x3f.Address0x3eislowerbyteandaddress0x3fis

higherbyte.Thefirst64-bytebufferisforwrittendataandfollowing64-bytebufferis

for read data. Every time the data access will start from the beginning of the

Write-buffer/ReadbufferafterI2Cstopconditionoccurs.

DATA ACK

8bits

ReadFormatinmappingmode

START ID R

8bits

ACK NAK STOP

Figure8-6 ReadformatinI2CMappingmode

START ID W

8bits

ACK DATA ACK STOP

8bits

WriteFormatinmappingmode

Figure8-7 WriteformatinI2CMappingmode

8.2.4.3Commandanalysismode

For I2C Master that uses self-defined I2C protocol and read/write format, a

specific“CommandAnalysis”modeissupportedbytheI2CoftheST17H30Q(Slave).

I2CMastershouldspecify initialaccessaddressas0x20(offsetby0x800000) in

DMA mode, or configure mapping mode buffer address registers (addresses

0x3e~0x3f) as 0x800020 in mappingmode, by sending command to I2C Slave. I2C

Slave supports command analysis function. By reading address 0x21[2:1], user can

knowwhethertheI2CMasteroperationthatjusthappenedisreadorwriteoperation.


DS-ST17H30Q-E15 54 Ver2.4.0

8.3 SWS

TheST17H30QsupportsSWS(SingleWireSlave) interfacewhichrepresentsthe

slave device of the single wire communication system developed by Lenze. The

maximumdataratecanbeupto2Mbps.

8.4 Pull-up/Pull-downresistor

FortheST17H30QET24,theGPIOsincludingGP17~GP18,GP22~GP23andGP31

support configurable 1MΩ/10KΩ pull-up resistor or 100KΩ pull-down resistor; the

GPIOs including GP5 and GP9~GP10 support 100KΩ pull-down resistor. Related

registerconfigurationcanbefoundinTable8-6.Bydefaultthepull-upandpull-down

resistorsaredisabled.

Take the GP17 as an example: Setting analog register afe3V_reg08<1:0> to

2b’01/2b’10/2b’11 is to enable 1MΩ pull-up resistor/10KΩ pull-up resistor/100KΩ

pull-down resistor respectively for GP17; Clearing the two bits disables pull-up and

pull-downresistorsforGP17.

Table8-6 3.3VanalogregistersrelatedtoPull-up/Pull-downresistor


Description

afe3V_reg08<1:0> pullupdown_ctrl<1:0> 00

WakeupmuxinputGP17pullup/downcontrols00--Nopullup/downresistor 01--1MOhmpull-upresistor10–10kOhmpull-upresistor11–100kOhmpull-downresistor



afe3V_reg08<5:4> pullupdown_ctrl<1:0> 00 reserved




DS-ST17H30Q-E15 55 Ver2.4.0


Description






afe3V_reg40<7:0> pulldown_ctrl<7:0>00000000

GP6~GP0,GP32pulldownenable0--Nopulldownresistor1--enable100kOhmpulldownresistor

afe3V_reg41<7:0> pulldown_ctrl<15:8>00000000

GP14~GP7pulldownenable0--Nopulldownresistor1--enable100kOhmpulldownresistor

afe3V_reg42<1:0> pulldown_ctrl<17:16> 00 reserved






DS-ST17H30Q-E15 56 Ver2.4.0

9 QuadratureDecoder

TheST17H30Qembedsonequadraturedecoder(QDEC)whichisdesignedmainly

forapplicationssuchaswheel.TheQDECimplementsdebouncefunctiontofilterout

jitteronthetwophaseinputs,andgeneratessmoothsquarewavesforthetwophase.

9.1 Inputpinselection

The QDEC supports two phase input; each input is selectable from the 6

dedicated GPIOs including GP17~GP18, GP22~GP23 and GP30~GP31 via setting

address0xd2[4:0](forchannela)/0xd3[4:0](forchannelb).

Table9-1 InputpinselectionAddress0xd2[4:0]/0xd3[4:0] Pin

0 Reserved(GP16)

1 GP17

2 GP18

3 Reserved(GP19)

4 Reserved(GP20)

5 Reserved(GP21)

6 GP22

7 GP23

8 Reserved(GP24)

9 Reserved(GP25)

10 Reserved(GP26)

11 Reserved(GP27)

12 Reserved(GP28)

13 Reserved(GP29)

14 GP30

15 GP31

9.2 Commonmodeanddoubleaccuracymode

TheQDEC embeds an internal hardware counter, which is not connectedwith

bus.

Address0xd7[0]servestoselectcommonmodeordoubleaccuracymode.

For each wheel rolling step, two pulse edges (rising edge or falling edge) are

generated.


DS-ST17H30Q-E15 57 Ver2.4.0

If address0xd7[0] is cleared to select commonmode, theQDECCounter value

(real time counting value) is increased/decreased by 1 only when the same

rising/fallingedgesaredetectedfromthetwophasesignals.

Onewheelrolling

COUNTERvalueincreasedby1

Anotherwheelrolling


Onewheelrolling

COUNTERvaluedecreasedby1

Anotherwheelrolling


Figure9-1 Commonmode

If address 0xd7[0] is set to 1b’1 to select double accuracy mode, the QDEC

Counter value (real time counting value) is increased/decreased by 1 on each

rising/falling edge of the two phase signals; the QDEC Counter value will be

increased/decreasedby2foronewheelrolling.


DS-ST17H30Q-E15 58 Ver2.4.0

Onewheelrolling


Anotherwheelrolling




Onewheelrolling


Anotherwheelrolling




Figure9-2 Doubleaccuracymode

9.3 Readrealtimecountingvalue

Neither canHardwareCountervaluebe readdirectlyvia software,nor can the

countingvalueinaddress0xd0beupdatedautomatically.

To read real time counting value, firstwrite address 0xd8[0]with 1b’1 to load


DS-ST17H30Q-E15 59 Ver2.4.0

HardwareCounterdataintotheQDEC_COUNTregister,thenreadaddress0xd0.

HardwareCounter

DigitalRegisterQDEC_COUNT(address0xd0)

1)Write“ 1” toaddress0xd8[0]toloaddata

QDEC

2)Read

Figure9-3 Readrealtimecountingvalue

9.4 QDECinterrupt

Address0xd4[0]servestoenableormaskQDECinterrupt.

If address 0xd4[0] is set to 1b’1 to enable QDEC interrupt, whenever counter

value changes, an QDEC IRQ is asserted and address 0xd5[0] is set to 1b’1

automatically.Writing1b’1toaddress0xd5[0]cancleartheinterruptflagbit.

9.5 QDECreset

Address0xd6[0]servestoresettheQDEC.TheQDECCountervalueisclearedto

zero.

9.6 Otherconfiguration

The QDEC supports hardware debouncing. Address 0xd1[2:0] serves to set

filteringwindowduration.Alljitterwithperiodlessthanthevaluewillbefilteredout

andthusdoesnottriggercountchange.

Address0xd1[4]servestosetinputsignalinitialpolarity.


DS-ST17H30Q-E15 60 Ver2.4.0

Address 0xd1[5] serves to enable shuttle mode. Shuttle mode allows

non-overlappingtwophasesignalsasshowninthefollowingfigure.

Figure9-4 Shuttlemode

9.7 Registertable

Table9-2 RegistertableforQDEC

Address Mnemonic Type DescriptionResetvalue

0xd0 QDEC_COUNT RQDECCountingvalue(readtoclear):Pulseedgenumber

0xd1 QDEC_CC R/W

[2:0]:filtertime(canfilter2^n*clk_32k*2 widthdeglitch)[4]:pola,inputsignalpola0:nosignalislow,1:nosignalishigh[5]:shuttlemode 1toenableshuttlemode

0xd2 QDEC_CHNA0 R/W[4:0]QDEC0inputpinselectforchannelachoose1of6pinsforinputchannela

0x00

0xd3 QDEC_CHNB0 R/W[4:0] QDEC0 input pin select for channel bchoose1of6pinsforinputchannelb

0x01

0xd4 QDEC_MASK R/W[0]Interruptmask1:enable0:mask

0x00

0xd5 QDEC_INT R[0]InterruptflagWrite1toclear

0xd6 QDEC_RST R/W [0]Write1toresetQDEC 0x0

0xd7 QDEC_DOUBLE R/W [0]Enabledoubleaccuracymode 0x0

0xd8 DATA_LOAD R/W[0]write1toloaddatawhenloadcompletesitwillbe0


DS-ST17H30Q-E15 61 Ver2.4.0

10 SARADC

TheST17H30QintegratesoneADCmodule,whichcanbeusedtosamplebattery

voltageandexternalanaloginput.

10.1 Registertable

Table10-1 RegistertableforSARADC

Address Mnemonic Type DescriptionReset

Value

DigitalRegisters

0x2b ADCREF RW

[0]selectreference0:Vbg 1:VDDH[7:1]rsvd

0x03

0x2c ADCMUXM RW

Analoginputsselectbit[2:0]selanainput000:closeall 001:GP17 010:GP18 011:GP22 100:GP23 101:VDDDEC110: VGP23 or 1/3*VGP23. Refer to analogregisterafe3V_reg02<3>.111:reserved[5:4]seldifinput choose single or diff mode and selectnegativeinput00:singlemode 01:GP18asnegativeinput10:GP23asnegativeinput11:VDDDECasnegativeinput

0x02

0x35 ADC_RUN R/W [7]manualmoderunsignal 0

0x38 ADC_DAT[7:0] R

0x39 ADC_DAT[9:8] R[1:0]ADC_DAT[9:8][6:2]rsvd[7]adc_busy

0x3c ADCTSAPM RW[2:0] Select number of clock cycles for ADCsampling

0x00


DS-ST17H30Q-E15 62 Ver2.4.0

Address Mnemonic Type DescriptionReset

Value

Setting #ofclockcycles 000 3001 6 010 9 011 12 100 18 101 24 110 48 111 144

[4:3]ADCresolutionselect00:7bit 01:8bit 10:9bit 11:10bit[5]SelectsignofADCoutputdatabit<9>0:positive 1:negative

Analogregisters

afe3V_reg

06<0>PowerDown RW

PowerdownSARADC1:Powerdown0:Powerup

1

afe3V_reg

02<3>

power_logic_sel

_atbRW

Select VGP23or 1/3*VGP23as ADC input (refertodigitalregister0x2c[2:0]).0:VGP231:1/3*VGP23

0

10.2 SARADCclock

ADCclockderivesfromFHS.Address0x6b[7]shouldbesetto“1”toenableADC

clock.

ADC clockmust be lower than 5Mwhen ADC reference voltage is selected as

VDDHandmustbelowerthan4MwhenADCreferencevoltageisselectedasVbg.

ADCclockiscalculatedaccordingtotheformulabelow:

F"#$&'(&) = F+,- ∗ adc_step[10: 0]/adc_mod[11: 0]

RefertoSection5.2.1 SARADCclockfordetails.

10.3 SelectADCrange,resolutionandsamplingtime

ADCrangeissameastheADCreferencevoltage,whichisconfiguredbyregister


DS-ST17H30Q-E15 63 Ver2.4.0

0x2b[0]:Vbg(1.26Vbandgapreference),orVDDH.

Address 0x3c[4:3] serves to set resolution: 7bit, 8bit, 9bit or 10bit. ADC data

format isalways10bitnomattertheconversionbit isset.Address0x3c[5]servesto

set the sign of ADC output data bit[9] as positive or negative. For example, 8 bits

resolutionindicateshigher8bitsarevalidbitsandthelower2bitsareinvalidbits.

ADCsamplingtimecanbeconfiguredbyaddress0x3c[2:0], the lowersampling

cycle,theshorterADCconverttime.

10.4 Selectinputmodeandchannel

TheST17H30QADChasupto4inputchannelwhichcanbeselectedbyaddress

0x2c[2:0].

Address0x2c[5:4]servestoselectdifferentialmodeorsingle-endinputmode.

When address 0x2c[5:4] is set to 2b’00 to select single-end mode, 0x2c[2:0]

servestoselectinputchannel.

For example, if address 0x2c is set to 0x06 (i.e. 8b’ 00000110), and analog

register afe3V_reg02<3> is set to 1b’1, 1/3*VGP23 is selected as ADC input of

single-endmode.

Whenaddress0x2c[5:4]issetto2b’01/2b’10/2b’11,differentialmodeisselected,

the corresponding channel identified by address 0x2c[5:4] is selected as negative

input,andthepositiveinputisselectableviaaddress0x2c[2:0].

Forexample,ifaddress0x2cissetto0x11(i.e.8b’00010001),GP17andGP18are

selected as positive-end and negative-end input of differential mode; actual input

signalforADCisthedifferenceofVGP17andVGP18(i.e.VGP17minusVGP18).

10.5 ADCstart

Address0x35[7]setto“1”startsADCsamplingandconversionprocess.

10.6 ADCstatus

ADCbusyflagbit,i.e.address0x39[7],indicateswhetherADCisbusy.


DS-ST17H30Q-E15 64 Ver2.4.0

10.7 ADCdata

TherealtimeoutputdataADC_DAT[9:0]canbereadfromaddresses0x39~0x38.

11 PWM

TheST17H30Qsupportsupto4-channelPWM(Pulse-Width-Modulation)output.

PWM#n_INVindicatesinvertedoutputcorrespondingtoPWM#n.

11.1 Registertable

Table11-1 RegistertableforPWM


Value

0x780 PWM_EN R/W

[0]: 0--disable PWM0, 1--enable PWM0




0x00

0x781 PWM_CLK R/W (PWM_CLK+1)*sys_clk 0x00

0x782 PWM_MODE R/W[1:0]: 00-pwm0 normal mode[1:0]: 01-pwm0 count mode[1:0]: 11-reserved

0x00

0x783 PWM_CC0 R/W [3:0]:1‘b1 invert PWM output 0x000x784 PWM_CC1 R/W [3:0]:1‘b1 invert PWM_INV output 0x000x785 PWM_CC2 R/W [3:0]:1’b1 PWM’ pola,low level first 0x00

0x788 PWM_PHASE0 R/W [7:0] bits 7-0 of PWM0's phase time 0x000x789 PWM_PHASE0 R/W [15:8] bits 15-8 of PWM0's phase time 0x000x78a PWM_PHASE1 R/W [7:0] bits 7-0 of PWM1's phase time 0x000x78b PWM_PHASE1 R/W [7:8] bits 15-8 of PWM1's phase time 0x000x78c PWM_PHASE2 R/W [7:0] bits 7-0 of PWM2's phase time 0x000x78d PWM_PHASE2 R/W [15:8] bits 15-8 of PWM2's phase time 0x000x78e PWM_PHASE3 R/W [7:0] bits 7-0 of PWM3's phase time 0x000x78f PWM_PHASE3 R/W [15:8] bits 15-8 of PWM3's phase time 0x00

0x794 PWM_TCMP0 R/W[7:0] bits 7-0 of PWM0's high time or low

time(if pola[0]=1) 0x00

0x795 PWM_TCMP0 R/W[15:8] bits 15-8 of PWM0's high time or

low time 0x00

0x796 PWM_TMAX0 R/W [7:0] bits 7-0 of PWM0's cycle time 0x000x797 PWM_TMAX0 R/W [15:8] bits 15-8 of PWM0's cycle time 0x00


DS-ST17H30Q-E15 65 Ver2.4.0


Value

0x798 PWM_TCMP1 R/W[7:0] bits 7-0 of PWM1's high time or low


0x799 PWM_TCMP1 R/W[15:8] bits 15-8 of PWM1's high time or

low time 0x00

0x79a PWM_TMAX1 R/W [7:0] bits 7-0 of PWM1's cycle time 0x000x79b PWM_TMAX1 R/W [15:8] bits 15-8 of PWM1's cycle time 0x00

0x79c PWM_TCMP2 R/W[7:0] bits 7-0 of PWM2's high time or low


0x79d PWM_TCMP2 R/W[15:8] bits 15-8 of PWM2's high time or

low time 0x00

0x79e PWM_TMAX2 R/W [7:0] bits 7-0 of PWM2's cycle time 0x000x79f PWM_TMAX2 R/W [15:8] bits 15-8 of PWM2's cycle time 0x00

0x7a0 PWM_TCMP3 R/W[7:0] bits 7-0 of PWM3's high time or low


0x7a1 PWM_TCMP3 R/W[15:8] bits 15-8 of PWM3's high time or

low time 0x00

0x7a2 PWM_TMAX3 R/W [7:0] bits 7-0 of PWM3's cycle time 0x000x7a3 PWM_TMAX3 R/W [15:8] bits 15-8 of PWM3's cycle time 0x000x7ac PWM_PNUM0 R/W [7:0]PWM0 Pulse num in count mode 0x000x7ad PWM_PNUM0 R/W [15:8] 0x00

0x7b0 PWM_MASK R/W

INT mask [0] PWM0 Pnum int 0: disable 1: Enable [1] rsvd [2] PWM0 frame int 0: disable 1: Enable [3] PWM1 frame int 0: disable 1: Enable [4] PWM2 frame int 0: disable 1: Enable [5] PWM3 frame int 0: disable 1: Enable [7:6] rsvd

0x00

0x7b1 PWM_INT R/W

INT status ,write 1 to clear[0]:PWM0 pnum int(have sent PNUM pulse,PWM_NCNT==PWM_PNUM)[1]:rsvd[2]:PWM0 cycle done int(PWM_CNT==PWM_TMAX)

0x00


DS-ST17H30Q-E15 66 Ver2.4.0


Value

[3]:PWM1 cycle done int(PWM_CNT==PWM_TMAX)[4]:PWM2 cycle done int(PWM_CNT==PWM_TMAX)[5]:PWM3 cycle done int(PWM_CNT==PWM_TMAX)[7:6]: rsvd

0x7b4 PWM_CNT0 R [7:0]PWM 0 cnt value 0x7b5 PWM_CNT0 [15:8]PWM 0 cnt value 0x7b6 PWM_CNT1 R [7:0]PWM 1 cnt value 0x7b7 PWM_CNT1 [15:8]PWM 1 cnt value 0x7b8 PWM_CNT2 R [7:0]PWM 2 cnt value 0x7b9 PWM_CNT2 [15:8]PWM 2 cnt value 0x7ba PWM_CNT3 R [7:0]PWM 3 cnt value 0x7bb PWM_CNT3 [15:8]PWM 3 cnt value 0x7c0 PWM_NCNT0 R [7:0]PWM0 pluse_cnt value 0x7c1 PWM_NCNT0 [15:8]PWM0 pluse_cnt value

11.2 EnablePWM

Register PWM_EN (address 0x780)[3:0] serves to enable PWM3~PWM0

respectivelyviawriting“1”forthecorrespondingbits.

11.3 SetPWMclock

PWMclockderivesfromsystemclock.RegisterPWM_CLK(address0x781)serves

tosetthefrequencydividingfactorforPWMclock.Formulabelowapplies:

FPWM=FSystemclock/(PWM_CLK+1)

11.4 PWMwaveform,polarityandoutputinversion

EachPWMchannelhasindependentcounterandthreestatusincluding“Delay”,

“Count”and“Remaining”.CountandRemainingstatusformasignalframe.


DS-ST17H30Q-E15 67 Ver2.4.0

11.4.1 PWMwaveform

When PWM#n is enabled, PWM#n enters Delay status. By default PWM#n

outputs Low level at Delay status. The Delay status duration, i.e. Phase time, is

configured in register PWM_PHASE#n (address 0x788~0x78f). Phase difference

betweenPWMchannelsisallowedbydifferentphasetimeconfiguration.

After Phase time expires, PWM#n exits Delay status and starts to send signal

frames.FirstPWM#nisatCountstatusandoutputsHighlevelsignalbydefault.When

PWM#ncounterreachescyclessetinregisterPWM_TCMP#n(address0x794~0x795,

0x798~0x799, 0x79c~0x79d, 0x7a0~0x7a1), PWM#n enters Remaining status and

outputs Low level till PWM#n cycle time configured in register PWM_TMAX#n

(address0x796~0x797,0x79a~0x79b,0x79e~0x79f,0x7a2~0x7a3)expires.

Aninterruptionwillbegeneratedattheendofeachsignalframeifenabledvia

registerPWM_MASK(address0x7b0[2:5]).

11.4.2 InvertPWMoutput

PWM#n and PWM#n_INV output could be inverted independently via register

PWM_CC0 (address 0x783[3:0]) and PWM_CC1 (address 0x784[3:0]). When the

inversionbit isenabled, thecorrespondingPWMchannelwaveformwillbe inverted

completely.

11.4.3 Polarityforsignalframe

By default, PWM#n outputs High level at Count status and Low level at

Remaining status. When the corresponding polarity bit is enabled via register

PWM_CC2 (address 0x785[3:0]), PWM#nwill output Low level at Count status and

HighlevelatRemainingstatus.


DS-ST17H30Q-E15 68 Ver2.4.0

Figure11-1 PWMoutputwaveformchart

11.5 PWMmode

11.5.1 SelectPWMmode

PWM0 supports 2 modes, including Continuous (normal) mode and Counting

mode.PWM1~PWM3onlysupportContinuousmode.

RegisterPWM_MODE(address0x782[1:0])servestoselectPWM0mode.

11.5.2 Continuousmode

PWM0~PWM3allsupportContinuousmode.Inthismode,PWM#ncontinuously

sends out signal frames. PWM#n should be disabled via address 0x780 to stop it;

whenstopped,thePWMoutputwillturnlowimmediately.

DuringContinuousmode,waveformcouldbechangedfreely.Newconfiguration

forPWM_TCMP#nandPWM_TMAX#nwilltakeeffectinthenextsignalframe.

A frame interruption will be generated (if enabled) after each signal frame is

finished.

Figure11-2 Continuousmode


DS-ST17H30Q-E15 69 Ver2.4.0

11.5.3 Countingmode

OnlyPWM0supportsCountingmode. In thismode,PWM0sendsoutspecified

numberofsignalframeswhichisdefinedasapulsegroup.Thenumberisconfigured

via register PWM_PNUM0 (address 0x7ac~0x7ad). After a pulse group is finished,

PWM0will be disabled automatically, and a Pnum interruptionwill be generated if

enabledviaregisterPWM_MASK(address0x7b0[0]).Int

Int

Int

CountingMode

Pnum

_int

Delay

DelayCountingModewithInvert=High

PWM_EN[0]willbeclearedaftersendingPNUM0pulses

Puslegroup(PWM_PNUM0pulses)

SignalFrame SignalFrame SignalFrame

Figure11-3 Countingmode

11.6 PWMinterrupt

There are 5 interrupt sources from PWM function. After each signal frame,

PWM#nwillgenerateaframe-doneIRQ(InterruptRequest)signal.InCountingmode,

PWM0 will generate a Pnum IRQ signal after completing a pulse group. Interrupt

statuscanbeclearedviaregisterPWM_INT(address0x7b1).

12 KeyElectricalSpecifications

12.1 Absolutemaximumratings

Table12-1 AbsoluteMaximumRatings

Characteristics Sym. Min. Max Unit TestCondition


DS-ST17H30Q-E15 70 Ver2.4.0

SupplyVoltage VDD -0.3 3.9 VAll AVDD and DVDD pinmusthavethesamevoltage

VoltageonInputPin VIn -0.3VDD+0.3

V

OutputVoltage VOut 0 VDD V

Storage temperatureRange

TStr -65 150 oC

SolderingTemperature TSld 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operationalsectionsofthisspecificationisnotimplied.

12.2 Recommendedoperatingcondition

Table12-2 Recommendedoperationcondition

Item Sym. Min Typ. Max Unit Condition

Power-supplyvoltage VDD 1.9 3.3 3.6 V

OperatingTemperatureRange

TOpr -40 27 85 oC

12.3 DCcharacteristics

Table12-3 DCcharacteristics


Txcurrent ITx

- 15 - mAContinuousTxtransmission

@0dBmoutputpower

- 22 - mAContinuousTxtransmission

@maximumoutputpower


DS-ST17H30Q-E15 71 Ver2.4.0

Rxcurrent IRx - 12 - mA ContinuousRxreception

Suspendcurrent ISusp - 10 - uA

Deepsleepcurrent IDeep - 0.7 - uA

*Note:Alltestsabovearedoneatroomtemperature(T=25℃).

12.4 ACcharacteristics

Table12-4 ACCharacteristics


Digitalinputs/outputs

Inputhighvoltage VIH 0.7VDD VDD V

Inputlowvoltage VIL VSS 0.3VDD V

Outputhighvoltage VOH VDD-0.3 VDD V

Outputlowvoltage VOL VSS 0.3 V

RFperformance(1Mbps)

Item Min Typ Max Unit

RF_Rxperformance

Sensitivity 1Mbps -94 dBm

FrequencyOffset

Tolerance -300 300 KHz

Co-channelrejection -3 dB

In-bandblocking

rejection

±1MHz

offset 3 dB


DS-ST17H30Q-E15 72 Ver2.4.0


(SingleTone

Interference)

-2MHz

offset 33 dB

+2MHz

offset 30 dB

-3MHz

offset 33 dB

+3MHz

offset 34 dB

>4MHz

offset 35 dB

In-bandblocking

rejection

(EqualModulation

Interference)

±1MHz

offset -3 dB

-2MHz

offset 26 dB

+2MHz

offset 22 dB

-3MHz

offset 31 dB

+3MHz

offset 35 dB

>4MHz

offset 32 dB

Imagerejection 44 dB

RF_Txperformance

Outputpower 6 dBm

Modulation20dB

bandwidth 1.3 MHz


DS-ST17H30Q-E15 73 Ver2.4.0


16MHzcrystal

Nominal frequency

(parallelresonant)fNOM

16 MHz

Frequencytolerance fTOL -60 +60 ppm

Loadcapacitance CL 5 12 18 pFProgrammableon

chiploadcap

Equivalent series

resistanceESR 50 100 ohm

32MHzRCoscillator

Nominalfrequency fNOM 32 MHz

Frequencytolerance fTOL 1 %

Onchip

calibration

32kHzRCoscillator

Nominalfrequency fNOM 32 kHz

Frequencytolerance fTOL 0.03 %

Onchip

calibration

Calibrationtime 3 ms

ADC

Differential

nonlinearityDNL 0.8 LSB

Integralnonlinearity INL 0.7 LSB

Signal-to-noise and

distortion ratio

(fin=1kHz,fS=16kHz)

SINAD 57.8 dB

Spurious free SFDR 64.5 dB


DS-ST17H30Q-E15 74 Ver2.4.0


dynamic range

(fin=1kHz,fS=16kHz)

Effective Number of

BitsENOB 9.2 bits

Samplingfrequency Fs

250 KHz VDDHreference

200 KHz Vbgreference


DS-ST17H30Q-E15 75 Ver2.4.0

13 Application

13.1 ApplicationexamplefortheST17H30QET24

13.1.1 Schematic


DS-ST17H30Q-E15 76 Ver2.4.0

Figure13-1 SchematicfortheST17H30QET24


DS-ST17H30Q-E15 77 Ver2.4.0

13.1.2 Layout

Figure13-2 LayoutfortheST17H30QET24

13.1.3 BOM(BillofMaterial)

Table13-1 BOMtablefortheST17H30QET24

Quantity Reference Value Spec

5

C26 1uF 0402C27 1uF 0402C28 1uF 0402C30 1uF 0402C31 1uF 0402

1 C29 10uF 0603

2R4 0 0402R5 0 0402

2R7 3.3K 0402R8 3.3K 0402

1 U2 FM24C04B FM24C04B

1 U4 ST17H30QET24 ST17H30QET241 Y1 12MHZ OSC_25x32_+/-20ppm_12pF_4pin

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