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8x8 SRAM

Wing ChanMahavir ShethJunghoon Kang

Shalin Shah

Advisor: Dave Parent12/6/04

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Agenda

• Abstract • Introduction

– Simple Theory– Back Ground information

• Summary of Results• Project Details• Results• Cost Analysis• Conclusions

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Abstract

• We designed an 8x8 SRAM that operates at 200Mhz and uses 15.2mW of power and occupies an area of

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Introduction

• The SRAM project helped us understand the IC design process (schematic and layout) keeping in mind the delay, power, and area specifications.

• SRAM is a 6-transistor bistable latch that stores one of the two possible states as long as power supply is provided.

• Equations used:

bit bit_b

word

7.0

3

5

LWLW

34.0

1

3

LWLW

1

5 63

2

4

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Project Details

• The SRAM Circuit is a 8 bit 64 cell in a standard 8 column by 8 row design.

• Each Row of the cell is selected by the 3 x 8 decoder.

• The Data is read in at the positive edge of the clock from the DFF and feed into the 8 input lines.

• Each Row has two write circuits that writes to the bit lines and inverted bit lines that provides the voltages for the sense amplifier for reading when read enable is selected.

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Power = 6.08mA * 2.5V

= 15.2mW

nsnsPHL 42.0

125

Total delay: 3.7ns

Area = 273µcm x 495µcm

=0.135µ cm2

Or 0.11W/µcm2

Calculated:

Observed:

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Longest Path CalculationsLogic Gate Cg to #C

DNs

#CDPs

#LNs #LPs

WN WP WN WP WN WP Cg to

Level Drive (H.C) (H.C) (S) (S) (L) (L) Gate

1 Decoder                        

2 Inv 20.3fF 1 1 1 1 5.55 3.3 6.3 4.35 7.05 4.95 18.3fF

3 Nand3 16fF 5 3 3 1 4.95 4.8 5.3 5.5 6 6 20.3fF

4 InvBuffer 80fF 1 1 1 1 4.55 2.55 5 3.35 5.4 4.05 16fF

5 DFF 30fF             2.62 4.54 2.62 4.54 8.2fF

                  2.69 2.33 2.69 2.33  

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Schematic

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Schematic

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Schematic

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Layout

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Verification

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Simulations

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Cost Analysis

– Spend over 50 hrs verifying circuit logic and timing.

– Over 100 hrs doing layout and post extract simulation.

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Lessons Learned

• Post extract simulation does not always matches the schematic circuit even when LVS matches-specially if there are analog circuit components.

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Summary• The SRAM project covers many areas that’s important to

learning IC design-from timing verification to layout. RESULT: - schematic simulation showed correct logic for the

SRAM - meets timing specification of 5ns - meets power specification of 23mW(15.2mW) - LVS matches the layout with schematic successfully

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Post extracted simulation does not charge and discharge to correct logic.

POSSIBLE REASONS:

- larger than expected capacitance on the bit lines to charge up

- needs pre-charge bit lines before each read cycle.

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Acknowledgements

• Thanks to Synopsys for Software donation• Professor Parent