Spring 2016, Jan 13 ELEC 5200-001/6200-001 Lecture 1 1 ELEC 5200-001/6200-001 Computer Architecture...

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Spring 2016, Jan 13 Spring 2016, Jan 13 ELEC 5200-001/6200-001 ELEC 5200-001/6200-001 Lecture 1 Lecture 1 1 ELEC 5200-001/6200-001 ELEC 5200-001/6200-001 Computer Architecture and Computer Architecture and Design Design Spring 2016 Spring 2016 Introduction Introduction Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor Department of Electrical and Computer Department of Electrical and Computer Engineering Engineering Auburn University, Auburn, AL 36849 Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal http://www.eng.auburn.edu/~vagrawal [email protected] [email protected]

description

Spring 2016, Jan 13 ELEC / Lecture 1 3 Course Organization Text book: D. A. Patterson and J. L. Hennessy, Computer Organization & Design, the Hardware/Software Interface, Fifth Edition, Morgan Kaufman (Elsevier), 2014, ISBN Instructor: Vishwani D. Agrawal, Broun 323, x41853, Graduate Assistant: Yun Wang, Broun 357, consulting hours: Friday 3-5PM. Classroom: Broun 235, MWF 11:00-11:50AM. Lab: Broun 320.

Transcript of Spring 2016, Jan 13 ELEC 5200-001/6200-001 Lecture 1 1 ELEC 5200-001/6200-001 Computer Architecture...

Page 1: Spring 2016, Jan 13 ELEC 5200-001/6200-001 Lecture 1 1 ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2016 Introduction Vishwani D. Agrawal.

Spring 2016, Jan 13Spring 2016, Jan 13 ELEC 5200-001/6200-001 Lecture 1ELEC 5200-001/6200-001 Lecture 1 11

ELEC 5200-001/6200-001ELEC 5200-001/6200-001Computer Architecture and DesignComputer Architecture and Design

Spring 2016Spring 2016IntroductionIntroduction

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal

[email protected]@eng.auburn.edu

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Course WebpageCourse Webpagehttp://www.eng.auburn.edu/http://www.eng.auburn.edu/~vagrawal/COURSE/E6200_Spr16/~vagrawal/COURSE/E6200_Spr16/course.htmlcourse.htmlOr,Or,

Go to professor’s webpage Go to professor’s webpage http://www.eng.auburn.edu/~vagrawal/http://www.eng.auburn.edu/~vagrawal/Click on ELEC5200-001/6200-001 Computer Click on ELEC5200-001/6200-001 Computer Architecture and Design, MWF 11AM, Broun Architecture and Design, MWF 11AM, Broun 235. 235.

Spring 2016, Jan 13Spring 2016, Jan 13 ELEC 5200-001/6200-001 Lecture 1ELEC 5200-001/6200-001 Lecture 1 22

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Course OrganizationCourse OrganizationText book: D. A. Patterson and J. L. Hennessy, Text book: D. A. Patterson and J. L. Hennessy, Computer Computer Organization & Design, the Hardware/Software InterfaceOrganization & Design, the Hardware/Software Interface, , Fifth EditionFifth Edition, Morgan Kaufman (Elsevier), 2014, ISBN 978-0-, Morgan Kaufman (Elsevier), 2014, ISBN 978-0-12-407726-3.12-407726-3.Instructor: Vishwani D. Agrawal, Broun 323, x41853, Instructor: Vishwani D. Agrawal, Broun 323, x41853, [email protected]@eng.auburn.edu. . Graduate Assistant: Yun Wang, Graduate Assistant: Yun Wang, [email protected], Broun 357, consulting [email protected], Broun 357, consulting hours: Friday 3-5PM.hours: Friday 3-5PM.Classroom: Broun 235, MWF 11:00-11:50AM.Classroom: Broun 235, MWF 11:00-11:50AM.Lab: Broun 320.Lab: Broun 320.

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Author of the Text BookAuthor of the Text Book

Spring 2016, Jan 13Spring 2016, Jan 13 ELEC 5200-001/6200-001 Lecture 1ELEC 5200-001/6200-001 Lecture 1 44

Q&A: RISC and Reward, Communications of the ACM,Volume 57, No. 3, pp. March 2014, pages 112 and 111.

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Author of the Text BookAuthor of the Text Book

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Student Performance EvaluationStudent Performance EvaluationHomework (25%): 1 per week, most weeks.Homework (25%): 1 per week, most weeks.Two Class Tests (25%):Two Class Tests (25%):

Test 1, TBD, 11:00-11:50AM, Broun 235.Test 1, TBD, 11:00-11:50AM, Broun 235.Test 2, TBD, 11:00-11:50AM, Broun 235.Test 2, TBD, 11:00-11:50AM, Broun 235.

CPU Design Project (25%).CPU Design Project (25%).Final Exam (25%): Tuesday, May 3, 2016, 12:00 – Final Exam (25%): Tuesday, May 3, 2016, 12:00 – 2:30PM, Broun 235.2:30PM, Broun 235.Class Presentation, if time permits, on assigned Class Presentation, if time permits, on assigned topic by ELEC6200 Students; “Satisfactory” grade topic by ELEC6200 Students; “Satisfactory” grade necessary; attendance necessary for ELEC5200 necessary; attendance necessary for ELEC5200 students. students.

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Course ObjectiveCourse Objective

Learn Learn whatwhat a digital computer contains a digital computer contains and and howhow it works. it works.Learn Learn design conceptsdesign concepts of a modern of a modern computer.computer.Gain design experience (through project).Gain design experience (through project).

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The Concept of a ComputerThe Concept of a Computer

Application software

Programs userwrites and runs

Hardware

Systems software

Operating systemcompiler

assembler

User

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SoftwareSoftware

Application software,a program in C:

swap (int v[ ], int k){int temp;

temp = v[k];v[k] = v[k+1];v[k+1] = temp;

}

MIPS binary machine code:

00000000101000010000000000011000000000000001100000011000001000011000110001100010000000000000000010001100111100100000000000000100101011001111001000000000000000001010110001100010000000000000010000000011111000000000000000001000

Compiler Assembler

Application software

Hardware

Systems software

See pages 122-123

MIPS compiler output,assembly language program:

swap;muli $2, $5, 4add $2, $4, $2lw $15, 0 ($2)lw $16, 4 ($2)sw $16, 0 ($2)sw $15, 4 ($2)jr $31

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The Hardware of a ComputerThe Hardware of a Computer

Control

Datapath MemoryCentral Processing

Unit (CPU)or “processor”

Input

Output

FIVE EASY PIECES

Application software

Hardware

Systems software

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Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)A set of assembly language instructions (ISA) A set of assembly language instructions (ISA) provides a link between software and hardware.provides a link between software and hardware.Given an instruction set, software programmers Given an instruction set, software programmers and hardware engineers work more or less and hardware engineers work more or less independently.independently.ISA is designed to extract the most performance ISA is designed to extract the most performance out of the available hardware technology.out of the available hardware technology.

Inst

ruct

ion

setSoftware Hardware

Application software

Hardware

Systems software

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ISAISADefines registersDefines registersDefines data transfer modes between registers, Defines data transfer modes between registers, memory and I/Omemory and I/OTypes of ISA: RISC, CISC, VLIW, SuperscalarTypes of ISA: RISC, CISC, VLIW, SuperscalarExamples:Examples:– IBM370/X86/Pentium/K6 (CISC)IBM370/X86/Pentium/K6 (CISC)– PowerPC (Superscalar)PowerPC (Superscalar)– Alpha (Superscalar)Alpha (Superscalar)– MIPS (RISC and Superscalar)MIPS (RISC and Superscalar)– Sparc (RISC), UltraSparc (Superscalar)Sparc (RISC), UltraSparc (Superscalar)

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Computer Computer ArchitectureArchitecture

Architecture: System attributes that have a Architecture: System attributes that have a direct impact on the logical execution of a direct impact on the logical execution of a programprogramArchitecture is visible to a programmer:Architecture is visible to a programmer:– Instruction setInstruction set– Data representationData representation– I/O mechanismsI/O mechanisms– Memory addressingMemory addressing

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Computer Computer OrganizationOrganization

Organization: Physical details that are Organization: Physical details that are transparent to a programmer, such astransparent to a programmer, such as– Hardware implementation of an instructionHardware implementation of an instruction– Control signalsControl signals– Memory technology usedMemory technology used

Example: System/370 architecture has Example: System/370 architecture has been used in many IBM computers, which been used in many IBM computers, which widely differ in their organization.widely differ in their organization.

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Architecture and OrganizationArchitecture and Organization

SoftwareProgrammers

HardwareEngineers

ISA

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CPU Design ProjectCPU Design ProjectDesign and implementation of a Design and implementation of a processor:processor:– Define instruction setDefine instruction set– Design datapath and control hardwareDesign datapath and control hardware– Implement hardware in FPGAImplement hardware in FPGA– VerifyVerify

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Research and Developments of Research and Developments of Continuing InterestContinuing Interest

Instruction level parallelism (ILP)Instruction level parallelism (ILP)Multi-core systems and chip multi-processing (CMP)Multi-core systems and chip multi-processing (CMP)

ProcessorsProcessorsInter-processor communicationInter-processor communicationMemory organizationMemory organizationOperating systemOperating systemProgramming languagesProgramming languagesComputing algorithmsComputing algorithms

Energy efficiency and low power designEnergy efficiency and low power designEmbedded systemsEmbedded systemsQuantum computing, biological computing, . . .Quantum computing, biological computing, . . .

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SummarySummaryA computer processes digital data.A computer processes digital data.A user solves problems by writing and running programs A user solves problems by writing and running programs written in a written in a high-level programming languagehigh-level programming language like C. like C.Inside computer, Inside computer, system programssystem programs called called compilercompiler and and assemblerassembler break the user program down into assembly break the user program down into assembly code (code (instruction setinstruction set) and then into binary machine code.) and then into binary machine code.The machine code is processed by the 5-piece hardware The machine code is processed by the 5-piece hardware (control unit, datapath, memory, input and output) to (control unit, datapath, memory, input and output) to obtain the desired result.obtain the desired result.Readings on architecture (posted at course website):Readings on architecture (posted at course website):– S. Borkar and A. A. Chen, “The Future of Microprocessors,” S. Borkar and A. A. Chen, “The Future of Microprocessors,”

Comm. ACMComm. ACM, vol. 54, no. 5, pp. 67-77, May 2011., vol. 54, no. 5, pp. 67-77, May 2011.– L. Hoffmann, “Q&A: RISC and Reward (An Interview with David L. Hoffmann, “Q&A: RISC and Reward (An Interview with David

Patterson),” Patterson),” Comm. ACMComm. ACM, vol. 57, no. 3, pp. 112, 111, March , vol. 57, no. 3, pp. 112, 111, March 2014.2014.