Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 1 ELEC 5200-001/6200-001 Computer Architecture...

Spr 2015, Mar 13 . . .Spr 2015, Mar 13 . . . ELEC 5200-001/6200-001 Lecture 8ELEC 5200-001/6200-001 Lecture 8 11

ELEC 5200-001/6200-001ELEC 5200-001/6200-001Computer Architecture and DesignComputer Architecture and Design

Spring 2015Spring 2015

Microprogramming (Appendix D)Microprogramming (Appendix D)

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

http://www.eng.auburn.edu/[email protected]


Alternatives for Control Unit (CU)Alternatives for Control Unit (CU)Hard-wired (hardware)Hard-wired (hardware)– Random logic, programmable logic array (PLA), or ROMRandom logic, programmable logic array (PLA), or ROM– FastFast– InflexibleInflexible

FirmwareFirmware– Microprogrammed or microcoded CUMicroprogrammed or microcoded CU– Control implemented like a computer (microcomputer)Control implemented like a computer (microcomputer)

MicroinstructionsMicroinstructionsMicroprogramMicroprogram

– FlexibleFlexibleSoftware-like changes to instruction set possibleSoftware-like changes to instruction set possibleCompletely different instruction sets can be emulatedCompletely different instruction sets can be emulated

– Speed limited by microcomputer memorySpeed limited by microcomputer memory

26-31 toControl

FSM


Multicycle DatapathMulticycle DatapathP

C

Inst

r.

reg

. (I

R)

Mem

. D

ata

(MD

R)

AL

UO

ut

Reg

.

A R

eg.

B R

eg.

A

LU

Reg

iste

r fi

le

Mem

ory

Ad

dr.

Data

4

Sign extend

Shift left 2

ALUcontrol

0-5

0-15

16-2021-25

IorD

MemtoReg

ALUOp

AL

US

rcB

AL

US

rcA

RegDstIRWrite

RegWrite

MemWrite

MemRead

Shift left 20-25

28-31

PCSource

PC

Wri

te e

tc.

11

-15


Multicycle Control FSMMulticycle Control FSM

Instr. decode/reg.

fetch/branch

addr.

ALU operation

Write PC on branch condition

Write memory

data

Write jump addr.

to PC

Write register

Read memory

data

Instr. fetch/

adv. PC

Compute memory

addr.

Write register

lw or sw

lw

sw

RB

J

Start

State 0 1

23

4 5

6

7

8 9

Inputs: 6 opcode bitsOutputs: 16 control signals


States and OutputsStates and OutputsSuppose 10 states are encoded 0000 through 1001.Suppose 10 states are encoded 0000 through 1001.State code completely determines 16 control signals State code completely determines 16 control signals (Moore machine).(Moore machine).States 0 (0000), 3 (0011) and 6 (0110)States 0 (0000), 3 (0011) and 6 (0110)

Next state ← present state + 1Next state ← present state + 1

State 1 (0001) – opcode determines next stateState 1 (0001) – opcode determines next stateState 2 (0010) for lw or swState 2 (0010) for lw or swState 6 (0110) for R-type of instructionState 6 (0110) for R-type of instructionState 8 (1000) for branch instructionState 8 (1000) for branch instructionState 9 (1001) for jump instructionState 9 (1001) for jump instruction

State 2 (0010) – opcode determines next stateState 2 (0010) – opcode determines next stateState 3 (0011) for lwState 3 (0011) for lwState 5 (0101) for swState 5 (0101) for sw

States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 (1001) – next state is unconditionally 0 (0000)(1001) – next state is unconditionally 0 (0000)


A Program-Like ImplementationA Program-Like Implementation

Instr. decode/reg.

fetch/branch

addr.

ALU operation

Read memory

data

Instr. fetch/

adv. PC

lw or sw

lw

sw

RB

J

Start

State 0000 0001

00100011

0100 0101

0110

01111000 1001


Compute memory

addr.

Write jump addr.

to PC

Write register

Write memory

data

Write register



Implementing with ROMImplementing with ROM

ControlPLA or ROM

16 words

Four flip-flops

16 control signals

PLA input orROM address

6-bit opcode

State sequencer

Select one of 4 ways

16

2

4

6


ROM and State SequencerROM and State SequencerControl ROM

Sixteen18-bit words4-bit address

4-bit state flip-flops

16

2

Controlsignals to datapath

4 4

0001

MUX11 10 01 00

0000

AddrCtl go to00 st. 011 st. + 101 st.

2,6,8,910 st. 3,5

Dispatch ROM 2 Dispatch ROM 1

Adder

6

6-bitOpcode from IR

Address

Advance state4

ROM Address sw, lw, R, B or J

sw or lw


Dispatch ROM ContentsDispatch ROM Contents

Dispatch ROM 1Dispatch ROM 1

InstructionInstruction AddressAddress

(Opcode)(Opcode)

ContentContent

lwlw 100011100011 00100010

swsw 101011101011 00100010

RR 000000000000 01100110

BB 000100000100 10001000

JJ 000010000010 10011001

Each dispatch ROM has sixty-four 4-bit wordsAddress is 6-bit opcodeContent is next state (4-bits)

Dispatch ROM 2Dispatch ROM 2

InstructionInstruction AddressAddress

(Opcode)(Opcode)

ContentContent

lwlw 100011100011 00110011

swsw 101011101011 01010101


Control ROM ContentsControl ROM ContentsControl ROM has sixteen Control ROM has sixteen 18-bit words:18-bit words:– bits 0-1, AddrCtl to bits 0-1, AddrCtl to

control muxcontrol mux– bits 2-17, sixteen bits 2-17, sixteen

control signals for control signals for datapathdatapath

Address is 4-bit state of Address is 4-bit state of control machinecontrol machine

Addr.Addr. bits 17-2bits 17-2 bits 1-0bits 1-000000000 10010100000010001001010000001000 1111

00010001 00000000000110000000000000011000 0101

00100010 00000000000101000000000000010100 1010

00110011 00110000000000000011000000000000 1111

01000100 00000010000000100000001000000010 0000

01010101 00101000000000000010100000000000 0000

01100110 00000000010001000000000001000100 1111

01110111 00000000000000110000000000000011 0000

10001000 01000000101001000100000010100100 0000

10011001 10000001000000001000000100000000 0000


Microprogram: Basic IdeaMicroprogram: Basic IdeaThe control unit in a computer generates an output The control unit in a computer generates an output (sequence of control signals) for each instruction.(sequence of control signals) for each instruction.Suppose we break down each instruction into a series of Suppose we break down each instruction into a series of smaller operations (microinstructions), such as, smaller operations (microinstructions), such as, fetchfetch, , decodedecode, etc., etc.Then, implement the control unit as a smallThen, implement the control unit as a small computer computer (within the computer) that executes a sequence of (within the computer) that executes a sequence of microinstructions (microprogram) for each instruction.microinstructions (microprogram) for each instruction.M. V. Wilkes, “The Best Way to Design an Automatic M. V. Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Calculating Machine,” Report of Manchester University Report of Manchester University Computer Inaugural ConferenceComputer Inaugural Conference, pp. 16-18, 1951., pp. 16-18, 1951.Reprinted in E. E. Swartzlander (editor), Reprinted in E. E. Swartzlander (editor), Computer Design Computer Design Development: Principal PapersDevelopment: Principal Papers, pp. 266-270, Rochelle , pp. 266-270, Rochelle Park, NJ: Hayden, 1976.Park, NJ: Hayden, 1976.


Maurice V. WilkesMaurice V. WilkesBorn June 26, 1913, Staffordshire, UK, died November 29, 2010

1967 Turing Award citation:

Professor Wilkes Is best known as the builder and designer of the EDSAC, the first computer with an internally stored program. Built in 1949, the EDSAC used a mercury delay line memory. He is also known as the author, with Wheeler and Gill, of a volume on “Preparation of Programs for Electronic Digital Computers” in 1951, in which program libraries were effectively introduced.


Microcoded Control UnitMicrocoded Control Unit

Sixteen18-bit words4-bit address

4-bit state flip-flops

16

2

Controlsignals to datapath

4 4

0001

MUX11 10 01 00

0000

AddrCtl


Adder

6

Opcode from IR

Address

Microcodememory

μPC

Address select logic

Microcode word

Sequencing field

lw or sw sw, lw, R, B or J

ROM address


Implementing the IdeaImplementing the IdeaUse a memory type implementation for control Use a memory type implementation for control unit.unit.Create a software infrastructure to automatically Create a software infrastructure to automatically translate instructions into memory data translate instructions into memory data (microcode):(microcode):

Microinstructions – define a machine language in which Microinstructions – define a machine language in which instructions can be describedinstructions can be describedMicroprogram – an instruction described as a sequence of Microprogram – an instruction described as a sequence of microinstructionsmicroinstructionsMicroassembler – converts microprogram to (binary) Microassembler – converts microprogram to (binary) microcodemicrocode

Is there a micro-compiler?Is there a micro-compiler?


MicroprogrammingMicroprogramming

A microinstruction set is defined.A microinstruction set is defined.

To program the control of a computer for an To program the control of a computer for an instruction set, a programmer writes a instruction set, a programmer writes a microprogram for each machine instruction.microprogram for each machine instruction.

Each micrprogram is converted into Each micrprogram is converted into microcode, specific to the datapath microcode, specific to the datapath hardware, by a microassembler and the hardware, by a microassembler and the entire microcode is loaded in the microcode entire microcode is loaded in the microcode memory of the control unit (CU).memory of the control unit (CU).

Breaking Up MIPS InstructionsBreaking Up MIPS Instructions

R-type instruction:R-type instruction:FetchFetch

DecodeDecode

ALU operationALU operation

Write register Write register

lw:lw:FetchFetch

DecodeDecode

Memory address computationMemory address computation

Read memoryRead memory

Write registerWrite register



Microinstructions for MIPS ISAMicroinstructions for MIPS ISAFetchFetch fetch instructionfetch instruction

DecodeDecode decode instruction, read decode instruction, read registers, registers, calculate branch addresscalculate branch address

RegWrRegWr write registerwrite register

LWSW1LWSW1 compute memory addresscompute memory address

LW2LW2 memory readmemory read

SW2SW2 memory writememory write

R1R1 register type executionregister type execution

BEQ1BEQ1 branch executionbranch execution

JUMP1JUMP1 jump executionjump execution

Let’s Construct MIPS InstructionsLet’s Construct MIPS Instructions

R-type instruction:R-type instruction:FetchFetch

DecodeDecode

R1R1

RegWrRegWr

lw:lw:FetchFetch

DecodeDecode

LWSW1LWSW1

LW2LW2

RegWrRegWr

sw:sw:FetchFetch

DecodeDecode

LWSW1LWSW1

SW2SW2

Branch:Branch:FetchFetch

DecodeDecode

BEQ1BEQ1

Jump:Jump:FetchFetch

DecodeDecode

JUMP1JUMP1Spr 2015, Mar 13 . . .Spr 2015, Mar 13 . . . ELEC 5200-001/6200-001 Lecture 8ELEC 5200-001/6200-001 Lecture 8 1818


Microinstruction FormatMicroinstruction FormatJust one instruction with seven argumentsJust one instruction with seven argumentsA label or name for control state(s), e.g., Fetch, MEM1, etc. A label or name for control state(s), e.g., Fetch, MEM1, etc. Seven arguments and their possible values:Seven arguments and their possible values:– ALU controlALU control add, subtract or funct. codeadd, subtract or funct. code # result to ALUOut# result to ALUOut– SRC1SRC1 PC or APC or A– SRC2SRC2 B, 4, extend or extend-shiftB, 4, extend or extend-shift– Reg. controlReg. control ReadRead # read two reg. specified by IR into A # read two reg. specified by IR into A

and Band BWrite ALUWrite ALU # write ALUOut to register file# write ALUOut to register fileWrite MDRWrite MDR # register file ← MDR# register file ← MDR

– MemoryMemory Read PCRead PC # IR # IR ← ← M[ PC ]M[ PC ]Read ALURead ALU # MDR ← M[ ALUOut ]# MDR ← M[ ALUOut ]Write ALUWrite ALU # M[ ALUOut ] ← B# M[ ALUOut ] ← B

– PCWritePCWrite ALUALU # write PC from ALU# write PC from ALUALU cond.ALU cond. # If zero = 1, PC ← ALUOut# If zero = 1, PC ← ALUOutJump addr.Jump addr. # # PC ← jump addressPC ← jump address

– Sequencing Seq # choose next μInst. Sequentiallyfetch # go to first μInst. to begin new

instr.Dispatch i # use Dispatch ROM i, i = 1 or

2


Sequencing IllustratedSequencing Illustrated

Instr. decode/reg.

fetch/branch

addr.

ALU operation


Write memory

data

Write jump addr.

to PC

Write register

Read memory

data

Instr. fetch/

adv. PC

Compute memory

addr.

Write register

lw

R1 BEQ1 JUMP1

State 01

23

4 5

6

7

8 9

Sequencing= seq

Dispatch 1

Dispatch 2

seq seq

Fetch

Fetch Fetch

LW2

SW2

LWSW1


Microinstruction ArgumentsMicroinstruction Arguments

ArgumentArgument ValueValue μμCode valueCode value ActionAction

ALU CtrlALU Ctrl AddAdd ALUOp = 00ALUOp = 00 ALU addsALU adds

SubtSubt ALUOp = 01ALUOp = 01 ALU subtracts for beqALU subtracts for beq

Funct codeFunct code ALUOp = 10ALUOp = 10 ALU executes R-type instructionALU executes R-type instruction

SRC1SRC1 PCPC ALUSrcA = 0ALUSrcA = 0 PC is first ALU inputPC is first ALU input

AA ALUSrcA = 1ALUSrcA = 1 Reg A is first ALU inputReg A is first ALU input

SRC2SRC2 BB ALUSrcB = 00ALUSrcB = 00 Reg B is second ALU inputReg B is second ALU input

44 ALUSrcB = 01ALUSrcB = 01 Constant 4 is second ALU inputConstant 4 is second ALU input

ExtendExtend ALUSrcB = 10ALUSrcB = 10 Sign extension unit is second ALU Sign extension unit is second ALU inputinput

ExtshftExtshft ALUSrcB = 11ALUSrcB = 11 2-bit shift unit is second ALU input2-bit shift unit is second ALU input


Microinstruction Arguments (Cont.)Microinstruction Arguments (Cont.)ArgumentArgument ValueValue μμCode valueCode value ActionAction

Reg. CtrlReg. Ctrl ReadRead Load A and B from Register fileLoad A and B from Register file

Write ALUWrite ALU RegWrite = 1RegWrite = 1

RegDst = 1RegDst = 1

MemtoReg = 0MemtoReg = 0

An IR-specified register in An IR-specified register in Register file is written from Register file is written from ALUOutALUOut

Write MDRWrite MDR RegWrite = 1RegWrite = 1

RegDst = 0RegDst = 0

MemtoReg = 1MemtoReg = 1

An IR-specified register in An IR-specified register in Register file is written from MDRRegister file is written from MDR

MemoryMemory Read PCRead PC MemRead = 1MemRead = 1

IorD = 0IorD = 0

IRWrite = 1IRWrite = 1

IR ← M[ PC ]IR ← M[ PC ]

MDR ← M[ PC ]MDR ← M[ PC ]

Read ALURead ALU MemRead = 1MemRead = 1

IorD = 1IorD = 1MDR ← M[ ALUOut ]MDR ← M[ ALUOut ]

Write ALUWrite ALU MemWrite = 1MemWrite = 1

IorD = 1IorD = 1M[ ALUOut ] ← BM[ ALUOut ] ← B


Microinstruction Arguments (Cont.)Microinstruction Arguments (Cont.)FieldField μμInstr. valueInstr. value μμCode valueCode value ActionAction

PC Write PC Write CtrlCtrl

ALUALU PCSource = 00PCSource = 00

PCWrite = 1PCWrite = 1Register file loads A and BRegister file loads A and B

ALUOut-ALUOut-condcond

PCSource = 01PCSource = 01

PCWriteCond = 1PCWriteCond = 1An IR-specified register in An IR-specified register in Register file is written from Register file is written from ALUOutALUOut

Jump Jump addressaddress

PCSource = 10PCSource = 10

PCWrite = 1PCWrite = 1An IR-specified register in An IR-specified register in Register file is written from MDRRegister file is written from MDR

SequencSequencinging

SeqSeq AddrCtl = 11AddrCtl = 11 Choose next Choose next μμInstr. sequentiallyInstr. sequentially

FetchFetch AddrCtl = 00AddrCtl = 00 Go to first Go to first μμInstr.Instr. to begin new to begin new instructioninstruction

Dispatch 1Dispatch 1 AddrCtl = 01AddrCtl = 01 Use Dispatch ROM 1Use Dispatch ROM 1

Dispatch 2Dispatch 2 AddrCtl = 10AddrCtl = 10 Use Dispatch ROM 2Use Dispatch ROM 2


Microinstruction FetchMicroinstruction Fetch

Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.ctrl. ctrl. ctrl.

Fetch Add PC 4 Read PC ALU SeqDecode Add PC ExtShft Read Dispatch 1

Microassembler produces the following microcode:00 0 01 0 0 0 1 0 1 0 00 1 0 1100 0 11 0 0 0 0 0 0 0 00 0 0 01

AL

UO

p

AL

US

rcA

AL

US

rcB

Reg

Wri

teR

egD

stM

emto

Reg

Mem

Rea

dIo

rDIR

Wri

teM

emW

rite

PC

So

urc

eP

CW

rite

PC

Wri

teC

on

d

Ad

drc

tl


Microprogram for lw and swMicroprogram for lw and sw


LWSW1 Add A Extend Dispatch 2 LW2 Read ALU SeqRegWr Write MDR Fetch SW2 Write ALU Fetch

Microprogram consists of four microinstructions.


Microprogram for R-Type InstructionMicroprogram for R-Type Instruction


R1 Funct code A B SeqRegWr Write ALU Fetch

Go to next μInstr.Go to μInstr. Fetch

Microprogram consists of two microinstructions.


Microprogram for beq InstructionMicroprogram for beq Instruction


BEQ1 Subt A B ALUOut-cond Fetch

If (zero) then PC ← ALUOut Go to μInstr. Fetch

Microprogram consists of one microinstruction.


Microprogram for jump InstructionMicroprogram for jump Instruction


JUMP1 Jump address Fetch

Microprogram consists of one microinstruction.


μμProgram for Multi-Cycle CUProgram for Multi-Cycle CULabel ALU SRC1 SRC2 Reg. Mem. PCWrite Seq.

ctrl. ctrl. ctrl.

Fetch Add PC 4 Read PC ALU SeqDecode1 Add PC ExtShft Read Disp. 1

LWSW1 Add A Extend Disp. 2LW2 Read ALU SeqRegWr Write MDR FetchSW2 Write ALU Fetch

R1 FntCd. A B SeqRegWr Write ALU Fetch

BEQ1 Subt A B ALUOut-cond Fetch

JUMP1 Jump address Fetch

26-31 toMicrocoded

Control


Multicycle DatapathMulticycle DatapathP

C

Inst

r.

reg

. (I

R)

Mem

. D

ata

(MD

R)

AL

UO

ut

Reg

.

A R

eg.

B R

eg.

A

LU

Reg

iste

r fi

le

Mem

ory

Ad

dr.

Data

4

Sign extend

Shift left 2

ALUcontrol

0-5

0-15

16-2021-25

IorD

MemtoReg

ALUOp

AL

US

rcB

AL

US

rcA

RegDstIRWrite

RegWrite

MemWrite

MemRead

Shift left 20-25

28-31

PCSource

PC

Wri

te e

tc.

11

-15

Microcode OperationMicrocode Operation

μμPC is always initialized to 0000PC is always initialized to 0000

Load starting instruction address in PCLoad starting instruction address in PC

Clock control and datapathClock control and datapath



How Microcode WorksHow Microcode Works

Sixteen18-bit words

4-bit address

0000

16

11

clk 1: SetDatapathfor Fetch

4 4

0001

MUX11 10 01 00

0000

AddrCtl


Adder

6

Opcode from IRIn clk 2

Address

Microcodememory

μPC

Address select logic

Sequencing field

lw or sw sw, lw, R, B or J

ROM address

0001 in clk 2


Multicycle Control FSMMulticycle Control FSM

Instr. decode/reg.

fetch/branch

addr.

ALU operation


Write memory

data

Write jump addr.

to PC

Write register

Read memory

data

Instr. fetch/

adv. PC

Compute memory

addr.

Write register

lw or sw

lw

sw

RB

J

Start

State 0 1

23

4 5

6

7

8 9



SummarySummaryHard-wired control:Hard-wired control: A finite state machine A finite state machine implemented typically using programmable logic implemented typically using programmable logic array (PLA) or random logic.array (PLA) or random logic.Microinstruction:Microinstruction: A one-clock instruction that A one-clock instruction that asserts a set of control signals to the datapath and asserts a set of control signals to the datapath and specifies what microinstruction to execute next.specifies what microinstruction to execute next.Microprogram:Microprogram: A sequence of microinstructions A sequence of microinstructions that implements a multicycle (or single cycle) that implements a multicycle (or single cycle) instruction.instruction.Microcode:Microcode: Machine code of a microprogram, Machine code of a microprogram, generally produced by a generally produced by a microassemblermicroassembler..Microprogrammed or microcoded control:Microprogrammed or microcoded control: A A method of specifying control that uses microcode method of specifying control that uses microcode rather than a finite state machine.rather than a finite state machine.


Further on MicroprogrammingFurther on MicroprogrammingPreceding discussion is based on:Preceding discussion is based on:

D. A. Patterson and J. L. Hennessey, D. A. Patterson and J. L. Hennessey, Computer Organization and Computer Organization and Design, Second EditionDesign, Second Edition, San Francisco: Morgan-Kaufman, 1998, , San Francisco: Morgan-Kaufman, 1998, Chapter 5, pp. 399-410.Chapter 5, pp. 399-410.

Terms “microcomputer”, “microarchitecture” and Terms “microcomputer”, “microarchitecture” and “micropipeline” are not related to microprogramming.“micropipeline” are not related to microprogramming.Nanoprogramming: Two levels of microprogramming Nanoprogramming: Two levels of microprogramming – a “recursive” control:– a “recursive” control:

Nanodata Corp., Nanodata Corp., QM-1 Hardware Level Users ManualQM-1 Hardware Level Users Manual, 2, 2ndnd Ed., Ed., Williamsville, NY, 1972.Williamsville, NY, 1972.J. P. Hayes, J. P. Hayes, Computer Architecture and OrganizationComputer Architecture and Organization, Section , Section 4.4.3, NY: McGraw-Hill, 1978.4.4.3, NY: McGraw-Hill, 1978.

Virtual machines: Any program can be run on any Virtual machines: Any program can be run on any instruction set using an interpreter. Example, Java.instruction set using an interpreter. Example, Java.

Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 1 ELEC 5200-001/6200-001 Computer Architecture...

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