Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock Slide 1

Spezielle Anwendungen des VLSI – Entwurfs

Applied VLSI design

Course and contest

Results of Phase 4

Nam Pham Van

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Design comparison

Slide 2

P ~ A Power: P = (Pdyn * Pleak)

Area: A

Reduction of the area lower the power consumption

ASIC Values (Synopsis)

Brent Kung Adder Ripple Carry AdderFrequency - f 500 MHz 500 MHzVoltage - Vdd 1.0 V 1.0 VLibrary COREHVTtyp10V COREHVTtyp10V

Power PTotal (W) 2.7482*10-11 2.71122*10-11

Metric (1 / J2) [9.1*1027] [9.22*1027]

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

4-Bit Block

c04-Bit Block

4-Bit Block

c3c7cout

Design & architecture

Slide 3

• RCA small area low power consumption

4-Bit Block

c04-Bit Block

4-Bit Block

c‘3c3c‘7c7cout c‘11

P[3:0]P[7:4]P[11:8]0

1

0

1

0

1

• Improve speed with Carry Skip architecture

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Design & architecture optimization

Slide 4

Adder Reduction:

• 10 bit 8 bit

• 11 bit 10 bit

• 16 bit 13 bit

Influences:

Minimized switch activity

Reduced area & power consumption

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Cadence configuration

Slide 5

• Antenna fixing

• Eco route

• Wire optimization

Setting Effect

• Netlist optimization

• Design optimization

• Higher frequency are possible

• Power consumption raised immense

• No impact

• Other gate libraries • Higher frequency are possible

• Extreme high leakage power consumption

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Cadence configuration

Slide 6

Best settings:

• Core Ratio H/W: 1

• Core Utilization: 90

• IO Boundary: 15

• Power Ring:

• Width: 2

• Spacing: 0.5

• Offset: 2

• COREHVTtyp10V

55 60 65 70 75 80 85 90 95 100320

330

340

350

360

370Frequency - Core utilization

Frequency

core utilization [%]

f [MHz]

330 335 340 345 350 355 360 365 3709.5E+027

1E+028

1.05E+028

1.1E+028

1.15E+028

1.2E+028Metric - Frequency

Metic

f [MHz]

Metric [J-2]

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Chip with pads

Power (Pdyn / Pleak) 45.4152 mW / 6.2518 mW

Metric (J-2) [5.193*1020]

Results of ASIC design

Slide 8

Mandatory values for ASIC

Timing (Tmin / fmax) 2.6 ns / 384 MHz

Power (Pdyn / Pleak) 872.2123 µW / 13.4781 nW

# Pipeline Stages 8

Metric (J-2) [1.254*1028]

Core size 3000 µm2

Core utilization 90 %

Institute of Applied Microelectronics and Computer Engineering

College of Computer Science and Electrical Engineering, University of Rostock

Thank you for your attention!

Slide 9