Spacer Gate Lithography for Reduced Variability Due to...

09/06/2007 FLCC - Device/Integration

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FLCC

Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness

Student(s): Xin Sun

Faculty: Professor Tsu-Jae King Liu


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FLCC

Motivation• Variability in transistor performance is one of the major

challenges for continued scaling of CMOS technology.• As transistor gate lengths are scaled down:

– Line edge roughness (LER) is not reduced commensurately.– Thermal process budgets are reduced to achieve shallower and

more abrupt junctions.

→ The effects of gate LER become increasingly significant. Techniques for reducing LG variation will be need for sub-20nm LG.

A. Asenov, Symp. VLSI Tech. Dig., pp. 86-87, 2007.


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FLCC

Benefits of Spacer Lithography

• Sub-lithographic feature sizes– CVD film thickness determines feature size

• Tighter CD control

LG

Gate formation by spacer lithography

uniform LG

Oxide spacers, line width = 100.8nm

Silicon substrate

SEM plan-view of oxide spacers formed using 248nm lithography to pattern the sacrificial layer.

LG

Gate formation by conventionallithography

non-uniform LG

Y.-K. Choi et al., IEDM Technical Digest, pp. 259-262, 2002


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FLCC

FLCC Year 4 Milestones• Perform 3-D device simulations to assess the benefit of

spacer lithography for improving the uniformity of bulk-Si MOSFET performance, for LG < 50nm.

• Determine the relative impacts of various sources of variability.


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FLCC

Approach•LER Data + Matlab to generate inputs•Sentaurus 3-D process and device

LER (LWR) Generation

Structure Generation

Device Simulation

LER (LWR) Generation

Structure Generation

Device Simulation

simulation

Conventional Lithography Spacer Lithography

fc=1/(1.5*LG)

Gate Profiles LG

Gate Profiles

LG

Plan view of gate electrode

LER power spectrum

Spatial frequency


fc=1/(1.5*LG)


fc=1/(1.5*LG)

Gate Profiles LG

Gate Profiles

LG

Plan view of gate electrode

LER power spectrum

Spatial frequency

• The spacer gate profiles are smoothed along one edge.

• Assumptions:

•LWR in Leff is the same as that for the gate (worst case, relevant for future ultra-shallow junction technology).

•LER will not reduce with LGscaling.


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FLCC

Spacer vs. Conventional Gate LithographyLG = 14nm

1050 1100 1150 1200

10-1

100

101

LG=14nm

Conventional Lithography Spacer Gate Lithography

I OFF

(µA/µm

)

ION (µA/µm)

800 900 1000 1100 120010-3

10-2

10-1

100

Spacer Gate Lithography

LG=32nm LG=14nm

I OFF

(µA/µm

)

ION (µA/µm)

Variability is well suppressed with LG scaling, even if LER does not scale.


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FLCC

FLCC Year 4 Remaining Work

• Determine the relative impacts of the various sources of variability:– line-width variations– line-edge roughness– statistical dopant fluctuations

…for different applications:– high-performance logic – low-power logic– memory devices (e.g. flash)


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FLCC

Future Goals (under the IMPACT program)

• Quantify the benefits of non-classical transistor designs and advanced process technologies for reducing variability, and assess how these benefits scale with advancements in CMOS technology (to the 22nm node and beyond)– The benefits of spacer gate lithography, multi-gate MOSFET

structures, and highly engineered dopant profiles for mitigatingvariability will be quantified

• Assess impact of new transistor designs and process technologies for improving (6-T) SRAM yield in sub-45nm CMOS technologies.


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FLCC

Diffusion Studies in Isotopically Controlled Ge and SiGe

Faculty: Prof. Eugene E. Haller, UC BerkeleyProf. Hartmut Bracht, University of Münster, Germany

Student: Chris Liao


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FLCC

All Current FLCC Milestones in Integration

• Year 4 Milestone (2007): – Determine the Si and Ge self-diffusivity in SiGe alloys

with different compositions using isotopically enriched MBE grown multilayer structures (completed for SiGe with 5% and 25% Ge)

– Determine As diffusivity simultaneously with Si and Ge self-diffusivity in SiGe alloy using isotopically enriched MBE grown multilayer structures (in progress)


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FLCC

Motivation

Substrate

Gate

Source Drain

Substrate

Gate

Source DrainLeff Nsub

Xj

LgTox

Courtesy of Pankaj Kalra and Prof. Tsu-Jae King

Planar Bulk-Si MOSFET Structure

• SiGe and Ge are utilized in current and future generations of electronic devices

• Diffusion mechanisms in SiGe and Ge are largely unknown

• Advanced modeling and control of diffusion requires an improved basic understanding of diffusion processes in SiGe and Ge

• The fundamental understanding forms the backbone of future processing and defect engineering


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FLCC

The Problem• Equilibrium diffusion and non-equilibrium diffusion effects

are not well understood in Ge and SiGe• Self-diffusion of Si and Ge in SiGe alloys have not been

studied extensively• Defect reactions at relevant device processing

temperatures are unknown• Knowledge of diffusion mechanisms and dopant-defect

reactions are required for processing of future generations of devices in SiGe or Ge


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FLCC

As Diffusion in Ge

vacancy mechanism:

1016

1017

1018

0 10 20 30 40depth (µm)

conc

entr a

t ion

ofAs

( cm

-3) 680°C, 3d

730°C, 3d770°C, 4d820°C, 100min868°C, 300min920°C, 180min

1016

1017

1018

1019

1020

0 25 50 75 100depth (µm)

conc

ent ra

t ion

o fAs

(cm

- 3) 640°C, 19d

680°C, 90h730°C, 2d770°C, 2d820°C, 100min868°C, 150min

n: free electron concentration; ni: intrinsic carrier concentration

eqAs

AsVeqAsV

AsVAsi

iAsAs

sC

DCDD

nnnDD

+

−−

− ==⎟⎟⎠

⎞⎜⎜⎝

⎛= )()(*

)(

2

with )(−+− +↔ 2

s VAs)AsV(scm

TkeVnTD

BiAs /)70.2exp(30),( 2−=

Ref: H. Bracht et al, Mater. Sci. in Semicond. Process 9 (2006) 471


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FLCC

Simultaneous As and Ge Self Diffusion

Carbon doped natGe/70Ge/… isotope structure:

As implanted

1018

1019

1020

1021

1022

1023

0 500 1000 1500depth (nm)

conc

entra

tion

( cm

-3)

Ge

amor

ph

nat G

e70

Ge

70Ge

73Ge

12C

70Ge layers doped with carbon

Carbon concentration exceeds the solubility limit


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FLCC

Simultaneous As and Ge Self DiffusionEffect of Carbon

1017

1019

1021

1023

0 500 1000 1500 2000

75As12C

74Ge

depth (nm)

conc

entra

tion

(cm

-3)

700°C, 15 min

1017

1019

1021

1023

0 500 1000 1500 2000

74Ge

75As in natGe/70Ge ...

75As in natGe

depth (nm)

conc

entra

tion

(cm

-3)

700°C, 15 min

Finding: As diffusion is retarded by carbon


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FLCC

Fitting of As Diffusion Profiles in Si

1.E+16

1.E+17

1.E+18

1.E+19

1.E+20

1.E+21

0 200 400 600 800 1000 1200 1400Depth (nm)

As

Con

cent

ratio

n (c

m-3

)

930C 102 hr965C 45 hr1000C 17 hr930C fitting965C fitting1000C fitting

Fitting using known As in Si diffusion reactions*see H. Bracht et al. PRB 75, 035211 (2007)


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FLCC

New IMPACT Projects

Diffusion in Isotopically Controlled Semiconductors• Lead faculty: Prof. Eugene E. Haller, Prof. Tsu-Jae King, and

Prof. Nathan Cheung• Motivation:

– The rapidly diminishing dimensions of Si and SiGe devices and the continued increase in doping concentrations needed for future generation of devices requires an improved fundamental understanding of diffusion mechanisms.

– This work will yield valuable information such as diffusion coefficients and diffusion mechanisms of common impurities in SiGe and Ge

– In addition, this work will provide an understanding of defect reactions at relevant processing temperature; crucial for defect engineering and diffusion-less dopant activation


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FLCC

New IMPACT Projects

Diffusion in Isotopically Controlled Semiconductors

• Main Objective: To create a solid base of understandings of diffusion mechanisms and impurity-defect reactions for future use in advanced semiconductor device modeling, design, and manufacturing

• Project Goals:– Determine As diffusion mechanisms in relaxed SiGe using isotopically

controlled structure– Self-diffusion in strained isotopically enriched SiGe layers– Implement atomistic modeling to describe diffusion and compare it with

continuum theory modeling– Explore the diffusion of advanced gate oxide materials into SiGe and Ge


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FLCC

Engineered High Mobility CMOS Substrates

Student(s): Haiyan Jin

Faculty: Prof. Nathan Cheung


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FLCC

Motivation

•• Significantly higher electron mobility and hole mobility than Significantly higher electron mobility and hole mobility than that of that of siliconsilicon

•• Smaller contact resistance due to lower bandSmaller contact resistance due to lower band--gapgap•• Low Interface state Low Interface state denistydenisty is essential to Ge MOSFETis essential to Ge MOSFET•• Potential substrate for Potential substrate for FinFETFinFET structuresstructures

Technology Challenges

•• Compatibility with highCompatibility with high--k gate dielectric (HfOk gate dielectric (HfO22,ZrO,ZrO22,Al,Al22OO33))•• Higher mobility is expected through strained GermaniumHigher mobility is expected through strained Germanium


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FLCC

2007 Main Objective

• Reduction of Ge interface state density• Prototype GeOI MOSFET performance evaluation• Demonstrate Strained GeOI layer transfer

Achievements• Interface trap is decreased to 1010q/cm2 by forming gas annealing method• Interface bulk hole mobility is increased up to 500cm2/Vs, which is larger than that of silicon• GeOI substrate electrically stable up to 550• New pseudo-MOSFET methodology to extract bulk mobility of GeOI


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FLCC

New pseudo-MOSFET methodology(Extracting bulk mobility of GeOI)

-30 -20 -10 0 10 20 30

0.00050

0.00055Inversion

(I)

Depletion(II)

Accumulation(III)

VT=6.8VVFB= -10.2V

Experimental data Theoretical data

G =

I 1,4

/V2,

3(Ω

-1)

VG(V)

A

BOX

P+-Si substrate

Ge3 4

VG+

_

V

21

I 1,4V2,3

A

BOX

P+-Si substrate

Ge3 4

VG+

_

V

21

I 1,4V2,3

Bulk Ge film conductance G(A-G)2=B•VG+CA= fg q µB NSi(tSi + εs/Cox) B=2q (fg µB )2 εs NSiC=(fgq µB NSi )2 [(εs/Cox)2 - 2εsVFB/(qNSi)]To extract bulk mobility µB by fitting experimental data with theoretical data

Channel conductance GchGch= fg µ I Cox (VG-VFB, T) /[1+θ (VG-VFB, T)]Gch’=dGch/dVG=fgCoxµ I/[1+θ (VG-VFB, T)]2Gch/(Gch’)0.5=(fg µ ICox )0.5(VG-VFB,T) Gch/[Gch’(VG-VFB,T)]=1+θ (VG-VFB, T)


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FLCC

The condition of forming gas annealing

• Gas ratio : 10%H2, 90%N2

• Gas flow : 8L/min• Temperature : 400~600

• Time : 10min or 30min at each temperature point

0 50 100

400

500

600 Temperature increases step by step

Sample1slow ramp

Sample2 fast ramp

Tem

pera

ture

(o C)

Time (min)


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FLCC

Interface trap (Qit) and Interface charge(Qf) improved through forming gas annealing

400 500 6000.1

1

10

100

Slow ramp Fast ramp

Qf (

1010

q/cm

2 )

T(oC)

400 500 6000.1

1

10

100

Slow ramp Fast ramp

Qit (

1010

q/cm

2 )T(oC)

(A) (B)Both interface trap density Qit and interface fixed charge density Qfdecrease to 1010q/cm2 after forming gas annealing.

Qit Qf


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FLCC

Carrier mobility improved through forming gas annealing

400 500 6000

100

200

300

400

500 µpB (Slow ramp) µpB (Fast ramp)

Mob

ility

(cm

2 /Vs

)

T (oC)

400 500 6000

150

300

450 µpI (slow ramp) µnI (slow ramp) µpI (fast ramp) µnI (fast ramp)

Mob

ility

(cm

2 /Vs

)T (oC)

Bulk Interface

(A) (B)• 3X improvement of bulk hole mobility with fast ramp• 3X improvement of interface hole mobility with fast ramp• 2X improvement of interface electron mobility with slow ramp


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FLCC

Pseudo-MOSFET data at different measurement temperature

-50 0 50 1000

200

400

600

800 µnI

µpI

µpB

Car

rier M

obili

ty (c

m2 /

Vs)

T(oC)

2.5 3.0 3.5 4.0 4.520

22

24

26

28

Forming gas annealing: Ea=50mV

Without annealing: Ea=45mV

lnQ

it1000/T(K-1)

(A) (B)

• At same doping level Ge bulk hole mobility is higher than that of bulk Si (300cm2/V-sec)


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FLCC

IMPACT Proposal: Buried Stress Sheet MOSFETBuried Stress Sheet MOSFETflow and advantagesflow and advantages

(1) 1000 (1) 1000 annealing increase 0.5GPa stress in silicon channel (σ ∝ ∆T)

(2) For NMOS (Buried stress sheet orthogonal to S-D direction), increase 0.2-0.4GPa compressive stress in channel

(3) For PMOS (Buried stress sheet parallel to S-D direction), increase 1GPa compressive stress in channel and the mobility increase 50%

Buried uniaxial stress sheet formed

Si layer transferred

•1000 thermal expansionLPCVD SiN for tensile stress

PECVD SiN for compressive stress [ S.E.Thompson,IEDM2006 ]

NMOS and PMOS fabrication

Stress sheet

Stress sheet

Com

pres

sive

she

et

Stress sheet

High-K dielectric


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FLCC

Total Total --2GPa stress gives 3X 2GPa stress gives 3X µµpp; Total +1.3GPa stress gives 1.5X µµnn

Com

pres

sive

she

et

Compressive linerPMOS

(100)

Com

pres

sive

she

et

(100)

S G DPMOS NMOS

Buried uniaxial stress sheet

S

G

D

A

B’

A’

B

Side view of AASide view of AA’’ Side view of BBSide view of BB’’


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FLCC

IMPACT Proposal: Buried Stress Sheet for Buried Stress Sheet for FinFETFinFET structurestructure

BB’ side view of PMOS

FIN

gate

SubstrateBuried uniaxial compressive sheet

(110)

GS

D B’

(110)

PMOS

BA’AG (100)

S

DNMOS

Buried uniaxial compressive stress sheet

FINgate

Substrate

AA’ side view of NMOS

(100)

Buried uniaxial compressive sheet

Transferred (110) silicon layer gives higher hole mobility for PTransferred (110) silicon layer gives higher hole mobility for PMOSMOS

Total Total --1GPa stress gives 1.5X 1GPa stress gives 1.5X µµpp; Total +0.3GPa stress gives 1.3X µµnn


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FLCC

In Progress

• Prototype GeOI MOSFET performance with ALD high-K dielectric ( with Prof. J. Chang, UCLA)

• Large Area GeOI layer transfer using Ge epi wafers• Demonstrate Strained GeOI layer transfer (AMAT) • Buried stress sheet fabrication using layer transfer

method

Spacer Gate Lithography for Reduced Variability Due to...

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