SONET Transmission Products S/DMS TransportNode OC …Npatrick/Nortel-sdms-docs/N3RLTV4W.pdfS/DMS...

NT7E65DJ 323-1111-102

SONET Transmission Products

S/DMS TransportNode OC-3/OC-12 NE—TBM

Circuit Pack Descriptions

Standard Rel 14 February 2001

What’s inside ...

Circuit pack descriptions

Copyright

1992–2001 Nortel Networks, All Rights Reserved

The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose it only to its employees with a need to know, and shall protect it, in whole or in part, from disclosure and dissemination to third parties with the same degree of care it uses to protect its own confidential information, but with no less than reasonable care. Except as expressly authorized in writing by Nortel Networks, the holder is granted no rights to use the information contained herein.

Nortel Networks and S/DMS TransportNode are trademarks of Nortel Networks. VT100 is a trademark of Digital Equipment Corporation. UNIX is a trademark of X/Open Company Ltd.

Printed in Canada

iii

Contents What’s inside ...About this document vii

Circuit pack descriptions 1-1DS1 input circuit pack (NT4K32) 1-2

Functional description 1-2Physical appearance of the DS1 input circuit pack 1-2

DS1 output circuit pack (NT4K33) 1-3Functional description 1-4Physical appearance of the DS1 output circuit pack 1-4Equipping rules for the DS1 input and output circuit packs 1-5

DS1 VT mapper circuit pack (NT7E04) 1-6From DS1 interface to OC-12 or OC-3 optical interface 1-7From OC-12 or OC-3 optical interface to DS1 interface 1-7Control bus interface 1-7Point-of-use power supply (PUPS) 1-7Alarm LED definitions 1-7Provisioning options for the DS1 VT synchronous mapper 1-8Physical appearance of the DS1 VT synchronous mapper 1-9Equipping rules for the OC-12 or OC-3 shelf 1-10Associated I/O circuit packs 1-11

BNC I/O circuit pack (NT4K30) 1-11Functional description 1-11Physical appearance of the BNC I/O circuit pack 1-13Equipping rules 1-13

DS3 STS mapper circuit pack (NT7E08) 1-17From BNC I/O circuit packs to OC-12 or OC-3 optical interface 1-17From OC-12 or OC-3 optical interface to BNC I/O circuit pack 1-17Unframed DS3 clear channel 1-17Control bus interface (CBus) 1-18Point-of-use power supply (PUPS) 1-18Alarm LED definitions 1-18Physical appearance of the DS3 STS mapper 1-20Equipping rules for the OC-12 or OC-3 shelf 1-21DS3 STS mapper circuit pack (NT7E08BA) 1-22

STS-1 electrical interface circuit pack (NT7E09) 1-22From the BNC I/O circuit packs to the OC-12 or OC-3 optical interface 1-22From the OC-12 or OC-3 optical interface to the BNC I/O circuit packs 1-22Control bus interface 1-23

Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

iv

Contents

Point-of-use power supply (PUPS) 1-23Alarm LED definitions 1-23Equipping rules for the OC-12 or OC-3 shelf 1-24Physical appearance of the STS-1 interface 1-26

Protection switcher circuit pack (NT4K60) 1-27Functional description 1-27Bus connections 1-29Physical appearance of the protection switcher circuit pack 1-30Equipping rules for the OC-12 or OC-3 shelf 1-31

External synchronization interface carrier (NT7E19) 1-31Functional description 1-31

External synchronization interface (ESI) unit (NT7E27) 1-33Functional description 1-34Physical appearance of the ESI equipment 1-36Equipping rules for the OC-3 or OC-12 shelf 1-37

Maintenance interface controller circuit pack (NT4K53) 1-37Functional description 1-38Bus connections 1-43Equipping rules for the OC-12 or OC-3 shelf 1-43Physical appearance of the maintenance interface circuit pack 1-44

OC-12 optical interface circuit pack (NT7E02) 1-45OC-12 interfaces with changeable optical connectors 1-47Terminal, linear ADM, and ring ADM applications 1-50Regenerator application 1-50Control bus interface (CBus) 1-51Point-of-use power supply (PUPS) 1-52Equipping rules for the OC-12 shelf 1-52Alarm LED definitions 1-53

Ring loopback circuit pack (NT7E35) 1-55Control bus interface (CBus) 1-55Point-of-use power supply (PUPS) 1-57Equipping rules for the OC-12 shelf 1-57

Overhead bridge circuit pack (NT7E36) 1-59Equipping rules for the OC-12 shelf 1-59

OC-3 optical interface circuit pack (NT7E01) 1-61NT7E01GA and NT7E01GB optical interface circuit packs 1-61Transmit direction 1-61Receive direction 1-62Control bus interface (CBus) 1-62Point-of-use power supply (PUPS) 1-62Equipping rules for the OC-3 or OC-12 shelf 1-62Alarm LED definitions 1-63

STS-12 electrical interface (NT7E33) 1-66Control Bus (CBus) interface 1-67Point-of-use power supply (PUPS) 1-67Equipping rules for the OC-12 shelf 1-67Alarm LED definitions 1-67

OC-12 VTM circuit pack (NT7E05) 1-70VTM ring ADM application 1-73Bus interface 1-74Transport Control Subsystem 1-74

S/DMS TransportNode OC-3/OC-12 NE—TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Contents

v

Point-of-use power supply (PUPS) 1-74Equipping rules for the OC-12 shelf 1-74Alarm LED definitions 1-74

Operations controller (NT7E24) 1-76Solid state OPC (NT7E24EA or NT7E24FA) 1-76Centralized data management 1-76Software management 1-76OPC user interface 1-76Point-of-use power supply (PUPS) 1-76Alarm LED definitions 1-77Interfaces supported by the OPC 1-82Equipping rules for the OC-12 or OC-3 shelf 1-83

Processor circuit pack (NT4K52) 1-84Functional description 1-85Bus connections 1-87Point-of-use power supply (PUPS) 1-87Physical appearance of the processor circuit pack 1-88Equipping rules for the OC-12 or OC-3 shelf 1-89

Power termination circuit pack (NT4K58) 1-89Equipping rules for the OC-12 or OC-3 shelf 1-89

Side interconnect left circuit pack (NT4K50BA) 1-90


vi

Contents


vii

About this documentThis document provides a brief description of each circuit pack, a functional block diagram, and an illustration of the faceplate. The document also provides equipping rules.

AudienceThis document is for the following members of the operating company:

• planners

• provisioners

• network administrators

• transmission standards engineers

• maintenance personnel

References in this documentThis document refers to the following documents:

• System Description, 323-1111-100

• Software Description, 323-1111-101

• System Applications Description, 323-1111-150

• Ordering Information, 323-1111-151

• User Interfaces Description, 323-1111-301


viii

About this document


1-1

Circuit pack descriptions 1-This chapter describes all OC-12 and OC-3 network element (NE) circuit packs. See Table 1-1 for a list of all circuit packs described in this chapter.

Table 1-1 OC-3/OC-12 network element circuit packs and modules

PEC Circuit pack or module Page

NT4K30 BNC I/O circuit pack (NT4K30) 1-11

NT4K32 DS1 input circuit pack (NT4K32) 1-2

NT4K33 DS1 output circuit pack (NT4K33) 1-3

NT4K50 Side interconnect left circuit pack (NT4K50BA) 1-90

NT4K52 Processor circuit pack (NT4K52) 1-84

NT4K53 Maintenance interface controller circuit pack (NT4K53)

1-37

NT4K58 Power termination circuit pack (NT4K58) 1-89

NT4K60 Protection switcher circuit pack (NT4K60) 1-27

NT7E01 OC-3 optical interface circuit pack (NT7E01) 1-61

NT7E02 OC-12 optical interface circuit pack (NT7E02) 1-45

NT7E04 DS1 VT mapper circuit pack (NT7E04) 1-6

NT7E05 OC-12 VTM circuit pack (NT7E05) 1-70

NT7E08 DS3 STS mapper circuit pack (NT7E08) 1-17

NT7E09 STS-1 electrical interface circuit pack (NT7E09) 1-22

NT7E19 External synchronization interface carrier (NT7E19)

1-31

NT7E24 Operations controller (NT7E24) 1-76

—continued—


1-2


The following information is provided for each circuit pack:

• circuit pack function supported by a block diagram

• faceplate layout illustration with LED definitions

• equipping rules (if applicable)

DS1 input circuit pack (NT4K32) Install the DS1 input circuit pack in the upper level of the OC-12 or OC-3 shelf. Each working DS1 virtual tributary (VT) synchronous mapper in the lower level of the shelf must have one DS1 input circuit pack and one DS1 output circuit pack in the upper level. Each DS1 input circuit pack handles 14 DS1 channels of input (all DS1 input to a single DS1 VT synchronous mapper). Input DS1 signals enter the S/DMS TransportNode, travel to the DS1 input circuit pack, and onto the associated DS1 VT synchronous mapper.

Functional description Figure 1-1 shows a block diagram of the DS1 input circuit pack. The circuit pack filters electromagnetic interference (EMI) from the incoming DS1 signals. The signals pass through a splitter, and travel to the associated working DS1 VT synchronous mapper, then towards the DS1 protection bus in the shelf backplane. In normal operation, the signals do not reach the DS1 protection bus because an on-card relay is open. When a protection-switching request occurs for the associated working DS1 VT synchronous mapper, the relay closes, and the DS1 signals travel to the protection bus. (The DS1 protection bus routes the DS1 signals toward the protection DS1 VT synchronous mapper.)

Physical appearance of the DS1 input circuit pack The DS1 input circuit pack is 5.7 cm (2.25 in.) high by 25.8 cm (10.15 in.) deep by 2.0 cm (0.8 in.) wide. Figure 1-2 shows the front view of the DS1 input circuit pack. This circuit pack has a D connector at the front.

NT7E27 External synchronization interface (ESI) unit (NT7E27)

1-33

NT7E33 STS-12 electrical interface (NT7E33) 1-66

NT7E35 Ring loopback circuit pack (NT7E35) 1-59

NT7E36 Overhead bridge circuit pack (NT7E36) 1-59

—end—

Table 1-1 (continued)OC-3/OC-12 network element circuit packs and modules

PEC Circuit pack or module Page



1-3

Figure 1-1Block diagram of the DS1 input circuit pack

FW-1923

Figure 1-2Front view of the DS1 input circuit pack

FW-1927

DS1 output circuit pack (NT4K33) Install the DS1 output circuit pack in the upper level of the TBM shelf. Each working DS1 VT synchronous mapper in the lower level of the shelf must have one DS1 output circuit pack and one DS1 input circuit pack in the upper level. Each DS1 output circuit pack handles 14 DS1 channels of output (all DS1 output from a single DS1 VT synchronous mapper circuit pack). Output DS1 signals travel from the DS1 VT synchronous mapper to the associated DS1 output circuit pack, then out of the S/DMS TransportNode.

DSX-1twistedpair line

EMIfilter

6 dBsplitter

To WorkingDS1/VTsynchronousmapper

To ProtectionDS1/VTsynchronousmapper

Relay contactis normally open.

Fastening screw

44-pin D connector


1-4


Functional description Figure 1-3 shows a block diagram of the DS1 output circuit pack. The circuit pack receives DS1s from the associated working DS1 VT synchronous mapper (under normal circumstances) or the DS1 protection bus in the shelf backplane. When a protection-switching request occurs for the associated working mapper, the on-card relays break the connection to the associated working mapper and close the connection to the protection bus. The DS1 output circuit pack performs EMI filtering on the outgoing DS1s.

Figure 1-3Block diagram of the DS1 output circuit pack

FW-1931

Physical appearance of the DS1 output circuit pack The DS1 output circuit pack is 5.7 cm (2.25 in.) high by 25.8 cm (10.15 in.) deep by 2.0 cm (0.8 in.) wide. Figure 1-4 shows the front view of the DS1 output circuit pack. This circuit pack has a D connector at the front.

Figure 1-4Front view of the DS1 output circuit pack

FW-1927

DSX-1twistedpair line

EMIfilter

From WorkingDS1/VTsynchronousmapper

FromProtectionDS1/VTsynchronousmapper

Relay contactis normally open.

Relay contactis normally closed

Fastening screw

44-pin D connector



1-5

Equipping rules for the DS1 input and output circuit packs Figure 1-5 shows the slots in which DS1 input and DS1 output circuit packs can be installed in an OC-12 or OC-3 shelf. Each upper-level slot that accommodates DS1 input and output circuit packs is associated with a specific lower-level slot that accommodates a DS1 VT synchronous mapper.

Note: Cover unequipped in/out circuit pack positions with blank I/O faceplates (NT4K5830). Fill unequipped shelf slot positions with filler circuit packs (NT7E39).

Figure 1-5DS1 input and output circuit packs installed in the OC-12 or OC-3 shelf

FW-1926 (Vol 1)

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

30 32 34 36 38 40 42 44 46 48 50 52 54 55D

S1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

IN IN

OUT OUT

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1 In

DS

1 O

ut

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

DS

1/V

T M

pr

(NT

7E

04)

odd

eve

n

odd

eve

n

odd

eve

nodd

eve

n

odd

eve

n

OC-3OC-12

Note: An OC-12 can handle up to 168 DS1s (12 DS1/VT Mappers). An OC-3 Terminal can handle up to 84 DS1s (6 DS1/VT Mappers). An OC-3 ADM can handle up to 168 DS1s (12 DS1/VT Mappers).

OC-3OC-12 or OC-3 ADM

odd

eve

nodd

eve

nodd

eve

nodd

eve

n

odd

eve

nodd

eve

n

odd

eve

nodd

eve

nodd

eve

nodd

eve

n

odd

eve

nodd

eve

n

AssociatedMapperposition

odd

eve

n


1-6


Table 1-2 shows the association of slots in the OC-12 or OC-3 shelf.

DS1 VT mapper circuit pack (NT7E04)The DS1 VT mapper circuit pack provides interface circuitry between the DS1 input and output circuit packs, and the backplane STS bus (see Figure 1-6). The DS1 VT mapper circuit pack generates a half-full virtual tributary (VT) organized STS-1 signal from up to 14 DS1 signals. The DS1 signals are mapped as VT1.5 signals according to the floating DS1 asynchronous mapping provided by the SONET standard. Each circuit pack processes 14 DS1 transmit and receive signals independently. The STS-1 signals are transmitted and received by way of the backplane.

The two half-full STS-1 signals from adjacent DS1 mappers (odd and even slots) are merged on the backplane interface of the OC-3/OC-12 circuit pack to form a full STS-1 signal on the optical path.

You can perform loopbacks for link maintenance and fault detection purposes. Software controls the line build-out (LBO) range selection and can select for a range of 0 m to 200 m (0 feet to 655 feet). The following line codings are accepted: AMI, B8ZS, or AMIZCS.

Table 1-2Association of slots in the OC-12 or OC-3 shelf

DS1 protection group name

DS1 VT synchronous mapper

DS1 input circuit pack

DS1 output circuit pack

OC-12 and OC-3 ADM

OC-3 Term

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

P

1

2

3

4

11

12

13

14

15

16

17

18

19

30

31

34

35

38

39

42

43

46

47

50

51

Not applicable

32

33

36

37

40

41

44

45

48

49

52

53

Not applicable

X

X

X

X

X

X

X

X

X

X

X

X

X

—

—

—

—

—

—

X

X

X

X

X

X

X



1-7

From DS1 interface to OC-12 or OC-3 optical interface The DSI VT processor regenerates the 14 DS1 signals received from the DS1 input circuit pack, and performs DS1 clock recovery using digital phase lock loops. The system uses the recovered clock to time-regenerate each DS1 line data. Each DS1 is bit-stuffed into a SONET VT along with VT path overhead. The VTs are byte-interleaved into a VT group that is sent to a VT/STS processor where each VT group is byte-interleaved into an STS-1 format. The STS path overhead is then added. The half-full STS-1 signal travels to the OC-12 or OC-3 optical interface circuit pack where it merges with the half-full STS-1 signal from the adjacent DS1 mapper.

From OC-12 or OC-3 optical interface to DS1 interface The STS-1 signal coming from the OC-12 or OC-3 optical interface circuit pack travels to the VT/STS processor. The VT/STS processor extracts the STS path overhead, and demultiplexes the STS-1 payload into VT groups. The VT groups then travel to the DS1 VT. The DS1 VT processor extracts The DS1 signals and terminates VT path overhead. A programmable LBO circuit then regenerates the DS1 signals.

Control bus interfaceThe control bus interface (CBus) circuit that communicates with the processor through the control bus provides control and status monitoring for the DS1 VT mapper circuit pack. The CBus interface circuit also controls the Unit Fail LED (red) and the Active LED (green) located on the faceplate of the circuit pack.

Point-of-use power supply (PUPS) The DS1 VT mapper circuit pack is equipped with its own point-of-use power supply (PUPS) that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry. The PUPS are fused individually.

Alarm LED definitions Table 1-3 lists the names of the DS1 VT mapper circuit pack LEDs, the possible cause for LED activation, and how the LEDs are controlled (hardware or software).

Table 1-3DS1 VT mapper circuit pack LEDs

LED name Possible cause Controlled by

Unit fail Alarm points

• circuit pack fail

• receive STS bus parity error

Software

Active Active unit Software


1-8


Figure 1-6Block diagram of the DS1 VT mapper circuit pack

FW-1965

Provisioning options for the DS1 VT synchronous mapper The DS1 VT synchronous mapper can accept DS1 signals with the following frame formats:

• superframe (SF)

• extended superframe (ESF)

• null

The DS1 VT synchronous mapper can also accept SLC-96 DS1 signals as long as the DS1 facilities are provisioned with the following parameters:

• AMI line carding

• null framing format

• zeros alarm encoding

• asynchronous synchronization

Legend:

CBus =PUPS =

VT =STS =

Control BusPoint-of-Use Power SupplyVirtual TributarySynchronous Transport Signal

DS1/VTProcessor

VT/STSProcessor

CBusInterface

Active

UnitFail

To/FromApplication

Processor card

STS-1(To/FromOC-3 or OC-12Optical Interface)

DS11-14(To/From DS1Input/Outputcards)

VTOverhead

Insertion / Removal

STSOverhead

Insertion / Removal

CBus

PUPS+5 V dc

-4.5 V dc-48 V dc



1-9

Physical appearance of the DS1 VT synchronous mapper The DS1 VT synchronous mapper is 27.7 cm (10.9 in.) high by 25.7 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-7 shows the front view of the DS1 VT synchronous mapper.

Figure 1-7DS1 VT mapper circuit pack faceplate layout

FW-0127

Fail

ActiveActive LED (Green)Indicates the unit is processing DS1s. The circuit pack should notbe removed while this LED is lit. The LED is software controlled.

Fail LED (Red)Indicates a circuit pack failure. The LED is software controlled.

DS1VTMapper


1-10


Equipping rules for the OC-12 or OC-3 shelf

In an OC-12 shelf and an OC-3 ADM shelf, install up to twelve working DS1 VT synchronous mappers in slots 1 (G1) to 4 (G4), and 11 (G5) to 18 (G12). In an OC-3 terminal shelf, install up to six working DS1 VT synchronous mappers in slots 13 (G7) to 18 (G12). Install a protection DS1 VT synchronous mapper only in slot 19. The protection arrangement is revertive 1:N, where N≤12 for the OC-12, and N≤6 for the OC-3.

A pair of DS1 VT working mappers supplies the 28 VT1.5 signals (2 multiplied by 14 VT1.5 signals) required to fill the bandwidth of one STS-1. Install the working mappers in pairs of slots. In each pair of slots (for example, 17/18, 15/16, 13/14), the mapper in the odd-numbered slot serves the first set of 14 VT1.5 signals (1 to 14), and the even-numbered slot serves the second set of 14 VT1.5 signals (15 to 28).

CAUTIONRisk of traffic lossDeprovision unused DS3 ports before installing a DS1 VT mapper. If you do not deprovision unused DS3 ports, the DS1 traffic is not carried through the DS1 VT mapper even if the DS1 VT mapper is provisioned correctly.

If you insert mappers into slots other than those specified in the equipping rules, or configure a DS1/DS3-mix system contrary to the prescribed configurations, you can cause hits on traffic, or incorrect provisioning of the system.

If you equip a protection switcher circuit pack in slot 2, you cannot use slot 3 to provide DS1 service. Remove DS1 I/O circuit packs in slots 30 through 32 for any mix configuration. If you do not remove these circuit packs, protection traffic and the currently bridged DS3 or STS-1 traffic is affected.

Do not insert DS1 input and output circuit packs into slots other than those specified in the equipping rules.

CAUTIONRisk of preventing software downloads Seat DS1 I/O circuit packs in place correctly with screws tightened. Improperly seated I/O circuit packs can prevent software downloads.



1-11

In an OC-12 mixed system, DS1 VT mappers and DS3 STS mappers share the same slots. Thus the quantity of DS1 VT mappers to be installed depends on the quantity of DS3 STS mappers being installed.

In an OC-3 mixed system, install DS1 VT mappers after DS3 STS mappers. Once you install DS3 STS mappers, deprovision unused DS3 ports before inserting a DS1 VT mapper.

Associated I/O circuit packs Each DS1 VT synchronous mapper in the lower level of the shelf requires two circuit packs in associated slots in the upper level of the shelf. Table 1-2 shows the association of lower-level slots and upper-level slots in the TBM shelf. If a mapper in the lower level of the TBM shelf is a working unit, the associated circuit packs in the upper level must be a DS1 input circuit pack and a DS1 output circuit pack.

BNC I/O circuit pack (NT4K30) Install the BNC I/O circuit pack (formerly referred to as the DS3 I/O or the DS3 BNC I/O circuit pack) in the upper level of the TBM shelf. Each BNC I/O circuit pack handles both directions of one DS3 or STS-1 line: one DS3 or STS-1 coming into the S/DMS TransportNode, and one DS3 or STS-1 going out. An input DS3 signal enters the S/DMS TransportNode, makes its way to the BNC I/O circuit pack, and onto the associated DS3 STS mapper. An input STS-1 signal enters the S/DMS TransportNode, makes its way to the BNC I/O circuit pack, and onto the associated STS-1 electrical interface circuit pack. An output DS3 or STS-1 signal travels from the DS3 STS mapper or STS-1 interface (respectively) to the associated BNC I/O circuit pack, and out of the S/DMS TransportNode.

Functional description Each BNC I/O circuit pack has a splitter that sends the DS3 or STS-1 signal to both the associated working DS3 STS mapper circuit pack or STS-1 electrical interface circuit pack (respectively) and to the protection switcher circuit pack. (In normal operation, the signal sent to the protection switcher circuit pack terminates in that circuit pack.) Each BNC I/O circuit pack can receive DS3 signals either from the associated working DS3 STS mapper, or from the protection mapper (by way of the protection switcher circuit pack). Each BNC I/O circuit pack can also receive STS-1 signals from either the associated working STS-1 interface, or from the protection interface (by way of the protection switcher circuit pack). The BNC I/O circuit pack supports framed DS3 and STS-1 signals. Figure 1-8 illustrates these connections.

Note: The BNC I/O circuit pack also supports unframed (clear channel) DS3 signals.


1-12


In normal operation, an incoming DS3 or STS-1 signal passes through a splitter in the BNC I/O circuit pack. The signal then travels to both the associated DS3 STS mapper or STS-1 interface and the protection switcher circuit pack. The signal that goes to the protection switcher terminates on that circuit pack. The BNC I/O circuit pack receives a DS3 or STS-1 signal from the associated DS3 STS mapper or STS-1 interface. The BNC I/O circuit pack does not receive any signal from the protection switcher circuit pack.

If a protection-switching request occurs for the working DS3 STS mapper or STS-1 interface, the relays on the protection switcher circuit pack close. Incoming DS3 or STS-1 traffic travels to the associated DS3 protection mapper or STS-1 protection interface. The protection mapper or interface is synchronized to the incoming DS3 or STS-1 signals. The relays on the three associated BNC I/O circuit packs interrupt the traffic that comes from the working mapper or the working interface. Then, the relays accept the traffic that comes from the protection mapper or the protection interface by way of the protection switcher circuit pack.

Note: When a shelf is equipped with both DS3 mappers and STS-1 interfaces, install only one protection switcher circuit pack. The two services share the protection switcher circuit pack.

Figure 1-8Block diagram of the BNC I/O circuit pack

FW-1918 (R8)

Note: Heavy lines show signal flow in normal operation.

To Working DS3 STSMapper or STS-1 interfaceDS3 or STS-1

from DS3 or STS-1termination panel

= Open relay= Closed relay= Resistive termination

Legend:

To Protection switcher

From Protection switcher

From Working DS3 STSMapper or STS-1 interface

DS3 or STS-1to DS3 or STS-1termination panel



1-13

Physical appearance of the BNC I/O circuit packThe BNC I/O circuit pack is 5.7 cm (2.25 in.) high by 25.8 cm (10.15 in.) deep by 2.0 cm (0.8 in.) wide. Figure 1-9 shows the front view of the BNC I/O circuit pack. This circuit pack has two BNC-type connectors on the front.

Figure 1-9BNC I/O circuit pack

FW-1919

Equipping rules

Install I/O circuit packs individually or in sets of three. Each set of three circuit packs can handle all the input and output for a DS3 STS mapper circuit pack or an STS-1 electrical interface circuit pack (both directions of three DS3 or STS-1 signals).

Equipping rules for the OC-12 shelfIn the OC-12 shelf, install up to 12 BNC I/O circuit packs (the shelf can handle up to 12 DS3 or STS-1 signals). Install BNC I/O circuit packs in sets of three in slots 38, 39, and 40; in slots 42, 43, and 44; in slots 46, 47, and 48; and in slots 50, 51, and 52 (see Figure 1-10). Each set of three I/O circuit packs is associated with a DS3 STS mapper or STS-1 interface.

CAUTIONRisk of preventing software downloads Seat BNC I/O circuit packs in place correctly with screws tightened. Improperly seated I/O circuit packs can prevent software downloads.

Out

In

Fastening screw


1-14 Circuit pack descriptions

Figure 1-10 BNC I/O circuit packs installed in the OC-12 shelf

FW-3039

Legend:

DS3 Mpr =ESI =MIC =

OC-12 =Pwr =SIL =

STS-1 I/F =

DS3 to Synchronous Transport Signal Mapper (NT7E08)External Synchronization InterfaceMaintenance Interface CardOC-12 Interface Power Termination CardSide Interconnect Left CardSTS-1 Tributary Interface Card (NT7E09)

Optical Interfaces(NT7E02)

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

SIL

Ope

ratio

ns C

ontr

olle

r (O

PC

)(N

T7E

24)

OC-12G1

OC-12G2 M

IC (

NT

4K53

)

Pro

cess

or C

ard

(NT

4K52

)

30 32 34 36 38 40 42 44 46 48 50 52 54 55

ES

I

BNC I/O card (NT4K30)or

Blank I/O faceplate (NT4K5830) (Note)

ESI Carrier (NT7E19)equipped with

2 ESI units (NT7E27)

BN

C I/

O

Pw

r

Pw

r

BN

C I/

O

BN

C I/

O

DS

3 M

pr (

Pro

t) (

NT

7E08

)

Pro

tect

ion

Sw

itche

r (N

T4K

60)

BN

C I/

O

BN

C I/

O

BN

C I/

O

BN

C I/

O

BN

C I/

O

BN

C I/

O

BN

C I/

O

BN

C I/

O

BN

C I/

O

IN IN

OUT OUT

ES

I

Note: Unused In/Out card positions must be equipped with blank I/O faceplates (NT4K5830).

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

DS

3 M

pr o

r S

TS

-1 I/

F

ST

S-1

I/F

(P

rot)

(N

T7E

09)

DS

3 M

pr o

r S

TS

-1 I/

F

DS

3 M

pr o

r S

TS

-1 I/

F

DS

3 M

pr o

r S

TS

-1 I/

F


Circuit pack descriptions 1-15

Table 1-4 shows the set of three I/O circuit packs as associated with a DS3 STS mapper or STS-1 interface.

Equipping rules for the OC-3 shelfIn the OC-3 terminal shelf, install up to three BNC I/O circuit packs (the OC-3 signal can handle up to three DS3 or STS-1 signals). In the OC-3 add-drop multiplexer (ADM) shelf, install up to six BNC I/O circuit packs (the ADM shelf can handle up to three DS3 or STS-1 signals from each direction because no STS-1 signals are passed through). Install the circuit packs in sets of three in slots 38, 39, 40, and 42, 43, 44 (see Figure 1-11). Each set of three BNC I/O circuit packs is associated with a DS3 STS mapper or STS-1 interface (see Table 1-5 and Figure 1-11).

Table 1-4Association of BNC I/O circuit packs with DS3 STS mappers or STS-1 interfaces in the OC-12 shelf

DS3 or STS-1 protection group name

DS3 STS mapper or STS-1 interface slots

BNC I/O circuit pack slots

Port 1 Port 2 Port 3

G1

G2

G3

G4

11

13

15

17

38

42

46

50

39

43

47

51

40

44

48

52

Table 1-5Association of BNC I/O circuit packs with DS3 STS mappers or STS-1 interfaces in the OC-3 shelf

DS3 or STS-1 protection group name

DS3 STS mapper or STS-1 interface slots

BNC I/O circuit pack slots OC-3 shelf

Port 1 Port 2 Port 3

G1

G2

11

13

38

42

39

43

40

44

X

X



Figure 1-11BNC I/O circuit packs installed in the OC-3 shelf (terminal application)

FW-3040

Legend:

DS3 Mpr =ESI =MIC =

OC-3 =Pwr =SIL =

STS-1 I/F =

DS3 to Synchronous Transport Signal Mapper (NT7E08)External Synchronization InterfaceMaintenace Interface CardOC-3 Interface Power Termination CardSide Interconnect Left CardSTS-1 Tributary Interface Card (NT7E09)

Optical Interfaces(NT7E01)

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

SIL

Ope

ratio

ns C

ontr

olle

r (O

PC

)(N

T7E

24)

OC-3G1

OC-3G2 M

IC (

NT

4K53

)

Pro

cess

or C

ard

(NT

4K52

)

30 32 34 36 38 40 42 44 46 48 50 52 54 55

ES

I

BNC I/O card(NT4K30)

ESI Carrier (NT7E19)equipped with

2 ESI units (NT7E27)

BN

C I/

O

Pw

r

Pw

r

BN

C I/

O

BN

C I/

O

DS

3 M

pr (

Pro

t) (

NT

7E08

)

Pro

tect

ion

Sw

itche

r (N

T4K

60)

DS

3 M

pr o

r S

TS

-1 I/

FIN IN

OUT OUT

Note: Unused In/Out card positions must be equipped with blank I/O faceplates (NT4K5830).

ES

I

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

Bla

nk I/

O

ST

S-1

I/F

(P

rot)

(N

T7E

09)

or



DS3 STS mapper circuit pack (NT7E08) The DS3 STS mapper circuit pack provides interface circuitry between BNC I/O circuit packs and the backplane STS bus (see Figure 1-12). The DS3 STS mapper circuit pack generates an STS-1 signal (non-VT organized) from a DS3 signal (framed or unframed). Each circuit pack processes up to three DS3 transmit and receive signals independently. STS-1 signals are transmitted and received by way of the backplane STS buses.

Loopbacks can be performed for link maintenance and fault detection purposes. The line build-out (LBO) range selection is under software control and can be selected for long or short range (the length depends on the type of cable used).

From BNC I/O circuit packs to OC-12 or OC-3 optical interface Three BNC I/O circuit packs process three received DS3 signals, performing line equalization, clock recovery, and data regeneration. Regenerated DS3 signals travel to the DS3/STS processor which performs DS3 performance monitoring. Then, the DS3/STS processor bit stuffs each DS3 into a SONET STS-1 format and adds the STS path overhead. The three STS-1 signals coming out of the DS3 STS mapper circuit pack then travel to the OC-12 or OC-3 optical interface circuit pack.

From OC-12 or OC-3 optical interface to BNC I/O circuit packThree BNC I/O circuit packs process three STS-1 signals received from the OC-12 or OC-3 optical interface circuit pack. The circuit packs retime the STS-1 signals, extract the DS3 signal from each STS-1, then terminate the STS path overhead. The outgoing DS3 clock rate depends on the average (after pointer smoothing) DS3 data rate contained in the STS-1 SPE. The circuit packs frame outgoing DS3 signals, and monitor the DS3 parity prior to being B3ZS-encoded. DS3 signals then travel through a line driver circuit. A programmable LBO circuit generates the line signal.

Unframed DS3 clear channelThe DS3 STS mapper circuit pack has the built-in capability to carry unframed DS3 clear channel signals. The circuit pack processes the unframed signal in the same way it processes a standard DS3, except that it does not insert an alarm indication signal (AIS) upon detection of an unframed DS3 signal. Processor software does not process status messages provided by the mapper (LOF, parity error). The DS3 STS mapper circuit pack provides path performance monitoring counts. The counts are invalid but are displayed by the processor in the DS3 Facility screens. The circuit pack does not detect an unframed all-ones (111...), thus no AIS is inserted under this condition.



Control bus interface (CBus) The control bus interface (CBus) circuit that communicates with the Proc circuit pack through the control bus provides control and status monitoring for the DS3 STS mapper circuit pack. The CBus interface circuit also controls the Unit Fail LED (red), the Active LED (green), and the three DS3 LOS (loss of signal) LEDs (yellow) located on the faceplate of the circuit pack.

Point-of-use power supply (PUPS) The DS3 STS mapper circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry.

Alarm LED definitions Table 1-6 lists the names of the DS3 STS mapper circuit pack LEDs, the possible cause for LED activation, and how the LEDS are controlled (hardware or software).

On a DS3/STS-1 mix shelf, the DS3 STS mapper and STS-1 interface protection circuit packs share the same protection switcher. The protection switcher is bridged to only one of the protection circuit packs at a time. This bridge alternates every 60 minutes.

The LOS LEDs on the protection circuit pack are disabled whenever the circuit pack is not bridged. When bridged, the LOS LEDs mirror the LOS LEDs on the working circuit pack. As a result, when the alternating bridge feature is activated and if the unused channels are not put out of service, the LOS LEDs on the protection circuit packs change state every 60 minutes.

Table 1-6DS3 STS mapper circuit pack LEDs


Unit Fail Alarm points

• component fail


Software

Active Active unit Software

LOS1 DS3 No. 1 loss of signal Hardware





Figure 1-12Block diagram of the DS3 STS mapper circuit pack

FW-1970 (TBM)

DataRegenerator

CBus

CBusInterface

UnitFail Active

Path Overheadinsertion/removal

3 STS-1s(To/from OC-3 or OC-12 optical interfaces)

DS31 - 3(To/from DS3BNC I/O cards)

To/fromProcessor card

Legend:

CBus =PUPS =

STS =

Control BusPoint-of-Use Power SupplySynchronous Transport Signal

LineDriver

LOS 3 LOS 2 LOS 1

DS3/STS

Processor

PUPS

+5 V dc

+12 V dc-48 V dc-4.5 V dc

-12 V dc



Physical appearance of the DS3 STS mapper The DS3 STS mapper is 27.7 cm (10.9 in.) high by 26.7 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-13 shows the front view of a DS3 STS mapper.

Figure 1-13Front view of a DS3 STS mapper

FW-0129.1

Fail

LOS 3

Active

LOS 2

LOS 1LOS LEDs (yellow)Indicates a failure or a loss of an incoming DS3 signal on ports 1, 2, or 3.The LEDs are hardware or software controlled. (Note: If both optical cardsare removed, LOS LEDs may light on the Protection Mapper.)

Active LED (green)Indicates that the unit is processing DS3s. The Mapper should not be removedwhile this LED is lit. The LED is software controlled.

Fail LED (red)Indicates a circuit pack failure or the detection of a backplane parity error.The LED is software controlled.



Equipping rules for the OC-12 or OC-3 shelf

In an OC-12 shelf, install up to 4 working DS3 STS mappers in slots 11 (G1), 13 (G2), 15 (G3), and 17 (G4). In an OC-3 terminal shelf, install only one working DS3 STS mapper (slot 11, G1). In an OC-3 ADM shelf, install up to two working DS3 STS mappers (slots 11, G1 and 13, G2). Install one protection DS3 STS mapper in slot 1 of both the OC-12 and OC-3 shelf. Install a protection switcher circuit pack in slot 2. The protection arrangement is revertive 1:N where N≤4 for the OC-12, N≤2 for the OC-3 ADM, and N=1 for the OC-3. Do not install a working DS3 STS mapper in an even-numbered slot.

CAUTIONRisk of traffic lossDeprovision unused DS3 ports before installing a DS1 VT mapper. If you do not deprovision unused DS3 ports, the DS1 traffic is not carried through the DS1 VT mapper even if the DS1 VT mapper is provisioned correctly.

If you insert mappers into slots other than those specified in the equipping rules, or configure a DS1/DS3-mix system contrary to the prescribed configurations, you can cause hits on traffic, or incorrect provisioning of the system.

If you equip a protection switcher circuit pack in slot 2, you cannot use slot 3 to provide DS1 service. Remove DS1 I/O circuit packs in slots 30 through 32 for any mix configuration. If you do not remove these circuit packs, protection traffic and the currently bridged DS3 or STS-1 traffic is affected.

Do not insert DS1 input and output circuit packs into slots other than those specified in the equipping rules.

CAUTIONRisk of preventing software downloads Seat DS1 I/O circuit packs in place correctly with screws tightened. Improperly seated I/O circuit packs can prevent software downloads.



You can mix DS3 tributaries with DS1, STS-1, and OC-3 tributaries on the same shelf. When mixing DS3 and STS-1 services, equip slots 11, 13, 15, and 17 with either DS3 mapper or STS-1 interface circuit packs (all combinations are supported). When a shelf is equipped with both DS3 mappers and STS-1 interface circuit packs, the circuit packs share the protection switcher circuit pack (in slot 2).

Note: Install OC-3 tributaries only in an OC-12 shelf.

In an OC-12 mixed system, the DS1 VT mappers and DS3 STS mappers share the same slots. Thus the quantity of DS1 VT mappers to be installed depends on the quantity of DS3 STS mappers being installed.

In an OC-3 mixed system, install the DS3 STS mapper before the DS1 VT mappers. Once you install the DS3 STS mappers, deprovision the unused DS3 ports before inserting a DS1 VT mapper.

DS3 STS mapper circuit pack (NT7E08BA)Combined with OC-12 Release 14 software, the NT7E08BA circuit pack provides C-bit transparency, providing the ability to evolve to data oriented transmissions and allow C-bit based performance monitoring.

STS-1 electrical interface circuit pack (NT7E09)The STS-1 electrical interface circuit pack provides interface circuitry between the BNC I/O circuit packs and the OC-3 or OC-12 optical interface circuit packs (Figure 1-14). Each STS-1 electrical interface circuit pack processes up to three STS-1 transmit and receive signals independently. The STS-1 signals are transmitted and received by way of the backplane STS buses.

You can perform loopbacks for link maintenance and fault detection purposes. Software controls the line build-out (LBO) range selection, and can select for long or short range (the length depends on the type of cable used).

From the BNC I/O circuit packs to the OC-12 or OC-3 optical interfaceThree BNC I/O circuit packs process three received STS-1 signals. The circuit packs perform line equalization, clock recovery, and data regeneration. Regenerated STS-1 signals then travel to the STS-1 processor. The STS-1 processor performs B3ZS decoding, STS-1 framing, and performance monitoring. The STS-1 processor then bulk maps each STS-1, and adds the STS path overhead. Three STS-1 signals coming out of the STS-1 interface circuit pack then travel to the OC-3 or OC-12 optical interface circuit pack.

From the OC-12 or OC-3 optical interface to the BNC I/O circuit packs Three BNC I/O circuit packs process three STS-1 signals received from the OC-3 or OC-12 optical interface circuit pack. The circuit packs retime these STS-1 signals, and remove the STS path overhead. Then the circuit packs



frame and scramble outgoing STS-1 signals are framed, and monitor the signal parity prior to being B3ZS encoded. STS-1 signals then travel through a line-driver circuit, and a programmable LBO circuit generates the line signal.

Control bus interfaceThe control bus interface (CBus) circuit that communicates with the processor circuit pack through the control bus provides control and status monitoring for the STS-1 interface circuit pack. The CBus interface circuit also controls the Fail LED (red) located on the faceplate of the circuit pack.

Point-of-use power supply (PUPS)The STS-1 interface circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry.

Alarm LED definitionsTable 1-7 lists the names of the STS-1 interface circuit pack LEDs, the possible cause for LED activation, and how LEDs are controlled (hardware, software, or firmware).

On a DS3/STS-1 mix shelf, the DS3 STS mapper, and STS-1 interface protection circuit packs share the same protection switcher. The protection switcher is bridged to only one of the protection circuit packs at a time. This bridge alternates every 60 minutes.

The LOS LEDs on the protection circuit pack are disabled whenever the circuit pack is not bridged. When bridged, the LOS LEDs mirror the LOS LEDs on the working circuit pack. As a result, when the alternating bridge feature is activated and if the unused channels are not put out of service, the LOS LEDs on the protection circuit packs change state every 60 minutes.

Table 1-7STS-1 interface circuit pack LEDs


Fail Alarm points

• component fail


Software

Active Active unit Firmware

LOS1 STS-1 No. 1 loss of signal Hardware/Firmware





Equipping rules for the OC-12 or OC-3 shelfThe equipping rules for the working STS-1 interface circuit packs are identical to the equipping rules for the working DS3 STS mappers. In an OC-12 shelf, install up to four working STS-1 interfaces in slots 11 (G1), 13 (G2), 15 (G3), and 17 (G4). In an OC-3 terminal shelf, install one working STS-1 interface in slot 11 (G1). In an OC-3 ADM shelf, install up to two working STS-1 interfaces (slots 11, G1, and 13, G2). Install one protection STS-1 interface in slot 3 of both the OC-12 and OC-3 shelf. Install a protection switcher circuit pack in slot 2. The protection arrangement is revertive 1:N where N≤4 for the OC-12, N≤2 for the OC-3 ADM, and N=1 for the OC-3.

You can mix the STS-1 tributaries with DS1, DS3, and OC-3 tributaries on the same shelf. When mixing DS3 and STS-1 services, equip slots 11, 13, 15, and 17 with either DS3 mapper or STS-1 interface circuit packs (all combinations are supported). When a shelf is equipped with both DS3 mappers and STS-1 interface circuit packs, the services share the protection switcher circuit pack (in slot 2).

Note: Install OC-3 tributaries only in an OC-12 shelf.

See System Description, 323-1111-100, for more information on the shelf configurations.



Figure 1-14Block diagram of the STS-1 electrical interface circuit pack

FW-0086(TBMR8)

DataRegenerator

CBus

CBusInterface

Line and Section Overhead

Insertion/Removal

(3 STS-1s)

STS-11 - 3(to/from BNC I/Ocards)


Legend:

CBus =PUPS =

STS =


STS-1Processor

PUPS

+5 V dc

+12 V dc-48 V dc-4.5 V dc

-12 V dc

LineDriver

and LBO

To optical interfaces

(3 STS-1s)

FW-0086 (TBM R8)

From optical interfaces

UnitFail

Active LOS 3 LOS 2

Micro-controller

LOS 1



Physical appearance of the STS-1 interfaceThe STS-1 interface circuit pack is 27.7 cm (10.9 in.) high by 26.7 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-15 shows the front view of a STS-1 interface.

Figure 1-15Front view of the STS-1 interface

FW-0129.2

Fail

LOS 3

Active

LOS 2

LOS 1LOS LEDs (yellow)Indicates a failure or a loss of an incoming STS-1 signal on ports 1, 2, or 3.The LEDs are hardware or software controlled. (Note: If both optical cardsare removed, LOS LEDs may light on the protection STS-1 interface.)

Active LED (green)Indicates the unit is processing STS-1s. The interface should not beremoved while this LED is lit. The LED is software controlled.




Protection switcher circuit pack (NT4K60) Install the protection switcher circuit pack in the lower level of the shelf. Install this circuit pack if protection switching is provided for the working DS3 STS mappers or STS-1 interfaces. If protection is provided, install the protection switcher in slot 2. If a fault occurs in a working DS3 STS mapper, the protection switcher routes the traffic away from the faulty mapper to a protection mapper. If a fault occurs in a working STS-1 interface, the protection switcher routes the traffic away from the faulty interface to a protection interface. The protection switcher reroutes the traffic by switching the connections to the BNC I/O circuit packs.

Functional description All working DS3 STS mappers or STS-1 interfaces are normally connected to BNC I/O circuit packs. Each mapper or interface that can process both directions (receive and transmit) of up to three DS3 or STS-1 signals is connected to a set of three BNC I/O circuit packs. Each mapper or interface that can process both directions of only one DS3 or STS-1 signal is connected to a single BNC I/O circuit pack.

Each BNC I/O circuit pack is connected to the protection switcher as well as to the associated working mapper or interface. In normal operation, the signals that the protection switcher receives from the BNC I/O circuit packs are terminated. When a protection-switching request occurs for one of the working DS3 STS mappers or STS-1 interfaces, the protection switcher connects the three BNC I/O circuit packs to a protection DS3 STS mapper or a protection STS-1 interface (respectively). The protection arrangements are revertive (1:N). When the fault clears the protection switcher reconnects the three BNC I/O circuit packs to the working DS3 STS mapper or STS-1 interface.

Note: When a shelf is equipped with both DS3 STS mapper and STS-1 interface circuit packs, the two services share the protection switcher circuit pack (in slot 2). As a result of this sharing, both service types are 1:N protected but only one service type can be protected at one time.



Figure 1-16 shows the connections to the protection switcher. Each direction has separate connections and relays.

Figure 1-16Connections to the protection switcher circuit pack

FW-1946(R8)

Connections to the12 DS3 or STS-1 signalsserving the fourBNC I/O circuit packs

For traffic flowing from the BNC I/O circuit packstoward the DS3/STS mappers or STS-1 interfaces:

RelaysConnection tothe DS3/STS protectionmapper in slot 1 or the STS-1protection interface in slot 3

For traffic flowing from the DS3/STS mappers or STS-1 interfacestoward the BNC I/O circuit packs:

Relays

Connections from the12 DS3 or STS-1 signalsserving the fourBNC I/O circuit packs

Connection tothe DS3/STS protectionmapper in slot 1 or the STS-1protection interface in slot 3



Figure 1-17 shows a functional block diagram of the 1:N protection switcher.

Figure 1-17Block diagram of the 1:N protection switcher circuit pack

FW-1947(R8)

Bus connections CBus The protection switch is connected to the CBus in the TBM shelf.

To DS3 mapperor STS-1 interfacecircuit packused for protection

From BNC I/Ocircuit pack(3 DS3s orSTS-1s In)

= Normally Open= Normally Closed= Resistive Termination

Legend:

1:N Protection switcher

To BNC I/Ocircuit pack(3 DS3s orSTS-1s Out)

From DS3 mapperor STS-1 interfacecircuit packused for protection



Physical appearance of the protection switcher circuit pack The protection switcher is 27.7 cm (10.9 in.) high by 25.6 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in. cm) wide. Figure 1-18 shows the front view of the protection switcher.

Note: Figure 1-18 shows the NT4K60AA version of the circuit pack which has an Active LED. The NT4K60BA version of the circuit pack does not have an Active LED.

Figure 1-18Front view of the protection switcher circuit pack

FW-1944

Fail

Active

DS3ProtSwtch

Note: The NT4K60BA version of this circuit pack does nothave the Active LED.

Active LED (Green)Indicates that DS3 or STS-1 protection switching is active.

Fail LED (Red)Indicates a protection switcher circuit pack failure.



Equipping rules for the OC-12 or OC-3 shelfInstall the protection switcher circuit pack (NT4K 60) in slot 2 whenever protection switching is to be provided for the working DS3 STS mapper or STS-1 interface circuit packs (see Figure 1-19).

Figure 1-19Protection switcher circuit pack installed in the shelf

FW-1926.5-Vol1

External synchronization interface carrier (NT7E19)The external synchronization interface carrier circuit pack provides the mechanical support and the electrical connections for two external synchronization interface (ESI) circuit packs (see Figure 1-20). The main function of the carrier is to route two distinct timing reference signals between the shelf connector, the OC-12 interface and the ESI units.

Functional descriptionThe MBus and the timing signal inputs going in the ESI carrier are split in two. The ESI carrier routes these signals to each ESI unit.

The different timing signals from the ESI unit travel through the ESI carrier shelf connector to the OC-12 interface.

Equipping rulesInstall the ESI carrier in slot 23 of the TBM shelf.

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

Pro

tect

ion

Sw

itche

r

30 32 34 36 38 40 42 44 46 48 50 52 54 55

IN IN

OUT OUT

Protection Switcher(NT4K60)



Figure 1-20External synchronization interface carrier—physical layout

FW-1972

Locking latch 2

Locking latch 1

Fastener (Rotate 45°clockwise to lock subunitinto the ESI carrier)

Slide into theESI carrier

Locking latches 1 and 2 must be secured in place before inserting the ESI subunits.Remove ESI subunits before removing the ESI carrier.

Note:

Lockedposition

ESI subunitcircuit packs

Slot on latch for inserting an

insulated tipscrewdriver

(using sleeving or electrical tape)

Small diameter insulated tip screwdriver (using sleeving or electrical tape) used to unlock and extract carrier

latches after ESI subunitsare removed

ESI carrier



External synchronization interface (ESI) unit (NT7E27)The external synchronization interface (ESI) unit provides the TBM shelf with the capability of increasing the quality of its shelf timing by synchronizing the shelf to an external timing source. The ESI unit also provides derived timing signals externally.

The ESI unit can perform the following functions:

• receive timing reference signals from an external reference timing source, such as a building-integrated timing source (BITS), and use them to provide the timing reference to the TBM shelf

• derive timing reference signals from the received primary optical interface, and use them to provide the timing reference to the TBM shelf

• provide external access to timing reference signals produced by the ESI, so that they can be used as a timing reference input to a BITS

The system connects to the external timing source using a cable attached to a connector on the left wing of the TBM shelf.

Receiving timing signals from the BITSThe primary function of the ESI unit is to receive timing reference signals from an external reference timing source, such as a building integrated timing supply (BITS), and provide a stable reference frequency to the TBM shelf. The shelf derives its system clock from this reference frequency, and synchronizes all data transmission to this reference. This synchronization makes it possible to integrate S/DMS TransportNode into a synchronous network.

The OC-12 or OC-3 optical interface circuit packs use the reference clock generated by the working ESI unit to

• phase-lock the system clock that is used for local timing

• provide the transmit system clock for the optical channels

The processor circuit pack directs the ESI unit to select one of the following external timing sources:

• a pair of DS1 timing references (from a BITS)

• a pair of 8 kHz signals derived from the primary optical signals received on the shelf

ESI line timingThe capability to derive a shelf reference signal from received optics permits ADM network elements to be synchronized in the network without requiring access to an external clock source. When an ADM is ESI line timed, the optical signal is routed to the ESI unit as the reference signal. The ESI unit produces the shelf timing signal to meet synchronization requirements, and provides holdover.



Transmitting timing signals to the BITS The ESI unit also transmits timing-specific DS1 reference signals to a building timing reference clock such as a BITS. In this case, the ESI unit derives the DS1 timing signal from received primary optical signals. This function of the ESI unit facilitates the development of a SONET-based timing distribution system.

Functional descriptionEach ESI unit has the following functional blocks (see Figure 1-21):

• microcontroller

• voltage-controlled oscillator

• system clock interface

• external clock interface

• timing-reference selector

• CBus interface to the shelf processor circuit pack

• PUPS

MicrocontrollerThe microcontroller controls the voltage-controlled oscillator by providing a voltage in the range 0 to +9 V, that controls the speed of the oscillator in 4096 steps. The microcontroller circuit pack adjusts the voltage, so the oscillator output frequency remains synchronized to the timing reference. If the reference signal received by the microcontroller fails, its output voltage remains at its current value for up to 24 hours, supporting a holdover mode that exceeds the stability requirements of a stratum 3 clock.

Voltage-controlled oscillator The oscillator produces the output timing signals of the ESI unit. Its frequency is determined by a control voltage received from the microcontroller.

System interface block The system interface block receives the 8 kHz timing references that are derived from the received optical signal or an incoming DS1 tributary.

External interface block The external interface block receives the timing signals from the external source such as the BITS. From the BITS, the ESI unit receives a DS1 or composite clock timing signal. The DS1 timing signal is a framed, all-ones, bipolar return-to-zero line format with a 50 percent duty cycle. The composite clock signal is a return-to-zero format with a 5/8 duty cycle. The basic waveform provides a 64 kb/s clock, and a bipolar violation every eight pulses provides an 8 kb/s clock.



Timing-reference selector The timing-reference selector has two functions. First, under the control of the shelf processor circuit pack, it selects an external timing reference signal that is to be used by the ESI unit. It switches from one reference signal to another, if a reference signal fails. Second, it compares the phasing of the external signal to the output of the oscillator and provides the microcontroller with an indication of the difference.

DS1 generatorThe DS1 generator is used to transmit a DS1 timing reference output that is synchronized to the timing source that is selected by the timing-reference selector.

CBus interface to the shelf processor circuit packThe interface to the shelf processor circuit pack is by way of the CBus. The interface is for status and control information.

Point-of-use power supply (PUPS)Each of the two ESI units is individually powered by a PUPS that supplies the following voltages: -4.5 V dc, +5 V dc, and +12.5 V dc.

Figure 1-21Block diagram of the external synchronization interface

FW-1939 (TBM)

Systeminterfaceblock

Externalinterfaceblock

8-kHzreferencesfrom high-speed cards

DS1 timingreference inputs

Timingref.selector

38.88/51.84MHzoscillator

Referenceclock tohigh-speedcards

CBusInterface

PUPS

CBus Status and control

-48 V -4.5 V+5 V+12.5 V

Micro-controller

DS1Generator

DS1 timingreferenceoutput

8-kHzreferencesfrom tributaries

2

2

2



Physical appearance of the ESI equipment The ESI carrier is 29.2 cm (11.5 in.) high by 25.8 cm (10.2 in.) deep. It is 2.0 cm (0.8 in.) wide. Figure 1-22 shows the front view of the ESI carrier, with two ESI units installed.

Figure 1-22Front view of the external synchronization interface carrier, with two ESI units installed

FW-1940

Active

Fail

Active

Fail

Active LED (green)Indicates that the circuit pack is active and can be used totime the shelf. The circuit pack should not be removed whenthis LED is lit. The LED is software controlled.

Fail LED (red)Indicates a circuit pack failure. The LED is software controlled.

ExtSyncIF

ExtSyncIF



Equipping rules for the OC-3 or OC-12 shelf An ESI unit can be installed in the top and bottom slots of the ESI carrier, which is located in slot 23 of the TBM shelf, as shown in Figure 1-23.

Figure 1-23ESI installed in the TBM shelf

FW-1926.1-Vol1

Maintenance interface controller circuit pack (NT4K53) The maintenance interface controller (MIC) circuit pack is installed in the lower level of the shelf. It performs the following major functions:

• The MIC circuit pack gathers and distributes alarm data:

— It scans the on/off condition of internal and external hardware (breakers, switches, and miscellaneous internal hardware), and notifies the processor circuit pack when a change of state occurs.

— When installed in an S/DMS TransportNode at a central office, it can receive parallel-telemetry data.

— It drives signals for the LEDs on the circuit packs that indicate circuit-pack failure. It controls circuits for alarm lights on the BIP.

— It controls the signal-distribution relays that can send signals (such as alarms) to parallel-telemetry systems.

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

30 32 34 36 38 40 42 44 46 48 50 52 54 55

ES

I

IN IN

OUT OUT

ES

IESI Carrier (NT7E19)

equipped with2 ESI units (NT7E27)



• It activates signals that open and close the relays in the DS1, DS3, or STS-1 signal paths (on the DS1 input circuit pack, DS1 output circuit pack, BNC I/O circuit pack, and protection switcher circuit pack).

• It supports human-machine interfaces. It has two ports, one for DTE-type devices, and one for DCE-type devices.

• It handles orderwire for voice-frequency communication by way of the SONET overhead bus (SOH bus) and for access to the public switched telephone network.

Functional description Figure 1-24 shows the block diagram of the MIC circuit pack. Subsequent sections explain the functions of each part shown in the diagram.

CBus interface The MIC circuit pack is connected to the CBusA. The interface to the CBusA is the main control interface of the MIC circuit pack. When the processor circuit pack gains control of the CBusA, it can read and write various registers in the MIC circuit pack. The CBusA operates in both non-multiplexed and multiplexed modes, using 8-bit and 16-bit transfers. The CBus interface does address and data buffering, address decoding, and an IDPROM. (There is no access to the MIC circuit pack by way of the CBusB.)

EEPROM The MIC circuit pack has 32 kbytes of nonvolatile electrically-erasable programmable read only memory (EEPROM). This memory is accessed by the CBusA only.

General-support block The general-support block of the MIC circuit pack includes the following components:

• a dual serial communications controller (SCC), which supports:

— a port to which you can connect a DTE-type device such as a local VT100-type terminal

— a port to which you can connect a line from a DCE device, such as a modem

• a performance monitoring clock and a time-of-day clock

CAUTIONRisk of disabling non-volatile storage (NVS), telemetry, and protection switchingTaking the MIC circuit pack out of service affects the PM counts, and disables NVS, telemetry, and DS1/DS3/STS-1 protection switching.



The SCC in the general support block provides the serial communication links that are used for human-machine interfaces.

The SCC supports an RS-232C port that has a 25-pin D connector on the local craft access panel (LCAP). This port provides a direct interface (no modem required) for a DTE-type device such as a VT100-type terminal. This port is the human-machine interface to the processor circuit pack.

The SCC also supports an RS-232C port that has a 9-pin D connector on the side interconnect left (SIL) circuit pack on the TBM shelf. This port provides an interface for a remote terminal. The remote terminal must be connected to an external modem, and the line from the modem connects to the 9-pin connector on the SIL circuit pack.

The general support block also includes two clocks: the performance- monitoring clock and the time-of-day clock. The performance-monitoring clock provides a one-second-rate clock for performance monitoring. The time-of-day clock is accessible to the processors over the CBusA to time-stamp events. Both clocks are driven by the frame pulse received from the OC-12 or OC-3 optical interface circuit packs. The frame pulse reaches the MIC circuit pack by way of the SOH bus.



Figure 1-24Block diagram of the maintenance interface circuit pack

FW-1941

Scan points, internal/external The scan points provide a means for S/DMS TransportNode to monitor on/off conditions, both inside the bay (internal conditions) and outside it (external conditions). An on or off condition is represented by the presence or absence of logic ground at a scan point. There are 17 internal scan points and 11 external scan points. The MIC circuit pack copies the contents of scan points into a buffer, and the processor circuit pack reads the buffer to get a snapshot of all the scan points in the group. The buffer holds the results of up to 16 scan points.

CBusInterfaceCBusA

Internaldrivepoints

Externaldrivepoints

Scanpoints

Orderwire

LEDsProtectionrelays

Switches andbreakers

PUPS

CBus

Time-of-dayclock and

performancemonitoring clock

Headset, handset(posts or jackson LCAP)

NVS

-48V dc

+5V dc+12V dc-12V dc

RS-232user interface

port

RS-232user interface

port

UI port 2DCE port,(D connectoron the LCAP)

UI port 1DTE port,(D connectoron the sideinterconnectleft circuit pack)

Central-officealarms, E2A,Parallel telemetryOut

Parallel telemetryIn

From Orderwireextension connectoron the sideinterconnect left

SOH busProcessor

RS-422Serial Telemetry

ports (2)TBOS(D connector on theside interconnect left circuit pack)



In an S/DMS TransportNode at a central office, the external scan points are normally used to receive control signals from a parallel telemetry system; in an S/DMS TransportNode at a remote location, the external scan points are normally used to receive information about environmental conditions (for example, whether a door is opened or closed).

To read some of the external scan points, the processor circuit pack needs the assistance of the orderwire microcontroller. The orderwire microcontroller (in the orderwire block) polls external lines. It also scans the external scan points and reports any state changes to the processor circuit pack.

Drive points, internal/external The MIC circuit pack contains internal drive points and external drive points.

Internal drive points control the LEDs mounted on the circuit packs and on the local craft access panel (LCAP). Internal drive points also control the relays that reroute DS1, DS3, and STS-1 traffic when protection switching is required. (For DS1 traffic, those relays are located on the DS1 input circuit packs and on the DS1 output circuit packs; for DS3 or STS-1 traffic, the relays are located on the BNC I/O circuit packs and on the protection switcher circuit pack.)

Under normal conditions, the processor circuit pack controls local alarms. It writes the internal drive points by way of the CBus. If needed, the processor circuit pack can also read the contents of some of the internal drive points. (Each drive point is composed of eight bits.)

Note: If the Proc fails or if the MIC circuit pack fails, alarms are still generated in an unambiguous manner. Hardware on the MIC circuit pack and the BIP provides this fail-safe feature.

External drive points are drivers for the relays on the alarm circuit pack of the BIP. Other external drive points control signal-distribution relays on the MIC circuit pack. The relays can send signals to parallel telemetry systems.

Dual ports for serial telemetryThe MIC circuit pack has two ports that can be used for general purpose communication with the processor circuit pack. The ports are implemented in a dual serial communications controller (SCC). The SCC is a dual universal asynchronous receiver transmitter (UART). For the physical layer, each port uses the RS-422 standard, which requires two twisted pairs for each port, one for each direction of transmission. The processor circuit pack can configure each port independently, controlling baud rate, parity, and synchronous or asynchronous operation. Shielded or unshielded cable can be used, tied at one end, or at both ends to equipment ground.



The MIC circuit pack uses these two ports for serial telemetry. The connection to the ports is by way of a single 25-pin connector located on the SIL circuit pack.

One example of a serial-telemetry system is Telemetry Byte-Oriented Serial (TBOS), a 2400-baud ASCII-format asynchronous alarm-reporting system. If a port is used for the TBOS application, 26-gauge cable must be used. The external cable, if shielded, can be grounded only at the transmitting end.

Orderwire The orderwire block is a means of providing VF communications between maintenance personnel at different sites or network elements. The orderwire service complies with SONET orderwire requirements and maintains commonality where necessary with existing orderwire procedures in transport products that are not SONET-based.

The orderwire block supports local orderwire and express orderwire. These channels enable craftspersons at different network elements to communicate with each other. Express and local orderwire channels are carried in the SONET overhead, and carried between the processor circuit pack and the MIC circuit pack by the SOH bus.

Note: Craftspersons can continue to use orderwire as long as the MIC circuit pack and the SONET links are functional, even if there is not a working processor circuit pack in the shelf.

The orderwire block contains a conference bridge. The conference bridge monitors all the links and monitors the VF ports on the MIC circuit pack, and connects the two strongest speakers to the listener. The conference bridge monitors the SOH buses which carry the express and local orderwire channels. Signaling to the remote end of orderwire is done by DTMF tones.

Using orderwire to access the public switched telephone networkThe local or express orderwire channel can be used to access the public switched telephone network (PSTN). Access to the PSTN is by way of a two-wire port on the MIC that is wired to connector J14, pins 35 and 36, on the side interconnect left circuit pack. In the central office, these pins are connected to the local switch using an NT7E44UA cable.

To access the PSTN, the craftsperson plugs a handset or headset into the LCAP jacks and dials the NE site ID and 9. This causes the MIC in the network element at the central office to connect the VF path to an outside line of the public switched telephone network. The LCAP tone and lamp are not activated in this case. The craftsperson can then dial a public telephone number. To release the connection, the craftsperson unplugs the headset or handset.

Point-of-use power supply (PUPS) The MIC circuit pack has a PUPS that supplies four voltages: +5 V dc, +5.2 V dc, +12 V dc, and -12 V dc.



Bus connections CBus The MIC circuit pack is connected to the control bus (CBus). The CBus is the means of accessing all the circuit packs in the shelf.

SOH bus The MIC circuit pack is connected to each SONET overhead bus (SOH bus) in the shelf. In a shelf, there is one SOH bus for each OC-12 or OC-3 optical interface circuit pack. Each SOH bus links the OC-12 or OC-3 optical interface circuit pack to the following other circuit packs in the shelf: the processor circuit pack, the MIC circuit pack, and any auxiliary communications processor circuit packs. The SOH bus carries the SONET data communication channels (DCCs), the section data communication channel, and the line data communication channel.

The SOH bus also carries the express orderwire channel and the local orderwire channel.

Note: Other channels are available on the SOH bus, but those channels are not used by S/DMS TransportNode.

Equipping rules for the OC-12 or OC-3 shelf As shown in Figure 1-26, the MIC circuit pack is installed in slot 20 in the TBM shelf. Because the functionality of the MIC circuit pack is not service-affecting, the circuit pack is not duplicated.



Physical appearance of the maintenance interface circuit pack The MIC circuit pack is 29.2 cm (11.5 in.) high by 25.8 cm (10.15 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-25 shows the front view of the MIC circuit pack.

Figure 1-25Front view of the maintenance interface circuit pack

FW-1942 (RNS)

Fail

Init

Active

LckOut

TestRun

TestFail

Temp

LoopBk

CU

MaintIF

LED (color) Probable cause when on

LoopBk (Yellow)

CU (Yellow)

Temp (RED)

TestFail (Red)

TestRun (Yellow)

LckOut (Yellow)

Init (Yellow)

Active (Green)

Fail (Red)

Loopback active on a facility terminating on the shelf

Cooling unit shelf hardware problem (Note 1)

Internal shelf temperature greater than 70°C (158° F)

DS3 exerciser failure

DS3 exerciser active

High- or low-speed lockout active on TBM shelf

Proc initializing

MIC active (Note 2)

MIC failure

Note 1: This LED is active only in the TBM shelf that terminates the cooling unitinterface cable.

Note 2: This circuit pack should not be removed when this LED is ON(unless otherwise instructed in Volume 5, Alarm and Trouble ClearingProcedures, 323-1111-543).

NT

4K53



Figure 1-26Maintenance interface circuit pack installed in the OC-12 or OC-3 shelf

FW-1926.2-Vol1

OC-12 optical interface circuit pack (NT7E02) The OC-12 optical interface circuit pack is used in terminal, linear add-drop multiplexer (ADM), ring ADM, and regenerator applications. The circuit pack provides interface circuitry between the backplane STS bus and the OC-12 fiber link (see Figure 1-27).

Table 1-8 lists the OC-12 optical interface circuit pack uses.

Table 1-8OC-12 optical interface circuit pack applications

Application Units required Termination details

Terminal two the units terminate working and protection channels

Linear ADM four provide working and protection channels to two other network elements

Ring ADM two each unit handles both working and protection channels for an adjacent network element in the ring

Regenerator two (back-to-back) regenerate the optical signal between two terminals that are spaced further apart than the maximum distance

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

MIC

30 32 34 36 38 40 42 44 46 48 50 52 54 55

IN IN

OUT OUT

Maintenance InterfaceCard (NT4K53)



The OC-12 optical interface circuit pack generates an OC-12 optical signal from STS-1 electrical signals. The optical signal can be a 1310-nm (intra-office, intermediate or long reach) or 1550-nm (extended long reach) wavelength depending on the particular circuit pack version chosen. Each circuit pack processes a maximum of 12 STS-1 transmit and receive signals independently. The STS-1 signals are exchanged with tributary mapper or interface circuit packs by way of the backplane STS buses.

Figure 1-27Block diagram of the OC-12 optical interface circuit pack

FW-1966 (TBM)

Overhead

CBus

UnitFail

(Red)

Active(Green)

STS-12 OC-12

To/FromProcessor card

BackplaneInterface

(BIF)

STSAdd-Drop

Bus

STSPass-Through

Bus

CBusInterface

System ClockGenerator

SyncCircuit

TransportOverheadProcessor

(TOP)

TransmitElectro-Optic

Module

LOS(Yellow)Micro-

controller

STS-12

PUPS

+5 V dc

+12 V dc-48 V dc-4.5 V dc

-12 V dc

Legend:

CBus =PUPS =

VT =STS =


ReceiveElectro-Optic

Module

To/fromtributary mappers

and interfaces



Each OC-12 interface is protected on a 1+1 basis (one working, one protection). OC-12 optical interface circuit packs are available in four reaches, each with a different system gain:

Note: OC-12 networking interface circuit packs (NT7E02xx) cannot perform virtual tributary bandwidth management (VTM). VTM capability is provided by the OC-12 VTM circuit pack (NT7E05xx).

OC-12 interfaces with changeable optical connectorsUse OC-12 interface circuit packs with changeable optical connectors for the same functions as the OC-12 networking interfaces with fixed optical connectors (linear, ring and intra-office). The NT7E02PB/PC/PD circuit packs can be used for linear or ring functionality.

Circuit packs with changeable optical connectors use a universal adapter to permit use of ferrule (FC), straight (ST) or subscriber connectors (SC). (FC connectors are steel-threaded, SC connectors are plastic snap-in, and ST connectors are bayonet press-and-twist.) Connector types can be changed easily. Circuit packs with universal adapters reduce the number of spares needed and permit easier cleaning. Order circuit packs and optical connector kits separately.

Circuit packs with changeable optical connectors are compatible with Release 9 software, or later. The NT7E02Px circuit packs are compatible with Release 9 software, or later for SONET functionality but can only be programmed for SDH functionality with Release 13 software, or later. The NT7E02Nx circuit packs provide SONET/SDH functionality for OC-3/OC-12 linear and ring systems for Release 11 software. The NT7E02Nx circuit packs are compatible with Release 9 software or later.

See Table 1-9 for a list of circuit pack with changeable optical connectors and their functional equivalents.

Optical interface System gain (BER = 10–10

Intra-office (1310 nm) 5 dB

Intermediate reach (1310 nm) 19 dB

Long reach (1310 nm) 29 dB

Extended reach (1550 nm) 29.2 dB



Note 1: The following interface circuit packs are manufacturer discontinued: NT7E02XB, NT7E33CA, NT7E33DA, and NT7E33EA.

Note 2: OC-12 circuit packs that provide ring functionality (NT7E02Ex, NT7E02Fx, NT7E02Jx, and NT7E02Px) can replace the OC-12 linear networking interface circuit packs (NT7E02Kx, NT7E02Lx, and NT7E02Mx) in all OC-12 linear applications.

Table 1-9OC-12 interface circuit packs with changeable optical connectors and their functional equivalents

Circuit packs with changeable connectors

PEC Functionality Functional equivalent

OC-12 intra-office interface (1310 nm)

NT7E02PA Program for either SONET, SDH or SONET midspan meet functionality for Release 13

NT7E33CANT7E33DANT7E33EANT7E02NA

OC-12 IR interface (1310 nm) NT7E02PB Program for either SONET, SDH or SONET midspan meet functionality for Release 13

NT7E02FBNT7E02FCNT7E02FDNT7E02LBNT7E02LCNT7E02LDNT7E02XB

OC-12 LR interface (1310 nm) NT7E02PC Program for either SONET, SDH or SONET midspan meet functionality for Release 13

NT7E02EBNT7E02ECNT7E02EDNT7E02KBNT7E02KCNT7E02KD

OC-12 ELR interface (1550 nm)

NT7E02PD Program for either SONET, SDH or SONET midspan meet functionality for Release 13

NT7E02JBNT7E02JCNT7E02JDNT7E02MBNT7E02MCNT7E02MD

OC-12 SDH intra-office interface

NT7E02NA Use for SONET/SDH midspan meets

An interim solution for Release 11 but compatible with Release 13

NT7E33EANT7E02PA(for Release 13 and later)

OC-12 linear SDH IR interface NT7E02NB Use for SONET/SDH midspan meets

An interim solution for Release 11 but compatible with Release 13

NT7E02XBNT7E02PB(for Release 13 and later)



Note 3: Software releases display a question mark in the CLEI codes for circuit packs created after the release of software. For example, Release 11 and 10 software display question marks for the NT7E02Nx/Px circuit packs. The question marks appear in the shelf inventory screen of the network element user interface (NEUI).

Note 4: Use OC-12 networking interfaces (NT7E02Px) for ADM functionality in a linear ADM, or in a NWK ring ADM (ring circuit packs only). Do not use NT7E02Px/Nx circuit packs in VTM ring ADM network elements. These network elements use NT7E05xx network interface circuit packs.

OC-12 intra-office and STS-12 circuit packsThe OC-12 intra-office optical carrier circuit pack (NT7E02PA) provides the same functionality as the STS-12 electrical carrier circuit packs, for software releases 9 and later. The intra-office circuit pack uses fiber optic cables instead of the coaxial cables required for the STS-12 circuit pack. Connectors for the intra-office circuit pack are interchangeable and must be ordered separately.

Note: STS-12 circuit packs NT7E33CA, NT7E33DA and NT7E33EA are manufacturer discontinued.

OC-12 SONET/SDH circuit packsFor Release 13, the OC-12 interface circuit packs (NT7E02Px) can be programmed for SONET or SDH functionality. For Release 11, the OC-12 SDH intra-office interface circuit pack (NT7E02NA) provides the same functionality as the STS-12 SONET/SDH interface circuit pack (NT7E33EA). The OC-12 linear SDH IR interface circuit pack (NT7E02NB) replaces the OC-12 IR 1310 nm SONET/SDH interface circuit pack (NT7E02XB). Both the NT7E02NA and the NT7E02NB are compatible with Release 13.

Use SONET/SDH midspan meet circuit packs NT7E02NA and NT7E02NB for SONET/SDH midspan meets only. Although the midspan meet occurs at the OC-3 rate, the SS Bits within the H1 Byte that determine SDH or SONET functionality are controlled and provisioned by the OC-12 circuit packs. These circuit packs cannot be used in OC-48 tributary applications. The circuit packs require that you provision the NE database by performing the commissioning procedure in Provisioning and Operations Procedures, 323-1111-310.

Optical connector kitsOptical connectors for the NT7E02Px and NT7E02Nx optical interface circuit packs are not part of the circuit pack. Order connector kits separately. Three connector kits are available depending on the type of connector required (FC, ST or SC). For more information, see Ordering Information, 323-1111-151.



Terminal, linear ADM, and ring ADM applications Transmit directionThe serial STS-1 signals from the add-drop and pass-through buses are received from the backplane. Two half-filled STS-1s from adjacent DS1 mappers (odd and even slots) are merged on the backplane interface of the OC-12 circuit pack to form a full STS-1. The transport overhead processor (TOP) inserts the line overhead (LOH) and section overhead (SOH), multiplexes and scrambles the STS-1 signals into a serial 622-Mbit/s STS-12 signal. The STS-12 electrical signal is then converted into an OC-12 optical signal by the electro-optic transmitter module and transmitted on the fiber link.

Receive direction The OC-12 optical signal from the fiber link is converted into a 622-Mbit/s STS-12 electrical signal by the electro-optic receiver module. The transport overhead processor (TOP) circuit demultiplexes the serial STS-12 signal and searches for the STS-12 frame word. The transport overhead (LOH and SOH) is extracted by the TOP circuit where it is reframed and descrambled. The signal is then routed to the synchronization circuit where the STS-level pointer processing is performed on each STS-1 to synchronize the payload to the system clock and frame. The STS-12 signal is then sent to the backplane interface where it is converted into 12 serial STS-1s to be routed to the add-drop and Pass-Through buses.

Timing reference signals are also derived from the received optical signal and provided to the system clock generator, which produces timing signals to the shelf timing clock buses. These signals can be used as reference inputs to the ESI units.

STS-1 channel usageIn terminal and linear ADM configurations, all 12 STS-1 channels carry working or protection traffic. In ring ADM configurations, STS-1 channels 1 to 6 carry working traffic, and STS-1 channels 7 to 12 carry protection traffic.

In the optical interface circuit packs used for ring ADM applications, only the six working STS-1 channels are sent to the backplane interface during normal operation. However, when high speed protection is active, all 12 STS-1 channels are provided to the backplane.

Regenerator application The receive portion of the circuit pack is looped directly to the transmit portion of the circuit pack. This allows the line overhead to be passed through while the section overhead is extracted, updated, and inserted into the outgoing STS-12. This signal goes through electro-optic conversion in the distributed feedback laser module. The OC-12 regenerator also generates the line alarm indication signal. Refer to Figure 1-28 for the block diagram. The OC-12



regenerator interface provides a unidirectional optical link. Therefore to regenerate one OC-12 signal, two OC-12 circuit packs are required at the regenerator site.

Figure 1-28Block diagram of the OC-12 regenerator

FW-0091 (OC12))

Control bus interface (CBus) Control and status monitoring for the OC-12 optical interface circuit pack is provided by the CBus interface circuit that provides communication with the shelf processor through the control bus. A local processor feeds information to the CBus interface circuit and is responsible for the control and monitoring of the OC-12 optical interface circuit pack real time events (for example, 1+1 optical protection arbitration) that cannot be dealt with by the processor circuit pack. The Unit Fail LED (red) located on the faceplate of the circuit pack is also controlled by the CBus interface circuit.

RegeneratorInterface

DFBLaser

ModuleOC-12

Active(Green)

Fail(Red)

CBusInterface

To/fromProcessor circuit pack

+5 V dc-4.5 V dc+12 V dc-12 V dc

-5.2 V dc

PUPS-48 V dcDistributed FeedbackControl BusPoint-of-Use Power Supply

DFB =CBus =PUPS =

Legend:

OC-12OC-12

ReceiveI/F

STS-12 STS-12

LOS(Yellow)



Point-of-use power supply (PUPS) The OC-12 optical interface circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated dc voltage levels required by the local circuitry.

Equipping rules for the OC-12 shelf Table 1-10 shows the equipping rules for the OC-12 shelf.

Refer to System Description, 323-1111-100, for more information on shelf configurations.

Table 1-10Equipping rules for the OC-12 shelf

Configuration circuit pack designation Slots

Terminal G1 / G2 9 / 10

Linear ADM G1S / G2S 5 / 7

Ring ADM G1S / G1 5 / 9

Regenerator 5 / 9

Note 1: Slots 9 and 10 are the primary transport slots for G1 and G2.

Note 2: Slots 5 and 7 are the secondary transport slots for G1S and G2S.



Alarm LED definitions Table 1-11 lists the names of the OC-12 optical interface circuit pack LEDs, the possible cause for their activation, and the manner in which they are controlled (hardware or software).

Note: When this interface circuit pack is installed in a protected transport configuration, if the facility at one of the pair of interface circuit packs is placed out-of-service, the LOS LED on both circuit packs is disabled and cannot indicate a loss of signal should one occur.

Table 1-11OC-12 optical interface circuit pack LEDs


Fail Alarm points

• component fail

• receive parity fail

• transmit laser fail

Software

Active Active unit Software in regenerator applications, and hardware in all other applications

LOS Optical signal fail Hardware



Figure 1-29 shows the faceplate layout of the OC-12 optical interface circuit pack.

Figure 1-29OC-12 optical interface circuit pack faceplate layout

FW-0121 (OC-12)

Fail

Active

LOS

IN

OUT LOS LED (Yellow)Indicates a loss of signal or loss of frame.

Active LED (Green)Indicates the unit is receiving traffic. The circuit pack should not beremoved while this LED is lit.

Fail LED (Red)Indicates a circuit pack failure or the detection of a backplane parity error.

OC-12LR1310NetIF (ST)



Ring loopback circuit pack (NT7E35)The OC-12 GR-1230 BLSR system is comprised of tributary, protection, and optics equipment. The ring loopback circuit pack, in conjunction with the overhead bridge circuit pack, provides protection switching for the optics equipment.

The ring loopback circuit pack provides the functionality required to perform a ring protection switch. This involves switching the working STS-1 channels 1-6, received from the optical interface pack, onto the protection STS-1 channels in the other direction (loopback) and returning them to the same optical interface pack. The ring loopback circuit packs do not carry traffic under normal operating conditions; only under fault conditions.

A functional block diagram of the ring loopback circuit pack is given in Figure 1-30. The circuit pack is based on the OC-12 optical interface circuit pack but with all the circuitry required to support the optical interface removed. The loopback is performed by connecting the STS-1 channels received from the backplane interface circuit back into this circuit, through the synchronization circuit. The synchronization circuit is required to align the loopback traffic with the backplane timing.

The transport control subsystem (TCS) controls communications between the OC-12 ring loopback circuit pack and its adjacent OC-12 optical interface circuit pack, as well as between the two loopback circuit packs.

The overhead bus interface circuit (OBIC) provides the ring loopback circuit pack with direct access to the K1 and K2 APS bytes received by the opposite line interface through the overhead bus on the backplane.

The ring loopback circuit pack located in slot 10 is responsible for generating system clocks. These clocks are derived from a 51.84 MHz timing source received from the optical interface circuit pack in slot 9 or from the ESI unit, and produced by the system clock generator block. These functions are disabled in the loopback circuit pack located in slot 7. If the optical interface circuit pack in slot 9 cannot provide system clocks, the system clock is provided by the ring loopback circuit pack in slot 10.

The loopback card contains firmware that can be downloaded from the OPC.

Control bus interface (CBus) Control and status monitoring for the ring loopback circuit pack is provided by the CBus interface circuit that provides communication with the shelf processor through the control bus. A local processor feeds information to the CBus interface circuit and is responsible for the control and monitoring of the ring loopback circuit pack real time events that cannot be dealt with by the processor circuit pack. The Unit Fail LED (red) located on the faceplate of the circuit pack is also controlled by the CBus interface circuit.



Figure 1-30Block diagram of the ring loopback circuit pack

FW-2446

CBus

UnitFail

(Red)

Active(Green)

To/FromProcessor card

BackplaneInterface

(BIF)

STSAdd-Drop

Bus

STSPass-Through

Bus

CBusInterface


SyncCircuit

TransportControl

Subsystem

STS-12

PUPS

+5 V dc

+12 V dc-48 V dc-4.5 V dc

-12 V dc

Legend:

CBus =PUPS =

VT =STS =


To/fromtributary mappers

and interfaces

To/fromOC-12 Optical

Interfacein other group

K-BytesInterface

OverheadBus

K-Bytes received fromOC-12 Optical Interface

in other group

Serial LinkTo OC-12 Optical I/Fin same group and

other Ring Loopback card



Point-of-use power supply (PUPS) The ring loopback circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated dc voltage levels required by the local circuitry.

Equipping rules for the OC-12 shelf

The ring loopback circuit packs (LpbkG1S and LpbkG1) are installed in slots 7 and 10, respectively, of the OC-12 TBM shelf.


CAUTIONRisk of loss of protection switchingFailure or removal of equipment that facilitates protection switching, such as ring loopback circuit packs, results in the inability to provide protection switching around the ring until the failed or removed unit is replaced.



Figure 1-31 shows the faceplate layout of the ring loopback circuit pack.

Figure 1-31Ring loopback circuit pack faceplate layout

FW-0121(BLSR)

Fail

Active

Active LED (Green)Indicates that this circuit pack is in-service. The circuit pack shouldnot be removed when this LED is lit.

Fail LED (Red)Indicates circuit pack failure.

OC-12RingLoopbk



Overhead bridge circuit pack (NT7E36)The OC-12 NWK ring (or BLSR) is comprised of tributary, protection and optics equipment. The overhead bridge circuit pack, in conjunction with the ring loopback circuit pack, facilitates protection switching for the optics equipment.

The overhead bridge circuit pack provides additional control links between the ring transport circuit packs by bridging tracks on the backplane. It provides the connectivity to support the following two functions:

• a serial communications link between the two ring loopback circuit packs

• bridging of incoming K-Bytes on the OC-12 optics circuit pack to the opposite ring loopback circuit pack

Equipping rules for the OC-12 shelf

The overhead bridge circuit pack is installed in slot 22 of the OC-12 TBM shelf.


CAUTIONRisk of loss of protection switchingFailure or removal of equipment that facilitates protection switching, such as ring loopback circuit packs, results in the inability to provide protection switching around the ring until the failed or removed unit is replaced.



Figure 1-32 shows the faceplate layout of the overhead bridge circuit pack. The overhead bridge circuit pack contains no active components or alarm LEDs.

Figure 1-32Overhead bridge circuit pack faceplate layout

FW-2447

OC-12RingOverhdBridge



OC-3 optical interface circuit pack (NT7E01) The OC-3 optical interface circuit pack provides interface circuitry between the backplane STS bus and the OC-3 fiber link (see Figure 1-33). When used as the transport interface circuit pack in an OC-3 terminal or linear ADM shelf, the circuit pack processes up to three STS-1 transmit and receive signals composed of DS1, DS3, or STS-1 tributary signals. When used as an optical tributary interface in an OC-12 terminal, linear ADM, or ring ADM shelf, the three STS-1 signals or single STS-3c concatenated signal is exchanged with the OC-12 transport interface circuit pack. Optical tributary circuit packs are protected in a 1+1 nonrevertive protection scheme.

When an OC-3 circuit pack is used as a transport interface circuit pack, the NT7E01Cx or NT7E01Dx Networking Interface modules are required for linear ADM applications. When an OC-3 circuit pack is used as a tributary, the NT7E01Cx or NT7E01Dx networking interface circuit packs are required for OC-12 terminal, linear ADM, and ring ADM applications. For more information, see Ordering Information, 323-1111-151.

NT7E01GA and NT7E01GB optical interface circuit packsOC-3 interfaces with changeable optical connectors (NT7E01GA and NT7E01GB) provide the same functionality as OC-3 networking interfaces with fixed optical connectors (NT7E01Dx and NT7E01Cx respectively). OC-3 interface circuit packs NT7E01GA and NT7E01GB are compatible with Release 9 software, or later.

Circuit packs with changeable optical connectors use a universal adapter to permit use of ferrule (FC), straight (ST) or subscriber connectors (SC). (FC connectors are steel-threaded, SC connectors are plastic snap-in, and ST connectors are bayonet press-and-twist.) Connector types can be changed easily. Circuit packs with universal adapters reduce the number of spares needed and permit easier cleaning.

Optical connector kitsOptical connectors for the NT7E01GA and NT7E01GB optical interface circuit packs are not part of the circuit pack. Order connector kits separately. Three connector kits are available depending on the type of connector required (FC, ST or SC). For more information, see Ordering Information, 323-1111-151.

Transmit direction In the transport interface application, the serial STS-1 signals from the add-drop and pass-through buses are received from the backplane. Two half-filled STS-1s from adjacent DS1 mappers (odd and even slots) are merged on the backplane interface of the OC-3 circuit pack to form a full STS-1.



In the optical tributary interface application, the three STS-1 channels received from the backplane are signals received by the OC-12 transport interface circuit pack.

The transport overhead processor (TOP) inserts the line overhead (LOH) and section overhead (SOH), multiplexes and scrambles the STS-1 signals into a serial 155.5-Mbit/s STS-3 signal. The STS-3 electrical signal is then converted into an OC-3 optical signal by the electro-optic transmitter module and transmitted on the fiber link.

Receive direction The OC-3 optical signal from the fiber link is converted into a 155.5-Mb/s STS-3 electrical signal by the electro-optic receiver module. The transport overhead processor (TOP) circuit demultiplexes the serial STS-3 signal and searches for the STS-3 frame word. The transport overhead (LOH and SOH) is extracted by the TOP circuit where it is reframed and descrambled. The signal is then routed to the synchronization circuit where the STS-level pointer processing is performed on each STS-1 to synchronize the payload to the system clock and frame. The STS-3 signal is then sent to the backplane interface where it is converted into three serial STS-1s to be routed to the add-drop and pass-through buses.

Control bus interface (CBus) Control and status monitoring for the OC-3 optical interface circuit pack is provided by the CBus interface circuit that provides communication with the shelf processor through the control bus. A local processor feeds information to the CBus interface circuit and is responsible for the control and monitoring of the OC-3 optical interface circuit pack real time events (for example, 1+1 optical protection arbitration) that cannot be dealt with by the processor circuit pack. The Unit Fail LED (red) located on the faceplate of the circuit pack is also controlled by the CBus interface circuit.

Point-of-use power supply (PUPS) The OC-3 optical interface circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry.

Equipping rules for the OC-3 or OC-12 shelf When used as the transport interface circuit pack in an OC-3 shelf, the primary OC-3 optical interface circuit packs (G1 and G2) are installed in slots 9 and 10 (for terminal and ADM shelves). The secondary OC-3 optical interface circuit packs (G1S and G2S) are installed in slots 5 and 7 (for ADM shelves only). Each pair of circuit pack groups (G1/ G2 and G1S/G2S) operate on a 1+1 nonrevertive protection scheme.



When used as an optical tributary interface in an OC-12 terminal or ADM shelf, the OC-3 optical interface circuit packs can be installed in slots 1 and 3 (working and protection pair G3 and G4), slots 11 and 13 (working and protection pair G5 and G6), and slots 15 and 17 (working and protection pair G7 and G8). In an OC-12 terminal shelf and VTM rings, the OC-3 optical interface circuit packs can also be installed in slots 5 and 7 (working and protection pair G1S and G2S). Each pair of circuit pack groups operate on a 1+1 nonrevertive protection scheme.

The OC-3 tributaries can be mixed with DS1, DS3, and STS-1 tributaries on the same shelf.

Refer to System Description, 323-1111-100, for more information on the shelf configurations.

Alarm LED definitions Table 1-12 lists the names of the OC-3 optical interface circuit pack LEDs, the possible cause for their activation, and the manner in which they are controlled (hardware or software).


Table 1-12OC-3 optical interface circuit pack LEDs


Unit Fail Alarm Points

• component fail


• transmit laser fail

Software

Active Active unit Hardware

LOS Optical signal fail Hardware



Figure 1-33Block diagram of the OC-3 optical interface circuit pack

FW-1966 (OC3 R8)

Overhead

CBus

UnitFail(red)

Active(green)

STS-3 OC-3


Backplaneinterface

(BIF)

STSadd-drop

Bus

STSpass-through

Bus

CBusinterface

System clockgenerator

Synccircuit


(TOP)

Transmitelectro-optic

module

LOS(yellow)Micro-

controller

STS-3

PUPS

+5 V dc

+12 V dc-48 V dc-4.5 V dc

-12 V dc

Legend:

CBus =PUPS =

VT =STS =

Control BusPoint-of-use Power SupplyVirtual TributarySynchronous Transport Signal

Receiveelectro-optic

module

To/fromDS1/VT mappers,

DS3 mappers,and STS-1 interfaces

(when used as a transport IF)OC-12/STS-12 circuit packs(when used as a tributary IF)



Figure 1-34 shows the faceplate layout of the OC-3 optical interface circuit pack.

Figure 1-34OC-3 optical interface circuit pack faceplate layout

FW-0121 (OC-3)

Fail

Active

LOS

IN

OUT LOS LED (Yellow)Indicates a failure or loss of signal. The LED is hardware controlled.

Active LED (Green)Indicates the unit is receiving traffic. The circuit pack should not beremoved while this LED is lit. The LED is hardware controlled.

Fail LED (Red)Indicates a circuit pack failure or the detection of a backplane parity error.The LED is software controlled.

OC-3IR1310(ST)



STS-12 electrical interface (NT7E33)The STS-12 electrical interface circuit pack provides interface circuitry between the ADM and terminal shelves in the 336-DS1 TBM application, or between collocated ADM shelves at a site where additional add/drop capacity is required. The STS-12 electrical interface generates an STS-12 electrical signal from STS-1 electrical signals. Each circuit pack processes a maximum of 12 STS-1 transmit and receive signals independently. The STS-1 signals are transmitted and received by way of the backplane STS buses.

Note: The STS-12 circuit packs are manufacturer discontinued. For their replacement circuit packs, see Table 1-9 on page 1-48.

Transmit directionThe serial STS-1 signals from the add-drop and Pass-Through buses are received from the backplane. The backplane interface circuit combines partially full STS-1s, and selects 12 STS-1s to be multiplexed. The transport overhead processor (TOP) inserts the line and section overhead (LOH and SOH), and multiplexes the STS-1 signals into a serial 622-Mb/s STS-12 signal. A line driver then interfaces this signal to the other shelf. See Figure 1-35.

Receive directionThe serial STS-12 electrical signal from the other shelf is first retimed in a clock recovery module and then the TOP circuit demultiplexes the serial STS-12 signal and searches for the STS-12 frame word. The transport overhead (LOH and SOH) is extracted by the TOP circuit where reframing is performed. The signal is then routed to the sync circuit where the STS level pointer processing is performed on each STS-1 to synchronize the payload with the system clock and frame. Then, the STS-12 signal is sent to the backplane interface where it is converted into 12 serial STS-1s to be routed to the backplane add-drop and Pass-Through buses.

Timing reference signals are also derived from the received electrical signal and provided to the system clock generator, which produces timing signals to the shelf timing clock buses. These signals can be used as reference inputs to the ESI units.

STS-1 channel usageIn terminal and linear ADM configurations, all 12 STS-1 channels carry working or protection traffic. In ring ADM configurations, STS-1 channels 1 through 6 carry working traffic, and STS-1 channels 7 through 12 carry protection traffic.

In the electrical interface circuit packs used for ring ADM applications, only the six working STS-1 channels are sent to the backplane interface, during normal operation. However, when high speed protection is active, all 12 STS-1 channels are provided to the backplane.



Control Bus (CBus) interfaceControl and status monitoring for the STS-12 electrical interface is provided by the CBus interface circuit that provides communication with the shelf processor through the control bus. A local processor, feeding information to the CBus interface circuit, is responsible for control and monitoring of the STS-12 electrical interface real time events (for example, 1+1 protection arbitration). The Unit Fail LED (red), located on the faceplate of the circuit pack, is also controlled by the CBus interface circuit.

Point-of-use power supply (PUPS)The STS-12 electrical interface is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated dc voltage levels required for the local circuitry.

Equipping rules for the OC-12 shelfSTS-12 electrical interface circuit packs are installed in slots 9 and 10 (G1 and G2) when used in a TBM terminal shelf (one working and one protection), in slots 5 and 7 (G1S and G2S) when installed in an ADM shelf (one working and one protection), and in slots 5 and 9 (G1S and G1) when used in a ring ADM shelf. Refer to System Applications Description, 323-1111-150, for more information.

Alarm LED definitionsThe following table provides a list of the STS-12 electrical interface LEDs and is presented in three columns: LED name, possible cause, and controlled by (hardware or software). Refer to Figure 1-36 for the STS-12 electrical interface faceplate layout showing the location of the LEDs.



Unit Fail

Active

LOS

Alarm points

• component fail


Active unit

Electrical signal fail

Software

Hardware

Hardware



Figure 1-35Block diagram of the STS-12 electrical interface circuit pack

FW-0443 (TBM)

Overhead

CBus

UnitFail

(Red)

Active(Green)

STS-12 STS-12

(To/FromDS3/STS Mappers

and DS1/VT Mappers)

To/FromProcessor Card

BackplaneInterface

(BIF)

STSAdd-Drop

Bus

STSPass-Through

Bus

CBusInterface


SyncCircuit


(TOP)

ElectricalInterface

LOS(Yellow)Protection

Processor

STS-12

PUPS

+5 V dc

+12 V dc-48 V dc-4.5 V dc

-12 V dc

Legend:

CBus =PUPS =

STS =


ElectricalInterface



Figure 1-36STS-12 electrical interface circuit pack — faceplate layout

FW-0121 (sts12 R11)

Fail

Active

LOS

STS-12In

STS-12Out

IntershelfSTS-12NetIF

NT

7E33

LOS LED (yellow)Indicates a failure or loss of signal. The LED is firmware controlled.

Active LED (green)Indicates the unit is receiving traffic. The circuit pack should not beremoved while this LED is lit. The LED is firmware controlled.




OC-12 VTM circuit pack (NT7E05) The OC-12 VTM circuit pack is used in the VTM ring ADM. For this application, two units are required. One unit handles the working and protection channels traveling in the east-to-west direction, and the other unit handles the working and protection channels traveling in the west-to-east direction.

The OC-12 VTM circuit pack can be equipped with the following optical connectors:

• ferrule (FC)

• straight (ST)

• subscriber (SC)

The OC-12 VTM circuit pack provides

• interface to the OC-12 signal

• bandwidth management at the STS-1 level and at the VT1.5 level

• timing to maintain the synchronization of the network element

Interface to the OC-12 signal The OC-12 VTM circuit pack generates an OC-12 signal from STS-1 electrical signals. The optical signal is a 1310-nm (intermediate reach) wavelength. Each circuit pack processes a maximum of 12 STS-1 transmit and receive signals independently. The STS-1 signals are exchanged with tributary circuit packs by way of the backplane add and drop buses.

Bandwidth managementThe OC-12 VTM circuit pack can perform bandwidth management at the STS-1 level and at the VT1.5 level. To perform bandwidth management, the circuit pack must perform both synchronization and switching.

The synchronization function aligns the STS-1 and VT signals so that the ANSI Switch ASIC can perform time slot management. Alignment enables the ANSI Switch ASIC in the circuit pack to locate the constituent STS-1 or VT time slots of the signals received at its input ports. Switching at the STS level requires STS-level synchronization; switching at the VT level requires VT-level synchronization.

Synchronization means that the received SONET signal must be aligned to the system clock. STS-level synchronization is achieved by performing STS pointer justification on the STS synchronous payload envelope (SPE) extracted from the received SONET signal. VT-level synchronization aligns the VT frames within an STS-1 to the 2 kHz system clock. This alignment requires VT pointer processing on each VT1.5.



To perform switching, the OC-12 VTM circuit pack contains a central STS-1 and VT cross-connect located in the ANSI Switch ASIC. The ANSI Switch ASIC has three bidirectional STS-12 ports and is fully nonblocking. Any VT1.5 at any add/drop port can be connected to any VT1.5 at any line port. The three ports are:

• the add-drop port, dedicated to the add-drop bus

• the line port, dedicated to the unit STS-12 line interface

• the Pass-Through port, which interfaces to

— the R-link, if the network element is a VTM ring ADM

— the Pass-Through bus in the shelf backplane, if the network element is a linear ADM (future application)

Note: VT-mapped STS-1s that are not VT-synchronized can be cross-connected at the STS-1 level but not at the VT level.

TimingWhen equipped in the primary transport slots, the OC-12 VTM circuit packs are responsible for generating shelf timing. Each OC-12 VTM circuit pack has a system clock generator that generates a 52 MHz clock, a 38 MHz clock, and a 2 kHz clock. The clocks are distributed to the tributary interfaces in the TBM shelf.

The master OC-12 VTM circuit pack locks to the selected timing reference for the shelf, and the slave unit locks to a timing reference provided by the master unit. The master OC-12 VTM circuit pack can lock its system clock generator to any of the following timing references:

• a 51.84 MHz timing reference supplied by an ESI card in the shelf

• timing signals in the received OC-12 signal

• a received OC-12 or STS-12 signal from the secondary transport slots

In the event that the timing reference is lost, the OC-12 VTM circuit pack provides a holdover capability that can maintain the frequency to within 4.6 ppm for a period of 24 hours (but ESI will overrule if equipped). The OC-12 VTM circuit pack can free-run with a frequency accuracy of ±20 ppm.

The OC-12 VTM circuit packs provide access to the synchronization-status messages contained in bits five to eight of the S1 byte of the SONET line overhead. In an VTM ring, each network element encodes the synchronization status message in the outgoing SONET signal. The message informs the adjacent network element of the quality level of the timing of the SONET signal. If a network element must choose a new timing source, because the active timing source has degraded or has been lost, then it chooses the



highest-quality timing source available. For detailed information on synchronization-status messages, see the chapter on network synchronization in System Description, 323-1111-100.

Figure 1-37Block diagram of the OC-12 VTM circuit pack

OS.0449

Ove

rhea

dP

roce

ssor

Ele

ctro

-opt

icsu

b-sy

stem

OC-12

Add bus

ANSISwitch

R-link

Drop bus

R-link

Transport Control System

Microprocessor EEPROM

RAMMBUS

synch.

Systemclockgenerator

52MHz

38MHz

2KHz

Pass-throughbus

Pass-throughbus

OC-12

VTSync

DropAddbackplane(DAB)

MicroprocessorAccess ASIC

Point-of-usepowersupply(PUPS)

18

24

12

18

12

12VTSync

VTSync

MuxDemux

MuxDemux

MuxDemux

MuxDemux

MuxDemux

MuxDemux

MuxDemux

MuxDemux

VTSync



VTM ring ADM applicationFigure 1-37 shows the transmit-direction and receive-direction signal flow in the OC-12 VTM circuit pack.

Transmit direction signal flow—going into the fiberThe DropAdd (DAB) ASIC can receive 12 serial STS-1 signals. In a VTM ring ADM, the DAB receives the 12 STS-1s from the R-link. The DAB multiplexes the 12 received STS-1s into an STS-12 signal, and routes that signal to the Pass-Through port of the ANSI Switch ASIC.

From the ANSI Switch ASIC, the STS-12 goes to the VT Sync ASICs, and then to the Overhead Processor ASIC. Each VT Sync ASIC performs VT pointer processing for a single STS-3 signal. The Overhead Processor ASIC adds the SONET section and line overhead and scrambles the result. From the Overhead Processor ASIC, the STS-12 goes to the electro-optic subsystem, where it is multiplexed to the 622 Mb/s line rate.

Receive direction signal flow—coming out of the fiberThe OC-12 signal from the fiber link is converted into a 622-Mb/s STS-12 electrical signal by the electro-optic subsystem. The STS-12 then goes to the Overhead Processor. The Overhead Processor frames and descrambles the STS-12 signal, extracts the SONET line overhead (LOH) and section overhead (SOH), and performs STS pointer processing to align the signal with local system timing. From the Overhead Processor, the STS-12 goes to the VT Sync ASICs, which provide VT pointer processing to align all the VTs with a local frame reference. Each VT Sync ASIC performs VT pointer processing for a single STS-3 signal. From the VT Sync ASICs, the STS-12 goes to the line port of the ANSI Switch ASIC.

From the ANSI Switch ASIC, two STS-12 signals go to the DropAdd backplane (DAB). One comes from the add-drop port, the other, from the Pass-Through port. The DAB takes the STS-12 signal from the add-drop port and demultiplexes it into 12 serial STS-1s, which are routed to tributary cards by way of the backplane drop bus. In a ring ADM, the DAB takes the STS-12 signal from the Pass-Through port and routes it to the adjacent OC-12 VTM circuit pack by way of the R-link.

The OC-12 VTM circuit pack can derive its timing reference signals from the received optical signal. The active OC-12 VTM circuit pack can lock its Timing Reference (T-REX2) to these timing reference signals. The system clock generator in the active OC-12 VTM circuit pack provides the 52 MHz clock, the 38 MHz clock, and the 2 kHz clock.

STS-1 channel usageIn the VTM ring ADM configuration, STS-1 channels 1 to 6 carry working traffic, and STS-1 channels 7 to 12 carry protection traffic.



Bus interfaceThe OC-12 VTM circuit pack interfaces to the processor card by way of the maintenance bus (MBUS), which is a subset of the control bus (CBUS). The processor card interfaces to the Transport Control Subsystem (TCS) of the OC-12 VTM circuit pack, and that subsystem interfaces to the hardware on the circuit pack.

Transport Control SubsystemThe Transport Control Subsystem is shown in Figure 1-37. The main parts of the subsystem are

• the microcontroller

• the Microprocessor Access ASIC, which provides the interface between the microcontroller and the processor card

• electrically erasable programmable read-only memory (EEPROM), for nonvolatile storage of bootload firmware and circuit-pack identification data (product engineering code and vintage)

• random access memory (RAM) for use by the microcontroller

Point-of-use power supply (PUPS)The OC-12 VT manager circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated dc voltage levels required by the local circuitry.

Equipping rules for the OC-12 shelf In a VTM ring ADM, the OC-12 VTM circuit packs (G1 and G2) are installed in slots 9 and 10.

For more information on the VTM ring ADM configuration, refer to System Description, 323-1111-100.

Alarm LED definitions Table 1-13 lists the names of the OC-12 VTM circuit pack LEDs, and the possible causes for the activation of each LED.

Table 1-13OC-12 VTM circuit pack LEDs

LED name Possible cause

Fail Circuit-pack fail condition

Active Active unit

LOS Loss of signal (LOS) orloss of frame (LOF) or the receiver cannot extract the clock



Figure 1-38 shows the faceplate layout of the OC-12 VTM circuit pack.

Figure 1-38OC-12 VTM circuit pack faceplate layout

OS.0219

Fail

Active

LOS

IN

OUT LOS LED (Yellow)Indicates a loss of signal or frame LOS/LOF if the label changed.

Active LED (Green)Indicates the unit is carrying traffic. The circuit pack should not beremoved when this LED is lit.

Fail LED (Red)Indicates a circuit pack failure.

OC-12IR1310VTMI/F



Operations controller (NT7E24)The operations controller (OPC) provides centralized data management and software management. It also provides an operations system (OS) interface, a 525-Mbyte hard disk, and an integrated tape drive (see Figure 1-39). For additional general information on the OPC, refer to System Description, 323-1111-100, and to Software Description, 323-1111-101. For a description of the OPC character-mode and graphical user interfaces, and the OPC tools, refer to User Interfaces Description, 323-1111-301.

Solid state OPC (NT7E24EA or NT7E24FA)In the NT7E24EA solid-state OPC, the hard disk drive has been replaced by a 640 Mbyte solid state version. In the NT7E24FA solid-state OPC, in addition to the solid state hard disk drive, the mechanical tape drive has been replaced by a solid state cartridge drive.

Centralized data management The operations controller manages data collection, data storage, and data consolidation by means of the CNet local area network, the Proc, and the SONET overhead. This allows for single-ended maintenance, remote inventory, alarm correlation, and global provisioning.

Software management Remote software delivery from Nortel Networks can be accomplished by way of pre-loaded hardware, a tape, or an electronic transfer. The OPC also provides software recovery, software upgrade, network element database backup and restore, and superset load/software options.

OPC user interface OAM&P operations can be performed by OPC screens or network element screens. The OPC user interface is window-based and supports VT100 terminals.

Point-of-use power supply (PUPS) The OC-12 OPC is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry.



Alarm LED definitions Table 1-14 lists the names of the OPC circuit pack LEDs, the possible cause for their activation, and whether they are controlled by hardware or software.

Table 1-14Names of OPC circuit pack LEDs


E LAN Fail OPC cannot communicate through the Ethernet port Software

CNET Fail OPC cannot communicate through the CNET port Software

Active OPC provisioned in-service Software

Unit Fail Circuit pack failure Software/Hardware



Figure 1-39Block diagram of the operations controller

FW-0316

Clock

CPU

DRAMBootROM

CPU memory

Real timeclock

SCSIhard diskcontroller

MBusinterface

I/O driver/receivercontrol

CNetinterface

SCSI hard disk325 or 525 Mbytes

PUPS+/-5 V

+/-12 V

Daughter board

Legend:CNet =CPU =

DRAM =PUPS =ROM =SCSI =

Control networkCentral processor unitDynamic random access memoryPoint-of-use power supplyRead-only memorySmall computer system interface

Daughter board

MagneticTape

SCSI backup tape drive

Optional tape drive



Figure 1-40Block diagram of the NT7E24EA/FA OPC equipped with a cartridge drive

OS.0201

Clock

CPU

DRAMBootROM

CPU memory

Real timeclock

SCSIhard diskcontroller

MBusinterface

Ethernetinterface

I/O driver/receivercontrol

CNetinterface

MBus

Ethernetport

CNet

SCSI hard disk

PUPS+/-5 V

+/-12 V

Daughter board

Legend:CNet =CPU =

DRAM =PUPS =ROM =SCSI =

Control networkCentral processor unitDynamic random access memoryPoint-of-use power supplyRead-only memorySmall computer system interface

Daughter board

Cartridge

SCSI backupcartridge drive

Optional cartridge drive



Figure 1-41 shows the faceplate layout of the OPC module.

Figure 1-41Operations controller faceplate layout (door open)

FW-0317 (SDH)

CNet Fail

FailActive

E LAN Fail

802.3 Ethernet10BASE-T Portbehind door

Internal TapeDrive behind door(Optional)

LED (Amber)Indicates the tape is being accessed. Do not remove thetape while this LED is lit.

LED (Green)Indicates that a tape is detected in the tape drive.

(FW-0317 (N)

Tape eject buttonbehind door

Door (open)

OPCModule

LED name (color) Probable cause when on

E Lan Fail (Yellow)

CNet Fail (Yellow)

Active (Green)

Unit Fail (Red)

Hard Disk (Green)

Ethernet port controller failure

CNet port controller failure

Unit active (do not remove while thisLED is lit)

Circuit pack failure

Illuminates intermittently as a part of normal functioning. Illuminatescontinuously when performing aread/write software function.

NT

7E24

CAUTION

SHOCK & VIBRATION SENSITIVE

Removing OPC priorto shut-down, will corrupt

the operating system.

!

Do not remove OPC whenActive or Hard Disk LED

is lit.

Hard Disk

CAUTION!

CAUTION




!



Figure 1-42 shows the faceplate layout of the OPC module.

Figure 1-42Operations controller NT7E24EA/FA faceplate layout (door open)

OS.0202

CNet Fail

FailActive

E LAN Fail

802.3 Ethernet10BASE-T Portbehind door

Internal Cartridge Drivebehind door (Optional)

(FW-0317 (OC48 R13)

Cartridge eject buttonbehind door

Door (open)

OPCModule

NT

7E24

CAUTION




!

Do not remove OPC whenActive or Hard Disk LED

is lit.

Hard Disk

CAUTION!

CAUTION




!

LED (green) Indicates that a cartridge is in the cartridge drive.(red) Indicates that the cartridge is in use.(unlit) Indicates that there is no cartridge in the cartridge drive.

E LAN Fail LED (yellow)Indicates the operations controller cannot communicatethrough the Ethernet port. The LED is software controlled.

CNet Fail LED (yellow)Indicates the operations controller cannot communicatethrough the CNet port. The LED is software controlled.

Active LED (green)The circuit pack should not be removed while this LED is lit.The LED is software controlled.

Fail LED (red)Indicates a circuit pack failure. The LED is hardware- orsoftware-controlled.



Interfaces supported by the OPC OS interfaces The OPC software supports communications between the network-level operations systems (OSs) and the network elements in the subnetwork.

User interfaces The OPC software supports both a graphical user interface and a character-mode user interface. The multiple-window graphical user interface is mouse driven and requires the use of an X-terminal. The character-mode user interface is window based and requires the use of a VT100 terminal. Using the NE Login Manager tool, the OPC can display the network element user interface session on any network element within the span of control of the OPC.

The multiple-window graphical interface allows the user to perform operations at the network element level from the network element user interface in one window, while simultaneously monitoring all alarms on the network from the network surveillance OPC tool in a second window.

OPC GUIThe operations controller graphical user interface (OPC GUI) is a PC-based software application that runs on Windows 95. Release 1.01 software can be used with OC-12 and OC-48 OPCs. The software simplifies use of the OPC by emulating a VT100 character mode terminal (CMT), and providing a point-and-click user interface.

The point-and-click user interface performs the same actions as keypad and keyboard commands. Users can navigate through the OPC tools using the point-and-click interface, or the keypad and keyboard commands of the OPC user interface.

The OPC GUI is intended for day-to-day maintenance activities. The application is not intended for software upgrades and system reconfigurations.

User access and security at the OPC The OPC software provides user-management functionality. User management includes functions such as the creation of authorized users of the OPC, the creation and maintenance of user groups, and security checking that occurs when a user signs on to use the OPC or tries to access a remote network element from the OPC.



Subnetwork-wide OAM&P services at the OPC The OAM&P software running in the OPC makes it possible for a user working at a central location to control all the network elements in the subnetwork by means of the CNet local area network, the processor circuit pack, and the SONET overhead channels. Using the OPC, a user can perform subnetwork-wide OAM&P functions. Some of the functions supported by this OAM&P software are:

• system lineup and test (SLAT) testing

• OPC operations, administration, and maintenance

— OPC performance-monitoring service

— OPC data collector

— performance monitoring (of the performance of the OPC)

— fault management (for the OPC)

— OPC application-configuration-management service (controls parameters that refer to operation of the OPC)

• configuration and maintenance of the subnetwork

• maintaining an inventory of components in each network element

• recording and reporting of alarms, logs and performance-monitoring data from all network elements:

— performance analysis for all network elements

— fault detection and reporting for all network elements

— software management (provisioning) and recovery

Software management functions of the OPC The software management functions performed by the OPC include initial software loading, recovery, and upgrades.

The OPC module has a hard disk that stores master copies of the software used in all the network elements of the subnetwork. Whenever a processor in a network element needs a software load, such as after a failure, the software is downloaded to the processor from the OPC by means of the CNet, the Proc, and the SONET overhead.

Equipping rules for the OC-12 or OC-3 shelf The OPC module occupies four slot positions (Figure 1-43). In an OC-12 or OC-3 TBM shelf, the OPC can be installed in slots 1-4, 5-8, 11-14, 15-18, or 16-19 depending on the shelf configuration and with a corresponding loss of tributary traffic.



To maintain full tributary traffic in a shelf, an OPC can be located in a control shelf. A control shelf is a terminal shelf with no transport or tributary interfaces. A control shelf must be connected to a network element with transport interfaces, using a CNet cable. In a control shelf, the OPC can be installed in slots 1-4, 5-8, 9-10, 11-14, 15-18, or 16-19.

Although 1:1 OPC protection is not a requirement, it is recommended that two OPCs be ordered for every 34 OC-12 or OC-3 shelves within a system.

Figure 1-43Operations controller module installed in the TBM shelf

FW-1926.3 (Vol1)

Processor circuit pack (NT4K52)The processor (Proc) circuit pack is a circuit pack that is installed in the lower level of the TBM shelf. It is the main processor of the OC-12 or OC-3 shelf. It provides central control functions for the shelf (see Figure 1-44). Every TBM shelf contains one processor circuit pack.

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

OP

C

30 32 34 36 38 40 42 44 46 48 50 52 54 55

IN IN

OUT OUT

Operations Controller(NT7E24)

OP

C

OP

C

OP

C

Note: The OPC can be installed in slots 1-4, 5-8, 11-14, 15-18, or 16-19 of an OC-3/OC-12TBM shelf depending on the shelf configuration and with corresponding loss of tributary traffic.

OP

C



Note: Both the NT4K52BB and NT4K52BC processor circuit packs can be used in linear ADM, ring ADM, and terminal applications.

Functional description The principal functions performed by the processor circuit pack are:

• host communications

• operations, administration, and maintenance (OAM)

The processor circuit pack contains two microprocessor-based functional blocks: the access processing unit (APU) and the host messaging unit (HMU).

APUThe APU contains the 68030-based microprocessor running at 24 MHz, and is responsible for all low-level external interfacing functions.

The APU contains up to 16 Mbytes of dynamic random access memory (DRAM). To minimize the possibility of a system failure due to a memory fault, error detection and correction (EDAC) is used for protection. During each DRAM refresh cycle, one memory location is read, corrected, and written back to memory. This process is called scrubbing. The entire memory is scrubbed every 4 minutes.

The 128-kbyte EEPROM contains basic firmware for APU initialization, and firmware that is specific to S/DMS TransportNode such as basic diagnostics and initialization routines. The EEPROM is expandable to 256 kbytes.

The APU interfaces to both of the control buses (CBuses) in a TBM shelf, to enable the processor circuit pack to control all the circuit packs that are installed in the TBM shelf. All the circuit packs that are installed in the shelf are accessible over one or the other of the CBuses. The processor circuit pack is the only circuit pack that connects to both CBuses.

The APU can perform 16-bit and 8-bit wide data transfers over each CBus. The CBus is compatible with the MBus, so the APU provides an MBus interface to all shelf circuit packs that use the MBus.



Figure 1-44Block diagram of the processor circuit pack

FW-1943

HMU The host messaging unit (HMU) manages the high level messaging interfaces in the processor circuit pack. The local area control network (CNet) and the SONET overhead bus (SOH) interfaces are managed directly by the HMU. Messages exchanged over the shelf CBuses are controlled through the APU.

The HMU contains a Motorola 68302 microprocessor, which controls access to 2 Mbytes of dynamic random-access memory (DRAM). To enable the HMU and the APU to perform their tasks simultaneously, the HMU has its own bus. All the functions controlled and maintained by the HMU are accessible by way of this bus.

ClockGenerator

Four-portbuffer

APU Bus

PUPS-48V+5V

+12V

Memory(DRAM)

Shelfbackplane

ID

HMU Bus

APUProcessor

Shelf ID

CBus AInterface CBus A

CBus BInterface CBus B

Memory(DRAM)

CNetInterface CNet bus

SONETOverheadInterface

SONETOverhead bus

HMUProcessor



Bus connections CBus The processor circuit pack is connected to the control bus (CBus). The CBus is the means by which the processor accesses all the circuit packs in the TBM shelf for maintenance and circuit pack diagnosis.

SOH bus The processor circuit pack is connected to each SONET overhead bus (SOH bus) in the shelf. In a shelf, there is one SOH bus for each optical interface circuit pack. Each SOH bus links the optical interface circuit pack to the processor circuit pack. The SOH bus carries the SONET data communications channel, which includes the section data communications channel and the line data communications channel. The SOH bus also carries orderwire channels.

Note: Other channels are available on the SOH bus, but those channels are not used by S/DMS TransportNode.

Point-of-use power supply (PUPS) A 30-W PUPS converts -48 V into +5 V, +12 V, -4.5 V, and -12 V. The PUPS module is protected by a 2-A fuse on the circuit pack.



Physical appearance of the processor circuit pack The processor circuit pack is 29.2 cm (11.5 in.) high by 25.8 cm (10.15 in.) deep. It is 2.5 cm (1 in.) wide. Figure 1-45 shows the front view of the processor circuit pack.

Figure 1-45Front view of the processor circuit pack

FW-0125

Fail

Active

Active LED (green)Indicates the shelf processor has booted properly and is processing information.The circuit pack should not be removed while this LED is lit.The LED is software controlled.

Fail LED (red)Indicates a shelf processor component failure, that initialization is under way, orthat initialization has failed. The LED is either software or hardware controlled.



Equipping rules for the OC-12 or OC-3 shelf Figure 1-46 shows the processor circuit pack in slot 21 of an OC-12 or OC-3 shelf.

Figure 1-46Processor circuit pack Installed in the TBM shelf

FW-1926.4-Vol1

Power termination circuit pack (NT4K58) The power termination (PWR) circuit pack interfaces the -48 V local battery feed to the TBM shelf. The power cables from the breaker interface panel (BIP) plug into the front of the PWR circuit pack. For protection, two PWR circuit packs are installed.

Equipping rules for the OC-12 or OC-3 shelf In both the OC-12 and OC-3 shelves, PWR circuit packs are installed in slots 54 and 55. Figure 1-47 shows the location of the circuit packs, on a TBM shelf.

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

Pro

c

30 32 34 36 38 40 42 44 46 48 50 52 54 55

IN IN

OUT OUT

Processor Card(NT4K52)



Figure 1-47Power termination circuit packs installed in the TBM shelf

FW-1922

Side interconnect left circuit pack (NT4K50BA) Cabling enters the transport bandwidth manager (TBM) shelf on the left side of the shelf, at the side interconnect left (SIL) circuit pack. Figure 1-48 identifies the connector layout and indicates the cable codes associated with each connector.

The side interconnect left (SIL) circuit pack is not a field-replaceable unit. It is considered part of the backplane.

CAUTIONRisk of traffic lossRemoving the SIL circuit pack can cause failure of transport and tributary optics. If you suspect the SIL connectors are defective, contact your next level of support or your Nortel Networks support group.

10 32 54 76 98 10 11 1312 1514 1716 1918 2120 22 23

SIL

OC-12G1

OC-12G2

30 32 34 36 38 40 42 44 46 48 50 52 54 55

Pw

r A

Pw

r B

IN IN

OUT OUT



Figure 1-48Connectors on the side interconnect left circuit pack

FW-1908 (R9)

AccessBIPJ14

External SyncJ13

ParallelTelemetryJ12

CNETJ11

User InterfacePort 1J10

OPC Port 1J09

Serial TelemetryPorts 1-4J08

OPC Port 2J07

CO AlarmsJ06

OrderwireExtensionJ05

CNETJ02

UnusedJ01

LCAPInterfaceJ04

CoolingUnitInterfaceJ03

44-pin

44-pin

44-pin

25-pin

25-pin

25-pin

25-pin

25-pin

25-pin

25-pin

9-pin

9-pin

9-pin

9-pin

NT4K86EA

NT4K85GA/GB/GC

NT7E44JA/JB/JC/JK(SONET DCC Bridge)

NT7E44EA/EB

NT7E44RA/RB/SA/SB/QA/QB/EA/EB

NT4K86CA(E2A-TBOS)

NT4K85CA/CB/CC

NT7E44JA/JB/JC/JK(SONET DCC Bridge)

Associated cable codes

NT7E5650/51/52

NT4K85RA

NT4K85JA/JC(see Note)

NT7E44UA

NT7E44XA/XB

Note: If a TBM shelf is equipped with a COP cooling unit (NT4K19AC) in shelf position 3, the COP cooling unit alarm cable (NT7E7802 ) is used to connect the cooling unit interface (J03) to the COP cooling unit alarm interface connector.


SONET Transmission Products

S/DMS TransportNode OC-3/OC-12 NE—TBM Circuit Pack Descriptions

Copyright 1992–2001 Nortel Networks, All Rights Reserved

The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose it only to its employees with a need to know, and shall protect it, in whole or in part, from disclosure and dissemination to third parties with the same degree of care it uses to protect its own confidential information, but with no less than reasonable care. Except as expressly authorized in writing by Nortel Networks, the holder is granted no rights to use the information contained herein.

Nortel Networks and S/DMS TransportNode are trademarks of Nortel Networks. VT100 is a trademark of Digital Equipment Corporation. UNIX is a trademark of X/Open Company Ltd.

323-1111-102 Rel 14 Standard February 2001Printed in Canada

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