Something about Asymmetry,Happex

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Something about Asymmetry,Happex Pengjia 2/8/2012

description

Something about Asymmetry,Happex. Pengjia 2/8/2012. Asymmetry test Diagram. Injector. Counting House. Pockels Cell HV. Helicity Board. Pair Sync. output. Delayed Helicity. QRT. change. MPS. Circular polarization of laser light. Fiber. Undelayed Helicity. Happex Crate. - PowerPoint PPT Presentation

Transcript of Something about Asymmetry,Happex

Page 1: Something about  Asymmetry,Happex

Something about Asymmetry,Happex

Pengjia 2/8/2012

Page 2: Something about  Asymmetry,Happex

Asymmetry test Diagram

Injector

Helicity BoardPockels Cell HV

Circular polarization of laser light

Spin of photo-emitted electrons

Counting HousePair Sync

Delayed Helicity

QRT

MPS

Happex Crate

change

change

output

Fiber

Moller

Compton

Left ArmHappex Crate

SIS3801 Scaler

Right ArmHappex Crate

SIS3801 Scaler

Third ArmSIS3801 Scaler

Helicity Board

Undelayed Helicity

V2F

Use undelayed helicity to generate a DAC signal with a known value of asymmetry

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Asymmetry test

•The result is consistent between two arm’s happex, scaler and moller•Chao will show the pictures in detail•Still can not understand why it is not consistent during commission between hall A scaler with hall C and moller(hall A scaler,hall C,moller’s signal came from the same V2F)

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bcm signal split problem

Left Happex Crate

Right Happex CrateV2F

Left arm Scaler Right arm Scaler 3rd arm Scaler

moller Hall C feedback MCC feedback

……

BCM electronic

Page 5: Something about  Asymmetry,Happex

Will reduce asymmetry resolution ….

Just connect to 1 happex ADC Copy to 2 happex ADC

Copy to 1 happex ADC and 1 V2F Copy to 2 happex ADC and 1 V2F

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reflection signal from happex and V2F

reflection from happex reflection from V2F

reflection from happex and V2F

Use pulser to check

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Happex DAQ improvement

Pulling Trigger interrupt

Before Right now

97% of cpu occupyNeed to set system clock rateCpu is easy to crash

18% of cpu occupyDon’t need to set clock rateCpu is more stable

Page 8: Something about  Asymmetry,Happex

Happex DAQ Settings Before

TimingBoard

HAPPEXADC

FLEXIO

MPS

VXWORKS CPU

trigger

trigger

Pair Sync

QRT

Helicity no

yes

RingBuffer Server

Read Flexio

Extract Pair Sync

pair sync changed?

Delay 0.x ms

Read ADC

Check&Predict Helicity

Write to RingBuffer

TCP- IP Server

Ring Buffer

Linux

TI

HRSTrigger

Superviser

T1,…,T8trigger

CODA

Event Builder

Event Recoder

control

Read

*.dat

OtherROCs & TIs

Page 9: Something about  Asymmetry,Happex

Happex DAQ Settings Right now

TimingBoard

HAPPEXADC

FLEXIO

MPS

VXWORKS CPU

trigger

trigger

Pair Sync

QRT

Helicity no

yesRingBuffer Server

Read ADC,Flexio

Write to RingBuffer

TCP- IP Server

Ring Buffer

Linux

TI

HRSTrigger

Superviser

T1,…,T8trigger

CODA

Event Builder

Event Recoder

control

Read

*.dat

OtherROCs & TIs

BaseLine

trigger

trigger