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Software Design Challenges for heterogenic SOC's1 There’s always a Logic Solution! Software Design...
Transcript of Software Design Challenges for heterogenic SOC's1 There’s always a Logic Solution! Software Design...
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There’s always a Logic Solution!
Software Design Challenges for heterogenic SOC'sRené Janssen, Product manager Logic Technology
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There’s always a Logic Solution!
Agenda
1. Advantages of heterogenous devices
2. How to manage inter-processor communication
3. Example Hardware setup demo snapshots
4. Summary
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ARM architecture for diverse computing needs
Cortex-AHighest performance
Optimized for rich operating systems
Cortex-RFast response
Optimized for high performance,
hard real-time applications
Cortex-MSmallest/lowest power
Optimized fordiscrete processing and
microcontrollers
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Modern compute systems have diverse workloads
Power
Time
Sleep mode
Interactive mode
Ambient mode
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Why heterogeneous devices?
Cortex-A benefits• Feature rich OS• Complex
applications• Sophisticated
HMI
Cortex-M benefits– Low I/O latency– Low power
standby– Fast system
start-up time
Linux application RTOS applicationInter-processor communication
Combines best of both worlds: feature-rich Linux and MCU with deterministic RTOS
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Use cases of HMP systems in embedded
Cortex-A Rich UI and OS, high performance
Cortex-M Real-time control and monitoring
Deterministic sensor control
Real-time monitoring
MedicalConsumerIndustrial
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Overview of software challenges
Developer productivity
Usability, portability, debugging
Data sharing
Is coherency necessary?
Taskpartitioning
How to optimally partition tasks?
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Software development challenges
• Running multiple operating systems
• Debugging bare-metal code and Linux applications at the same time
• Controlling communication between Linux application and bare-metal application
Linux application MCU
application
Common peripherals
Shared memory
ARMCortex-A7
Inter-processorcommunication
ARMCortex-M4
Linux OS
Complexity increases with heterogeneous devices
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Software development challenges
• Requires to write a Linux kernel module
» Memory segmentation
» Manage concurrency
» Kernel mode to User mode communication
• Bare-metal
» Manage concurrency
» Integration with RTOS
» Handle interrupts and memory management
Shared memory
ARMCortex-A7
ARMCortex-M4
Linux OS
Kernel module
Linux application
MCU application
Manually manage communication between Cortex-A and Cortex-M
Common peripherals
IPC
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Software development challenges
• CMSIS adopting OpenAMP
» CMSIS - Cortex Microcontroller Software Interface Standard
» Open source on Github
• OS support for HMP systems
» Remote Processor Messaging (RPMsg) for inter-processor communication
» Management framework using remoteproc
Standardization of software interfaces
Shared memory
ARMCortex-A7
ARMCortex-M4
Linux OS CMSIS-RTOS
RPMsg module
Linux application
MCU application
Common peripherals
RPMsg library
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Resource Domain Controller (RDC)
• Improve security by assigning peripherals to different domains
• Reduce risk of concurrent access to peripherals
ARMCortex-A7
ARMCortex-M4
#define BOARD_DEBUG_UART_RDC_PDAP rdcPdapUart2#define M4_DOMAIN_ID 1…/* Set UART2 for M4 core domain access only */RDC_SetPdapAccess(RDC,
BOARD_DEBUG_UART_RDC_PDAP,3 << (M4_DOMAIN_ID * 2),false, false);
UART2
RDC
Access (R/W) Access (R/W)
Example code
Domain 0 Domain 1
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Inter-processor communication
NXP i.MX7
Shared memory
ARMCortex-A7
ARMCortex-M4
Linux kernel CMSIS-RTOS2
RPMsgmodule
Linux application
MCUapplication
Virtual pipe RTX5/FreeRTOS
/dev/ttyRPMSG
RPMsg libraryrpmsg_rtos_init()rpmsg_rtos_recv…()rpmsg_rtos_send…()
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Inter-processor communication
• Virtio provides virtqueue API that allows user drivers to transmit and receive data with the communicating counterpart using the vring structure.
• Vring is a buffer management component
» Ring data structure to manage buffer descriptors located in shared memory.
• Inter-Processor Interrupts is used for notifications
Ref: https://github.com/OpenAMP/open-amp/wiki/OpenAMP-RPMsg-Virtio-Implementation
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Inter-processor communication
Measurement of round-trip time
0
200
400
600
800
1000
1200
0 50 100 150 200 250 300 350 400 450Tim
e (
µs)
Packet size (bytes)
RPMsg round-trip time
Linux application
MCUapplication
Ping
Ack
50 µsSetup time
~1Mb/sBandwidth
Performance
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Typical Hardware setup
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The Art of Embedded Systems Development – made Easy™
Embedded Artists in a Nutshell
• NXP, ARM based Computer-on-Module solutions.
• A family of pin-compatible boards.
• Industrial focus, with 10+ years longevity.
• A Proven Partner to NXP.
• High quality technical support directly from our engineers.
• The Art of Embedded Systems Development – made EASY™
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The Art of Embedded Systems Development – made Easy™
iMX Developer’s Kits
• Flexible hardware platforms…
• Documentation and guides…
• High quality support…
…to get up-and-running quickly!
…for Prototypes and Proof-of-concepts!
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The Art of Embedded Systems Development – made Easy™
Development board
• iMX7 Dual Developer’s Kit
» 1 GHz dual-core Cortex-A7 (and 200 MHz Cortex-M4)
» 1 GByte DDR3L RAM
» 4 Gbyte eMMC Flash
» One Gigabit Ethernet interface
• To get started with an iMX Developer’s Kit
» http://www.embeddedartists.com/com_getting_started
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Development environment
PowerEthernet
JTAG-10
USB orEthernet
Power
UARTs(via FTDI cables)
Embedded Artists IMX7D Developer Kit + Arm DSTREAM-STReset button
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Multiple simultaneous debug connections
JTAG
TCP/IP
• The Cortex-M application via DSTREAM and analyse with RTOS awareness and peripheral views.
• The Cortex-A Linux kernel and Linux kernel modules via DSTREAM and list kernel threads and processes.
• The Cortex-A Linux application via gdbserver on the running Linux system using Remote System Explorer.
Complete visibility to all software applications in the heterogeneous system
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Coresight debug interface
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There’s always a Logic Solution!
I.mx7 Debug interface
The i.MX7D debug is based on ARM’s CoreSight “HUGO” platform, with support for Cortex-A7 and Cortex-M4 core from ARM.
• Support 5-pins (JTAG), 2-pins (cJTAG, ARM SWD) interface
• Support both non-intrusive and halt-mode trace / debug options
• MDM-AP registers for debugger to control mutli-core halt / resume cores
• Trace Memory Controller (TMC) is used to enable capturing trace» 4 KB in SOC trace block» ETR (4 G memory range, 64-bit wide at 266 MHz) is used to allow routing tracedata to system
memory
• Support ARM real time trace interface: TPIU (16-bit x 133 MHz)
• Support cross trigger between CA7 and CM4
• Four JTAG security levels, via SJC security functions together with e-Fuse(challenge response, field return, intrusive detection
Source : i.MX 7Dual Applications Processor Reference Manual, Rev. 0.1, 08/2016
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Demo
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Demo
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There’s always a Logic Solution!
Q & A
Do you have any questions?
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Thank you for your attention
See you at the Logic Technology stand