soc
Transcript of soc
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Training Course of SOC Training Course of SOC EncounterEncounter
REF: • CIC Training Manual – Cell-Based IC Physical Design and Verification with SOC Encounter, July, 2006• CIC Training Manual – Mixed-Signal IC Design Concepts, July, 2007g g g p , y,
Speaker: T. –W. Tsengp g
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Outline
Basic Concept of the Placement & RoutingAuto Place and Route Using SOC EncounterAuto Place and Route Using SOC EncounterHard Block Abstraction Using Abstract GeneratorLABLAB
Advanced Reliable Systems (ARES) Lab.
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Basic Concept of the Placement & RoutingRouting
Advanced Reliable Systems (ARES) Lab.
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Cell-Based Design Flow
MATLAB/ C/ C++/ System C/ ADS/ Covergen (MaxSim)
Memory Generator
Spec.
System LevelADS/ Covergen (MaxSim)
NC-Verilog/ ModelSimDebussy (Verdi)/ VCS
Verilog/ VHDL SyntestRTL Level
Design/ Power Compiler
DFT Compiler/ TetraMAX
mpi
ler/
Fusi
on
Conformal/Formality
Logic Synthesis
Design for Test
NC-Verilog/ ModelSimDebussy (Verdi)/ VCS
hysi
cal C
omgm
a B
last
Gate Level
SOC Encounter/ Astro
DRC/ LVS (Calibre)
Ph Mag
GDS IILayout Level
Post-Layout Verification
PVS: Calibre xRC/ NanoSim(Time/ Power Mill)
Verification
Advanced Reliable Systems (ARES) Lab.
Tape Out
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SOC Encounter P&R Flow
Clock TreeIO, P/G Netlist (Verilog)Ti i C t i t ( d )
SpecifyFloorplan
Synthesis
TimingAnalysis
, /Placement
Timing Constraints (sdc)IO Constraints (ioc)
Floorplan
TimingAnalysis
Analysis
Post-CTSOptimization
Pre-CTS Optimization
PowerRoute
PowerPlanning
SI DrivenRoute
GDSPower
AnalysisTiming/SIAnalysis
GDSNetlistSpefDEF
Advanced Reliable Systems (ARES) Lab.
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IO, P/G Placement
Determine the positions of the PADs Corner1 I1 VDD O1 Corner2
Functional IO PADPower/Ground PADCorner PAD I2 O2Corner PAD
Just for the connection of PAD power rings
I2
IOVDD
O2
IOVSSpo e gs
I3
IOVDD
O3
IOVSS
I3 O3
Corner3 Corner4I4 VSS O4
Advanced Reliable Systems (ARES) Lab.
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Specify Floorplan
Determine the aspect ratio of the Core and the gap between the PAD and Core
The Core UtilizationThe Core Utilization is determined in this stepThe final CHIP areaThe final CHIP area is almost determined in this step
Hight
Width
Advanced Reliable Systems (ARES) Lab.
Width
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Floorplan
Determine the related positions of Hard Corner1 I1 VDD O1 Corner2
BlocksThe performance is highly affected I2 O2g y I2
IOVDD
O2
IOVSS
M2
I3
IOVDD
O3
IOVSS
M3M1I3 O3
Corner3 Corner4I4 VSS O4
Advanced Reliable Systems (ARES) Lab.
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Amoeba Placement
Observe the result of cells and Hard Blocks placement
Advanced Reliable Systems (ARES) Lab.
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Power Planning
Plan the power ring & power stripe
IR-drop consideration
Advanced Reliable Systems (ARES) Lab.
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Clock Tree Synthesis
CLK CLKCLK CLK
Advanced Reliable Systems (ARES) Lab.
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Power Analysis
IR-drop & electron migration
Advanced Reliable Systems (ARES) Lab.
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Power Route
Connect the power pins of standard cells to the global power lines
Advanced Reliable Systems (ARES) Lab.
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Add IO Filler
Fill the gap between PADs
Connect the PAD power ringsg
Advanced Reliable Systems (ARES) Lab.
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Routing
Construct the final interconnections
Advanced Reliable Systems (ARES) Lab.
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Prepare DataLibrary
Physical Library (LEF)Information of technology, standard cells, Hard Blocks, and APR
Timing Library (LIB)Timing information of the standard cells and Hard BlocksTiming information of the standard cells and Hard Blocks
Capacitance TableFor more accurate RC analysis
Celtic LibraryCeltic LibraryFor crosstalk analysis
FireIce/Voltage Storm Library
Not Necessary !
For RC extraction and power analysis
User DataGate Level Netlist (Verilog)Gate-Level Netlist (Verilog)SDC Constraint (*.sdc)IO Constraint (*.ioc)
Advanced Reliable Systems (ARES) Lab.
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LEF Format – Process Technology
Layers Design Rule Parasitic
POLY
Contact
Net WidthNet SpacingArea
ResistanceCapacitance
Metal 1
ContactEnclosureWide Metal SlotAntenna
l 2
Via1Current Density
Metal 2
Advanced Reliable Systems (ARES) Lab.
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LEF Format – Process Technology: Layer Define
Layer Metal1TYPE ROUTING;WIDTH 0.28;MAXWIDTH 8;
WidthWide Metal Spacing
MAXWIDTH 8;AREA 0.202;SPACING 0.28;SPACING 0.6 RANGE 10.0 10000.0;
Wide Metal
PITCH 0.66;DIRECTION VERTICAL;THICKNESS 0.26;ANTENNACUMDIFFAREARATIO 5496
Spacing
ANTENNACUMDIFFAREARATIO 5496;RESISTANCE RPERSQ 1.0e-01;CAPACITANCE CPERSQDIST 1.11e-04;EDGECAPACITANCE 9 1e-05;EDGECAPACITANCE 9.1e 05;
END Metal1
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology
UnitSiteSiteRouting PitchDefault DirectionDefault DirectionVia Rule
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology: Site
The placement site gives the placement grid of a family of macros
a row a sitea standard cella standard cell
Advanced Reliable Systems (ARES) Lab.
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Row Based PR
VDD
VSS
VDD
VSS
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology: Routing Pitch, Default Direction
Metal1 Routing Pitch
ViaVia
Metal2 Routing Pitch HorizontalRouting
VerticalRouting
Metal1 Metal2Metal1Metal3Metal5
Metal2Metal4Metal6
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology: Via Generation
To connect the wide metal, a via array is generated to reduce the via resistancereduce the via resistanceFormulas for generating via arrays are defined
Layer Metal1Direction HORIZONTALOVERHANG 0.2
Layer Metal2
Default Via
Layer Metal2Direction VERTICALOVERHANG 0.2
Layer Via1RECT -0.14 -0.14 0.14 0.14SPACING 0.56 BY 0.56
Generated Via
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology: Same Net Spacing
SPACING VIA12 and VIA23SAMENET Metal1 Metal1 0.23;SAMENET Metal2 Metal2 0.28 STACK;SAMENET Metal3 Metal3 0.28;SAMENET VIA12 VIA12 0 26;
Metal1 Metal3
SAMENET VIA12 VIA12 0.26;SAMENET VIA23 VIA23 0.26;SAMENET VIA12 VIA23 0.0 STACK;
END SPACING
VIA12 and VIA23 allow stack
Metal1Metal1
0.23 Same Net Spacing Rule
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology: Physical Macros
Define physical data forStandard cellsStandard cellsI/O padsMemoriesOther hard macros
Describe abstract shapeSizeClassPinsPinsObstructions
Advanced Reliable Systems (ARES) Lab.
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LEF Format – APR Technology: Physical Macros (Cont’)
MACRO ADD1CLASS CORE;Metal CLASS CORE;FOREIGN ADD1 0.0 0.0;ORIGEN 0.0 0.0;LEQ ADD;
VDD
SIZE 19.8 BY 6.4;SYMMETRY x y;SITE coresite;PIN A
Y
PIN ADIRECTION INPUT;PORTLAYER Metal1;
BA
LAYER Metal1;RECT 19.2 8.2 19.5 10.3;….ENDVSS Barrier
END A….END ADD1
Advanced Reliable Systems (ARES) Lab.
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LIB Format
Operating conditionSlow fast typicalSlow, fast, typical
Pin typeInput/output/inoutInput/output/inoutFunctionData/clockCapacitance
Path delayTiming constraint
Setup, hold, mpwh, mpwl, recovery
Advanced Reliable Systems (ARES) Lab.
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Gate-Level Netlist
If designing a chip, IO PADs, power PADs, and Corner PADs should be added before the netlist is importedPADs should be added before the netlist is importedMake sure that there is no “assign” statement and no “*cell*” cell name in the netlist
Advanced Reliable Systems (ARES) Lab.
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SDC Constraint
Clock constraintsInput delay/ Input driveInput delay/ Input driveOutput delay/ Output loadFalse pathFalse pathMulti-cycle path
Advanced Reliable Systems (ARES) Lab.
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IO Constraint
Version: 1Pad: CORNER0 NW PCORNERDGZPad: PAD_CLK NPad: PAD_HALT N
CORNER0 CORNER1
PA
D_
CLK
PA
D_
HA
LT
Pad: CORNER1 NE PCORNERDGZPad: PAD_X1 WPad: PAD X2 W
CORNER0 CORNER1
PAD X2 PAD VSS1
T
N
_
Pad: CORNER2 SW PCORNERDGZPad: PAD_IOVDD1 S PVDD2DGZ
PAD_X2 PAD_VSS1
PAD_X1 PAD_VDD1
W E
Pad: PAD_IOVSS1 S PVSS2DGZ
Pad: CORNER3 SE PCORNERDGZPad: PAD VDD1 E PVDD1DGZ
PA
D_
IO
PA
D_
IO
S
Pad: PAD_VDD1 E PVDD1DGZPad: PAD_VSS1 E PVSS1DGZ CORNER2 CORNER3
OV
DD
1
OV
SS
1
(*.ioc File)
Advanced Reliable Systems (ARES) Lab.
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How To Decide the NO. of Power/Ground PADs
The following factors are considered:SSO: Simultaneously Switch OutputsSSO: Simultaneously Switch OutputsSSN: The noise produced by SSO buffersDI: Maximum NO. of copies for one specific kind of IO PAD switching from high to low simultaneously without making ground voltage level higher than 0.8 volt for one ground PADDF: Driving Factor DF = 1/DIDF: Driving Factor, DF 1/DISDF: Sum of Driving Factor
Suggestion in SSO case:ggRequired NO. of ground PADs = SDFRequired NO. of power PADs = SDF/1.1
Advanced Reliable Systems (ARES) Lab.
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SDF Example
IO Type 2mA 4mA 8mA 12mA 16mA 24mAIO Type 2mA 4mA 8mA 12mA 16mA 24mADF Value 0.02 0.03 0.09 0.18 0.3 0.56
If a design has 20 PDB02DGZ (2mA) and 10 PDD16DGZ (16mA) Then(16mA). Then, SDF = 20 x 0.02 + 10 x 0.3 = 3.4In SSO caseIn SSO case,
NO. of VSS PAD = 3.4 4NO. of VDD PAD = 3.4/1.1 = 3.09 4
Advanced Reliable Systems (ARES) Lab.
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Tips to Reduce the Power/Ground Bounce
Don’t use stronger output buffers than what is necessaryUse slew-rate controlled outputspPlace power pad near the middle of the output bufferPlace noise sensitive I/O pads away from SSO I/OsPlace VDD and VSS pads next to clock input buffer
Advanced Reliable Systems (ARES) Lab.
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Auto Place and Route Using SOC o o gEncounter
Advanced Reliable Systems (ARES) Lab.
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CHIP-Level NetlistIf your gate-level netlist is generated by “CORE-level synthesis”, you should all
Ex:
y , ythe “CHIP-level module” in it
Advanced Reliable Systems (ARES) Lab.
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CHIP-Level Netlist (Cont’)If your design has a “Hard Block”, you should add an “empty module” for it
the module name should be the same as the “cell name” of the Hard
Ex:
the module name should be the same as the cell name of the Hard Block
Ex:
(Module Declaration)
(Module Reference)
Connected Wire Name in Verilog
i i
Connected Wire Name in Verilog
Advanced Reliable Systems (ARES) Lab.
Pin Name in SPICE
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CHIP-Level Timing ConstraintEx:
CHIP-Level Clock Declaration
Set False Path to Your Test Pins
Set Parameters to the PAD IO
Advanced Reliable Systems (ARES) Lab.
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Getting Started
linux %> ssh -l “user name” cae18.ee.ncu.edu.twunix %> source /APP/cad/cadence/SOC/CIC/soc.csh
Connect to Unix
%unix %> encounter
(Do not run in the background mode !!)
Advanced Reliable Systems (ARES) Lab.
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Import Design <Design>
Design/Design ImportVerilog Files: your gate-level netlistg y gTot CellLEF Files (*.lef): including all the LEF fil f ll lib i & h d bl kfiles of cell libraries & hard blocksLIB Files (*.lib):
Max Timing LibrariesMax Timing LibrariesMin Timing LibrariesCommon Model Libraries
IO A i Fil * iIO Assignment File: *.ioc
Advanced Reliable Systems (ARES) Lab.
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Import Design <Timing>Capacitance Table FileTiming Constraint File: *.sdc
Advanced Reliable Systems (ARES) Lab.
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Import Design <Power> <IPO/CTS>
Power NetsGround NetsF i f I PlFootprints for In-Place Layout Optimization (IPO) and Clock Tree Synthesis (CTS)(CTS)
Advanced Reliable Systems (ARES) Lab.
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Import Design <Misc.>
QX Tech FileQX Library DirectoryQ y y
(Floorplan View)Advanced Reliable Systems (ARES) Lab.
(Floorplan View)
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Global Net ConnectionFloorplan/Global Net Connections
Advanced Reliable Systems (ARES) Lab.
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Specify FloorplanFloorplan/Specify Floorplan
COREArea
Advanced Reliable Systems (ARES) Lab.
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Specify Scan Chainencounter %> specifyScanChain ScanChainName
- start {ftname | instPinName} - start {ftname | instPinName}
encounter %> scantrace
Ex:
(result)
Advanced Reliable Systems (ARES) Lab.
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Hard Block PlacementMove/Resize/Reshape floorplan object
Advanced Reliable Systems (ARES) Lab.
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Edit Block HaloFloorplan/Edit Block HaloReserve space without standard cell placement
Advanced Reliable Systems (ARES) Lab.
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Standard Cell PlacementPlace/Place
Advanced Reliable Systems (ARES) Lab.
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Power Planning – Add RingsFloorplan/Custom Power Planning/Add Rings
Advanced Reliable Systems (ARES) Lab.
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Power Planning – Add Block RingsFloorplan/Custom Power Planning/Add Rings
Advanced Reliable Systems (ARES) Lab.
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Example for Power Rings
Advanced Reliable Systems (ARES) Lab.
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PAD PinsRoute/SRoute
Advanced Reliable Systems (ARES) Lab.
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Power Planning – Add StripesFloorplan/Custom Power Planning/Add Stripes
Advanced Reliable Systems (ARES) Lab.
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Power Planning – Add Stripes (Cont’)
Ex:
Advanced Reliable Systems (ARES) Lab.
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Fix Un-Connected StripesRoute/SRoute
Advanced Reliable Systems (ARES) Lab.
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Flow Clock Tree Synthesize
Create Clock Tree Spec
clock spec
Specify Clock TreeModify
Synthesis Clock Tree Netlist
i l Cl k
Netlist Synthesis report
Clock netsRouting guide
Display Clock Tree
Advanced Reliable Systems (ARES) Lab.
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Create/Specify/Synthesis Clock Tree Spec.Clock/Create Clock Tree Spec
Clock/Specify Clock Tree
Clock/Synthesis Clock Tree(Clock Spec.)
Advanced Reliable Systems (ARES) Lab.
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Example for CTS Report
Advanced Reliable Systems (ARES) Lab.
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Display Clock TreeClock/Display/Display Clock Tree
Ex:
Advanced Reliable Systems (ARES) Lab.
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Power AnalysisPower/Edit Pad Location Power/Power
Analysis/Statistical
Ex:
Power/Edit Net Toggle Probabilitygg y
(Power Analysis Report)Advanced Reliable Systems (ARES) Lab.
(Power Analysis Report)
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Example for Rail Analysis of IR-Drop & EM
(IR-Drop) (EM)
Advanced Reliable Systems (ARES) Lab.
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Power RouteRoute/SRoute
Advanced Reliable Systems (ARES) Lab.
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IO Fillerencounter %> source addIoFiller.cmd
Advanced Reliable Systems (ARES) Lab.
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Nano RouteRoute/NanoRoute
Advanced Reliable Systems (ARES) Lab.
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Example for Nano Route
Advanced Reliable Systems (ARES) Lab.
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Cell FillerPlace/Filler/Add Filler
Ex:Ex:
Advanced Reliable Systems (ARES) Lab.
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Save DesignDesign/Save/Netlist *.vTiming/Calculate Delay *.sdfDesign/Save/DEF * defDesign/Save/DEF .def
SELECT “Save Scan”
Advanced Reliable Systems (ARES) Lab.
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Bounding PADunix %> chmod 755 addbonding.plunix %> /usr/bin/perl addbonding.pl CHIP.defencounter %> source bondPads cmdencounter %> source bondPads.cmd
Ex:
Advanced Reliable Systems (ARES) Lab.
![Page 69: soc](https://reader033.fdocuments.in/reader033/viewer/2022052618/548c8028b47959c46f8b47a4/html5/thumbnails/69.jpg)
Save GDSIIDesign/Save/GDS *.gds
Advanced Reliable Systems (ARES) Lab.
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LAB
Advanced Reliable Systems (ARES) Lab.